CIRCUIT DESIGN

4.2.1 LNA

The proposed LNA circuit schematic is shown in Fig. 4.2. A three-stage LNA is used to provide sufficient gain to suppress the noise from the following circuit blocks.

The second and third stages of the LNA are implemented by conventional cascode structures where LLNA4 and LLNA6 are used to resonate with the parasitic capacitances at sources of MLNA3 and MLNA5 for higher gain and better noise performance. However, design of the first stage of the LNA is most critical because it dominates noise figure and input matching performances of the LNA. As shown in Fig. 4.2, a single

common-source transistor MLNA1 with source degeneration inductor LLNA2 and gate inductor LLNA1 are adopted as the first stage in the proposed LNA instead of the conventional cascade structure as shown in Fig. 4.3. This is because the noise performance of the cascade structure is degraded rapidly when the operating frequency is on the same order of the unit-gain frequency (fT) of the transistor. The degradation of the noise performance mainly results from two reasons. Firstly, the pole at drain of MLNA1 due to the parasitic capacitance Cp is typically on the order of fT

/2 [65]. When the operating frequency is well below fT, Cp can be neglected so most noise current of MCC, in in Fig. 4.3, is trapped in the loop p1 and does not affect the output voltage of this stage (i.e. drain of MCC). However, when the operating frequency is close to fT, a considerable portion of in flows from output node to ground along the path p2 as shown in Fig. 4.3. Thus, it produces noise voltage at output node, thereby degrading the noise performance. Secondly, Cp also lowers the LNA gain because it shunts a considerable portion of the RF signal current to ground. This raises the noise contributed by in and degrades the noise performance further.

Some ADS simulations using 0.13μm CMOS technology are performed to observe the noise performances in both structures. Fig. 4.4 shows the simulated minimum noise figures (NFmin) of the LNAs in Fig. 4.2 and 4.3. In the simulations, all devices in Fig. 4.3 have the same sizes as the counterparts in Fig. 4.2 and the additional NMOS Mcc in Fig. 4.3 has the same size as MLNA1. It can be observed that the NFmin increases 3.3 dB if Mcc is used. To find actual noise contribution from non-ideal effect of Mcc as mentioned before, Mcc in Fig. 4.3 is replaced by a noiseless current buffer with infinite fT in another simulation and the result is also shown in Fig.

4.4. It can be found that Mcc contributes NFmin of 4.6 dB and the NFmin of the proposed LNA in Fig. 4.2 is much closer to this ideal case with increase in NFmin of only 1.3

dB.

Another important design issue of an LNA is the input matching performance.

The Miller capacitor provided by the gate-to-drain parasitic capacitor of MLNA1

decreases after the resonance at drain node of MLNA1. This characteristic significantly extends the input bandwidth to cover the frequency after the resonance. Fig. 4.5 shows simulated S11 of the LNAs in Fig. 4.2 and Fig. 4.3. For a fair comparison, in the simulations, LLNA1 in Fig. 4.2 and Fig. 4.3 both are optimized for the input matching bandwidth, defined as the frequency range when S11 < -12dB, to cover the unlicensed band. From Fig. 4.5, by using the proposed LNA, the input matching bandwidth can be extended from 13 GHz to 23 GHz and the improvement is 76.9%.

In summary, when the operating frequency is on the same order of transistor fT, using a simple common-source structure as the first stage of an LNA has not only better noise performance but also a wider input matching bandwidth than using the conventional cascode structure. Therefore, it is a better choice to be adopted in a receiver for 60-GHz UWB applications.

4.2.2 Sub-Harmonic Mixer

Third-order sub-harmonic mixers are used in the proposed receiver to reduce the required LO frequency (e.g. 20-GHz LO signal for 60-GHz RF signal). Fig. 4.6 shows the circuit schematic of the proposed third-order sub-harmonic mixer. MMixer1 can be seen as a voltage buffer provided a capacitive load to the previous stage, i.e. LNA.

MMixer2 and MMixer3 are the differential common-gate amplifier whose transconductances are modulated by LO signals. As mentioned in Chapter 3, they dominate the frequency conversion. Because a high-gain stage follows the mixer and

provides enough gain, passive resistor are chosen as output load in this situation for wider baseband bandwidth. Moreover, it is very important to reduce LO-to-output leakage to prevent the saturation of the high-gain stage. Therefore, MMixer3 and MMixer4

whose sizes are equal to MMixer2 and MMixer3 are used to improve the LO-to-output isolation even their extra load effect slightly degrades gain and bandwidth. At the output node omixer+ (omixer -), the LO leakage from MMixer2 (MMixer3) can be cancelled by the opposite-phase leakage from MMixer4 (MMixer5). On the other hand, because the previous stage is a 3-stage LNA with good reverse isolation, the matching network reported in Chapter 3 is replaced NMOS current sources, MMixer6 and MMixer7. The current sources fix the output DC voltages which bias the following gain stages in the non-saturation operation region.

As mentioned in Chapter 3, the transconductance Gm(t) of MMixer2 or MMixer3 can be represented as

( )

(

)

(

)

(

)

G_{m m0 m1}cosω_{LO m2} cos 2ω_{LO m3}cos3ω_LO , (4.1)

where ωLO is the radian LO frequency. If the input voltage is vRFcos(ωRFt) where vRF

(ωRF) is the input RF voltage amplitude (radian frequency), the desired differential output mixing term VIF can be calculated as

( )

where gm1 is the small signal transconductance of MMixer1 and Rmixer is the load resistance as shown in Fig. 4.6. From (4.2), the differential conversion gain Amixer of the third-order sub-harmonic mixer can be calculated as

0

which is proportional to Gm3/Gm0. The simulated contour map of Gm3/Gm0 is shown in Fig. 3.8(d) in Chapter 3. In this case, a current source Mmixer6 (Mmixer7) is used to control bias current of MMixer2 and MMixer3 (MMixer4 and MMixer5), which determines the gate-to-source DC voltages of MMixer2 and MMixer3 (MMixer4 and MMixer5). Therefore, as the analysis in Chapter 3, for a given Gm3/Gm0, the bias current should be designed as low as possible until the total size of MMixer2 to MMixer5 reaches the maximum which can be accepted by the previous stage, i.e. the integrated QVCO.

4.2.3 Quadrature VCO

Due to the reduction of the required LO frequency, for a 60-GHz direct-conversion receiver, the conventional QVCO [81] can be integrated in the system easily while covering entire unlicensed band from 57 to 64 GHz (the corresponding LO frequency is from 19 to 21.33 GHz). Fig. 4.7 shows the circuit schematic of the QVCO.

In order to reduce the capacitance at the oscillating nodes to obtain a wider frequency tuning range, NMOS cross-coupled pairs formed by MQVCO1 to MQVCO4 are used in the QVCO. MQVCO5 to MQVCO8 provide coupling between the output ports for quadrature outputs. The varactors are implemented using n-type A-MOS’s. Each A-MOS has 29 fingers and the finger width (length) is 2μm (0.5μm). The simulated maximum to minimum capacitance ratio of the varactor is approximately 3 with a quality factor of 8.49 at 20GHz. MQVCO9 and MQVCO10 are biased in the triode region and the DC voltages at the output nodes are designed as VDD/2 (0.6 V in this case) in order to achieve the maximum tuning range as Vtune ranges from 0 to VDD (1.2 V in this case).

4.2.4 Baseband Amplifier and output buffer

Fig. 4.8 shows the circuit schematic of the baseband amplifier and the output buffer. The baseband amplifier consists of two cascaded differential pairs and is used to enhance the receiver gain and extend the bandwidth while driving the output buffer.

The output buffer provides unit voltage gain when the off-chip 50-Ω loads is connected to its output ports.

4.2.5 Layout consideration

Layout is an important step in designing the receiver when the operating frequency is up to 60 GHz, because a different shape or length of each interconnecting metal line may significantly affect the performances of the receiver. Therefore, all parasitic effects from the interconnections on the MMW signal path are considered in the circuit design by using an EM simulator (Ansoft HFSS). Using 0.13-μm CMOS technology, the circuit layout of the receiver is shown in Fig. 4.9. The interconnections between the LNA and mixers are extracted with the inductors as a 17-ports component for EM simulation as shown in Fig. 4.10 (a). Moreover, the parasitic inductances of the interconnections between QVCO and mixers significantly reduce the down-conversion gain, so the interconnections should be designed as short as possible. In this design, they are extracted as a 12-ports component for EM simulation as shown in Fig. 4.10 (b).

Except the interconnections on the RF and LO paths, the layout of the cascode devices, i.e. MLNA3 and MLNA5 in Fig. 4.2, should be designed carefully as well.

Considering the parasitic inductor Lpg at gate node to VDD as shown in Fig. 4.11, MLNA3 or MLNA5 provides negative resistance looking into its source like in a Colpitts

oscillator. Therefore, the parasitic inductor Lpg significantly degrades the stability of the LNA. To reduce the effect from Lpg, space near the gate node should be reserved to put a bypass capacitor to ground. In this design, two sandwich capacitors, marked by CLNA3 and CLNA5 as shown in Fig. 4.9, are put close to the gate nodes of MLNA3 and MLNA5 as bypass capacitors to ground to improve the LNA stability.