In this chapter, an analytical model for a direct ILFD is presented. From the proposed model, important design guidelines have been developed. Based on the design guidelines, a 70-GHz direct ILFD has been designed and fabricated using 0.13μm bulk CMOS technology, where a PMOS current source was used to restrict the output voltage amplitude and to increase the overdrive voltage of the input device to improve the frequency locking range. For a direct ILFD, a higher-Q passive load can release the power required without decreasing the frequency locking range. Even if the input device size is small and the varactor is not used, the frequency locking range is large. Simulation results show that the proposed direct ILFD also can be operated in the case of using 1.2-V supply voltage. Therefore, it can be integrated with other circuit using 1.2-V supply voltage. Moreover, if 90-nm CMOS technology is used in the future, 1V can be chosen as the supply voltage of the proposed circuit structure as in this design. Therefore, the proposed direct ILFD can be integrated with an MMW VCO easily and is a favorable choice for use in a CMOS MMW PLL system.
Table 2.1
Performance Comparison between the Proposed CMOS ILFD and Other CMOS Frequency Dividers
This work [35] [36] [37] [38]
Technology 0.13μm 0.13μm 90nm 0.2μm 0.18μm
Divided number 2 2 4 2 2
Input frequency 70GHz 50GHz 70GHz 55GHz 40GHz
VDD (V) 1 *1.2 1.5 0.5 1 2.5
Locking Range (%) 13.57 *20.6 0.16 12.4 5.89 5.8 With/without
varactors Without Without With Without Without Power consumption
(mW) 4.4 *5.3 3 2.75 10.1 16.8
Size of the input device
3.6μm/
0.12μm
6μm/
0.12μm N.A. N.A. N.A.
*Simulation data
Fig. 2.1 A general block diagram of a differential direct ILFD.
(a)
(b)
Fig. 2.2 Two waveforms of Vin, Vout±, and Iin as φ is equal to (a) π/2. (b) π/4.
(a)
(b)
(c)
Fig. 2.3 The simulated waveforms of Vin, Vout±, Iin, Iicos(ωt+φ), Iqsin(ωt+φ) and the equivalent model as (a) 2ω=2ωo. (b) 2ω>2ωo. (c) 2ω<2ωo.
(a)
(b)
(c)
(d)
Fig. 2.4 The contour maps of gq,max as (a) vin=0.6V. (b) vin=0.5V. (c) vin=0.4V. (d) vin=0.3V.
Fig. 2.5 Circuit structure of the proposed direct ILFD.
Fig. 2.6 The simulated frequency locking ranges and gq,max with different values of the inductor.
64 66 68 70 72 74 76 78 Length of input device= 0.144μm
(a)
Fig. 2.7 The simulated input sensitivity curves (a) in cases of different input device length. (b) in the cases of different VDD.
(a)
(b)
Fig. 2.8 (a) The block diagram of the direct ILFD. (b) the linear loop for the phase noise analysis.
(a)
(b)
(c)
Fig. 2.9 The simulated curves of Sφn_out/Sφn_in with different (a) ωo (b) Vov (c) vin at the central frequency
V
inVDD
V
biasV
out+V
out-I
inM1 M2
M
inI
DCM
pRx
V
dummyGSG pad
A buffer for measurement
L/2 L/2
10kΩ
Rp
Fig. 2.10 Circuit structure of the Low-Q ILFD.
Fig. 2.11 The micrographs of ILFDs.
Ext. Mixer Sourece
Module
Signal Generator Spectrum Analyzer
(a)
Sourece Module Signal Generator
DUT
MMW probe
MMW probe Spectrum Analyzer
DC
probe Power Supply
Bias Tee
(b)
Fig. 2.12 (a) The measurement setup for input power measurement. (b) the measurement setup for divider measurement.
(a)
(b)
Fig. 2.13 (a) The measured output amplitude versus input frequency. (b) the measured and calculated/simulated locking range and the minimum output
amplitude versus IDC.
Fig. 2.15 The measured locking ranges versus output voltage amplitudes of both proposed and low-Q ILFDs.
Fig. 2.14 The locking range as the supply voltages are 0.8V and 1V.
Fig. 2.16 The measured input sensitivities of both ILFDs.
(a)
(b)
Fig. 2.17 (a) The measured output phase noise and the phase noise of input signal from Agilent mm-wave Source Module E8257DS15 [77]. (b) The measured output
phase noise and the free-run phase noise.
CHAPTER 3
THIRD-ORDER SUB-HARMONIC MIXER WITH AN ON-CHIP WIDE-TUNING-RANGE VCO
3.1 FREQUENCY TUNING RANGE OF COMVENTIONAL CMOS VCO
In order to analyze the relationship between the frequency tuning range and oscillating frequency, a conventional high-frequency VCO is used, as shown in Fig.
3.1(a), where Mv1 and Mv2 are varactors implemented by accumulation-mode MOS’s (A-MOS’s). The model of the equivalent circuit of the VCO is shown in Fig. 3.1(b), where the broken line in the middle represents either the common mode or ground.
The integrated spiral inductor Lint is modeled with gL, Lind, and Cind. Because the impedance of the varactor Mv1/Mv2 is a function of the tuning voltage Vtune, it is modeled with a capacitive function Cvar(Vtune) and a conductive function gvar(Vtune).
The cross-coupled pair formed by M1 and M2 is modeled with –gccp and Cccp. Cload
represents the load capacitance from the next stage.
From the equivalent model in Fig. 3.1(b), the frequency tuning range α of the VCO can be calculated as
where fmax (fmin) is the maximum (minimum) oscillating frequency of the VCO, Cmin = C +C (VDD)+C +C ≈ C (VDD)+C +C , and ΔC = C (0)–C (VDD).
The startup condition is considered to find the relationship between α and fmin. When Vtune = 0V, gvar(Vtune) is maximum and the oscillation frequency is minimum (fmin). For a large fmin (e.g. 60GHz), gvar(0) is usually much larger than gL. Therefore, the startup condition in the worst case (i.e. at fmin) with a small-signal loop gain of β can be expressed as
( )
(
g gvar 0)
gvar( )
0gccp =β L+ ≈β . (3.2)
In order to express gccp by process parameters, the small-signal model shown in Fig. 3.2 is applied to M1/M2 in Fig. 3.1(a), where rg is the parasitic gate resistor; Cgs, the parasitic gate-to-source capacitor; Cgd, the parasitic gate-to-drain capacitor; Vgs, the voltage on Cgs; and gm the small-signal transconductance. Considering the gate-to-channel and overlap capacitance, Cgs and Cgd can be written as
W
respectively, where Cox is the gate-oxide capacitance per unit area; Cov, the overlap capacitance per unit width; and W (L), the MOS width (length). If the quality factor Qg = (2πfrgCgs)–1 looking into the gate terminal at frequency f is much larger than 1, gmrg << 1, and the minimum length Lmin is chosen for M1/M2, from (3.3) and (3.4), gccp
can be calculated as
( )
2πf 2γ1 ggccp ≈ m− , (3.5)
where
Moreover, to express gvar(0), the equivalent model of a single-finger A-MOS varactor is shown in Fig. 3.3(a), where Cvar,s is a function of Vtune and Rs,s represents the parasitic resistors of the poly gate and channel. When Vtune = 0, for a frequency f, the equivalent parallel model using impedance transformation is as shown in Fig. 3.3(b), where
with the definition that
)
ΔC in (3.1) can be calculated at fmin from (3.2), (3.5), and (3.9). By replacing the result
where the parameters γ1 and γ2 are independent of frequency. From the above equation, it can be observed that α exhibits a drastic decrease for an increase in the oscillating frequency fmin.
In order to observe the relationship between α and fmin in (3.11), simulations of the circuit shown in Fig. 3.1(a) are performed using 0.13μm CMOS technology. All simulations are performed by assuming Cload = 30fF and the gate voltage of M1/M2 is designed as VDD/2 = 0.6V in order to achieve the maximum tuning range as Vtune
ranges from 0 to VDD = 1.2V. For simplification, the finger sizes of M1/M2 and Mv1/Mv2 are fixed, and their sizes are changed by their finger numbers FM and Fv, respectively. The single-turn spiral inductor shown in Fig. 3.4 is used and all inductor models are obtained by using an EM simulator. For different values of FM, the corresponding inductor radii Rind and Fv are decided by the required fmin and the startup condition in (3.2) with β = 3 [78]. The simulation results of α for different size of M1/M2 and fmin are shown in Fig. 3.5(a). The corresponding values of Rind for all simulations are shown in Fig. 3.5(b). From Fig. 3.5(a), it can be observed that the maximum frequency tuning ranges are 22.9%, 8.47%, and 2.16% when fmin is 20, 40, and 60GHz, respectively. The results agree with (3.11), where a drastic decrease is observed in α for an increase in fmin.
From the above results, it can be seen that a 60-GHz conventional VCO is
difficult to cover the entire unlicensed band from 57 to 64GHz (i.e. 11.57% at 60.5 GHz). Therefore, a 60-GHz third-order sub-harmonic mixer with a 20-GHz VCO is proposed in this chapter for wideband applications.
3.2 OPERATIONAL PRINCIPLE
Consider a common-gate amplifier, as shown in Fig. 3.6. The LO signal VLO(t) at the gate terminal results in a time-varying transconductance Gm(t), which is the dominant contributor to frequency conversion. Fig. 3.7(a) shows the simulation results of the relationship between Gm(t) and VLO(t). Moreover, for a sinusoidal VLO(t),
( )
t V v(
t)
VLO = G+ LOcosωLO , (3.12)
where VG is the DC gate voltage, and vLO and ωLO are the LO amplitude and radian frequency, respectively, the corresponding Gm(t), as shown in Fig. 3.7(b), can be generally expressed as
( )
t =G +G(
t)
+G(
t)
+G(
t)
+"Gm m0 m1cosωLO m2cos 2ωLO m3cos3ωLO . (3.13)
If an RF signal with an amplitude (radian frequency) of vRF (ωRF) is applied to the source terminal, as shown in Fig. 3.6, the desired IF current IIF for the third-order sub-harmonic mixer can be calculated as
( )
From the above equation, it is apparent that Gm3 should be maximized for higher conversion gain. As shown in Fig. 3.7(a), in an LO period, Mmix operates in three different regions—cut-off, weak-inversion, and strong-inversion. Therefore, it is
difficult to frame a general equation for Gm3 based on the process parameters of Mmix. Hence, in this section, HSPICE simulations are used to observe the relationship between Gm3, Gm0, VG, vLO, and the DC current IDC of Mmix and also to find a proper bias voltage VG.
For a given MOS size, the value of Gm3 is dependent on VG and vLO. Fig. 3.8(a) shows a simulation contour map of Gm3 for various VG and vLO. In the simulation, Mmix
has 15 fingers and the width (length) of each finger is 2.6μm (0.13μm). From Fig.
3.8(a), the maximum value of Gm3 is obtained when VG = 0.45V irrespective of the value of vLO. Therefore, without considering IDC and Gm0, for a given Gm3, VG should be set as 0.45V in order to use the smallest Mmix.
However, if IDC is considered, Gm3/IDC should be used as a criterion to compare the efficiency for different conditions of VG and vLO. The simulation results of Gm3/IDC
are plotted against VG for different vLO, as shown in Fig. 3.8(b). In general, vLO is determined by the VCO for other more important specifications in a receiver, e.g.
phase noise. From Fig. 3.8(b), it can be observed that for all values of vLO, the efficiency can be improved significantly by decreasing VG, which results in a larger Mmix for a given Gm3. However, because the LO frequency is only 1/3 of the RF input frequency, the limitation on the size of Mmix, which loads the integrated VCO, is extended significantly.
When the previous stage of the mixer is an LNA, Gm0 of Mmix also acts as an important parameter. In general, the performance of an LNA degrades with the increase in Gm0. Fig. 3.8(c) shows the simulation contour map of Gm0 for various VG
and vLO. In order to make an unbiased comparison between the different conditions, the simulation contour map of Gm3/Gm0 is shown in Fig. 3.8(d). For a fixed vLO and
required Gm3, lower VG results in lower Gm0 and this results in an improved LNA design.
In summary, for a given Gm3, lower VG provides two advantages—lower power consumption and lower Gm0, with the cost that a larger size of Mmix is required.
3.3 CIRCUIT DESIGN
A 60-GHz single-balanced third-order sub-harmonic active mixer with a 20-GHz integrated VCO is designed and fabricated using 0.13μm CMOS technology. The circuit schematic is shown in Fig. 3.9(a). A conventional VCO structure is used for high-frequency operations. In order to reduce the capacitance at the oscillating nodes to obtain a wider tuning range, an NMOS cross-coupled pair formed by Mccp1 and Mccp2 is used in the VCO. The varactors are implemented using two n-type A-MOS’s (i.e. Mvar1 and Mvar2 in Fig. 3.9(a)). Each A-MOS has 26 fingers and the finger width (length) is 2μm (0.4μm). From the simulation, it is observed that the maximum to minimum capacitance ratio of the varactor is approximately 3.57 with a quality factor of 9.7 at 20GHz. A PMOS current source Mp is used in the VCO to limit the amplitude of the output voltage. Moreover, by using Mp, the DC voltage at the oscillating nodes can be easily designed to 0.6V in order to achieve the maximum tuning range as Vtune ranges from 0 to 1.2V.
The differential LO signals from the VCO are applied to the gate terminals of Mmix1 and Mmix2, which are the core mixing devices and VG is set to 0V for higher efficiency, as mentioned in Section 3.2. The RF signal is applied to the common
source terminal through a transmission line T1, which is used to match the RF port to a 50-Ω system for measurement. Due to the balanced structure of the mixer, the fundamental and odd harmonic components of the LO signal are cancelled at the RF port. Therefore, the power leakage from the LO to the RF port mainly results from the even harmonic components. The transmission lines T2 and T3 are used to filter out the second LO harmonic component, denoted by 2LO and whose frequency is 40 GHz in this case, to improve the 2LO to RF isolation of the mixer. An on-chip unit-gain buffer is used to drive 50-Ω load from the measuring equipment. It should be noted that the third-order transconductances (Gm3) of the Mmix1 and Mmix2 are sensitive to the threshold voltage variation in this situation. Therefore, a bias circuit which compensates such variation can be used to bias VG for a robust design.
It should be noted that when the RF input port does not need to be matched to the 50-Ω system or is directly connected to the LNA output port, T1, T2, and T3 can be replaced by a notch filter, as shown in Fig. 3.9(b). The rejection frequency of the notch can be designed to be equal to the 2LO frequency to improve the 2LO to RF isolation. Moreover, if the LNA provides enough reverse isolation, such notch filter also can be replaced by a simple current source for DC bias.
Mload1 and Mload2 are used as active loads to improve the conversion gain to prove the proposed mixer can be used in high-gain applications. However, if the specification of the conversion gain is low (e.g. the required gain is provided by following IF stages), the passive resistive loads can be used (or in parallel with the active loads) for wider bandwidth. Moreover, the proposed mixer can also be applied to a heterodyne receiver [86] if the active loads are replaced by LC tanks that resonate
at the required IF frequency.
3.4 EXPERIMENTAL RESULTS
The die micrograph of the proposed mixer with an integrated VCO is shown in Fig. 3.10. The chip is measured on-wafer on a high-frequency probe station. The measurement setup and environment are shown in Fig. 3.11. The LO frequency is measured by the LO power leakage at the IF port. The measured and simulation frequency tuning ranges of the integrated VCO are shown in Fig. 3.12. The measured LO frequency range is from 18.18 to 20.78GHz and the corresponding RF frequency range is from 54.54 to 62.34GHz. Using either set of information, it can be determined that the tuning percentage is 13.35%. The simulation phase noise within the tuning range is also shown in Fig. 3.12. The average phase noise at 1-MHz offset is around –100dBc/Hz. The power consumption of the VCO is 6.6mW from a 1.2-V supply.
The measured and simulation conversion gains of the mixer within the tuning range when VG = 0 and the IF frequency is fixed at 100MHz are shown in Fig. 3.13.
The measured results indicate that the average conversion gain is 7.8dB and the gain variation is smaller than 2.2dB within the tuning range. Moreover, the average power consumption of the mixer core (i.e. Mmix1 and Mmix2) is 0.36mW from a 1.2-V supply.
The measured and simulation IF frequency response is shown in Fig. 3.14 for VG = 0 and 0.1V. In both cases, the VCO frequency is fixed at 20GHz, while the RF frequency varies between 60.05 and 61GHz, corresponding to an IF frequency varying between 50MHz and 1GHz. When VG = 0 V, the measured conversion gain is 8.5dB, the 3-dB bandwidth is around 300MHz, and the DC current of the mixer core
is 0.27mA. However, when VG = 0.1V, the measured conversion gain, 3-dB bandwidth, and the DC current become 3.45dB, 500MHz, and 0.72mA, respectively. The changes in the 3-dB bandwidth and conversion gain mainly result from the variant output resistances of the active loads due to different DC currents. It should be noted that if the load resistance of the output buffer increases from 50 Ω to a few kΩ when the mixer is used in practice, the bandwidth of the mixer can be extended because the required output buffer size becomes much smaller. The measured IF power versus RF power when VG = 0 is shown in Fig. 3.15. The input 1-dB compression point is around –10.2dBm.
Fig. 3.16 presents the measured power leakages of the 2LO and LO signals at the RF port. The 2LO and LO leakages in power are less than –35dBm and –42.5dBm, respectively, within the operating frequency range. Fig. 3.17 and Fig. 3.18 are the measured spectrums of IF power, LO-to-IF leakage, and LO/2LO-to-RF leakages. The output SNR for 1Hz is measured using a spectrum analyzer for an input frequency (intermediate frequency) of 60.1GHz (100MHz). The input power level is measured by a power meter. Based on this data, the noise figure is determined to be 27.6dB.
The fundamental conversion gain of the mixer is also measured and the measured results within the tuning range are shown in Fig. 3.19. When the input frequency around 20 GHz, the fundamental gain is 7 dB larger than the third-order gain. This implies that in the fundamental operation, the noise figure of the mixer is also 7-dB better than that in the third-order operation.
Table 3.1 presents a comparison of the performances of the integrated LO generators. As there is no doubler or buffer, the VCO can be directly connected to the proposed mixer and has a relatively larger operating frequency range and lower power
consumption. A comparison of mixer performances is shown in Table 3.2. The proposed active third-order sub-harmonic mixer has a performance comparable to that of the fundamental mixer when used in a homodyne receiver [65]. Additionally, in comparison with other sub-harmonic mixers [43], [53], the proposed mixer provides a much larger conversion gain and better isolation. Moreover, it consumes the least amount of power among all the other active mixers. The main expense of using the sub-harmonic mixer is a higher noise figure. To suppress the noise from the mixer, a high-gain LNA can be used in front of the mixer in a receiver system.
3.5 SUMMARY
In this chapter, a CMOS third-order sub-harmonic active mixer is proposed and analyzed. The required oscillating frequency of the integrated VCO is 3 times less than that required by a conventional fundamental mixer. Therefore, for a 60-GHz system, the problems in the integration of the LO due to the increase in the LO frequency can be significantly reduced. Based on the experimental results, it is apparent that in percentage, the tuning range of the integrated VCO is sufficient to cover the unlicensed band from 57 to 64GHz. In addition, the performance of the proposed mixer is comparable to that of the fundamental mixer. Moreover, due to the balanced structure and proper bias strategy, the mixer also has the advantages of good isolation and low power consumption. Therefore, this mixer has potential to be used in a CMOS 60-GHz receiver for wideband applications.
TABLE 3.1
Performance Comparison between the Integrated LO Generators in this and Other Works
*Simulation data (internal node cannot be measured)
** Only the power consumption of the input and core stage of the stand-alone doubler
TABLE 3.2
Performance Comparison Between the Mixers in this and Other Works
This work [43] [53] [65]
Technology 0.13 μm SiGe 90 nm 0.13 μm
Type Active Active Passive Active
RF frequency (GHz) 60 77 33 60
IF frequency (GHz) 0.1 1 1 0.1
LO harm. no. 3rd 2nd 3rd 1st
Conversion gain (dB) 7.8 -10.3 -14 ***12
P1dB (dBm) –10.2 2.4 **–2.6 N.A.
LO/2LO-to-RF iso.
(dB) *42.5/35 30/25 21.7/29.4 N.A.
Noise figure (dB) 27.6 ***23 N.A. ***18.5 Power consumption 0.36 mW 22 mW 0 ***1.08 mW
*Measured power leakage at RF port in –dBm ** Measured IIP3 – 9.6 dB
*** Simulation data
VDD
Fig. 3.1 (a) Conventional high-speed VCO (b) equivalent model of the VCO.
Fig. 3.2 Small signal model for M1/M2.
Fig. 3.3 (a) Equivalent model of a single-finger varactor and (b) equivalent parallel model when Vtune = 0.
Fig. 3.4 Single-turn spiral inductor.
(a)
Fig. 3.5 Simulation results of: (a) frequency tuning range and (b) Rind.
Fig. 3.6 Common-gate amplifier with time-varying transconductance.
(a)
(a)
(b)
0.0 0.2 0.4 0.6 0.8 1.0
0 5 10 15 20 25
G
m3/I
DC(V
-1)
V
G(V)
v
LO=0.3V
v
LO=0.4V
v
LO=0.5V
v
LO=0.6V
(c)
(d)
Fig. 3.8 Simulation results of (a) Gm3, (b) Gm3/IDC, (c) Gm3, and (d) Gm3/Gm0.
(a)
Fig. 3.9 (a) Circuit schematic and (b) notch filter and its frequency response.
Fig. 3.10 Die micrograph.
Sourece Module Signal Generator
Atteuneator
DUT
MMW probe
RF GSGSG probe Spectrum Analyzer
DC
probe Power Supply
Bias Tee
Bias Tee Terminal
Power Sensor
Power Meter
coupler
Fig. 3.11 Sub-harmonic mixer measurement setup and environment.
Fig. 3.12 Frequency tuning range and phase noise.
Fig. 3.13 Conversion gain within tuning range.