Inversion-mode varactor

Fig. 5.8 shows circuit schematic of the I-MOS varactor using in the RF VCO for frequency tuning. A large poly resistor Rbulk connects the NMOS bulk and ac ground Vbulk. When the terminal DS in Fig. 5.8 is biased at the positive end voltage, the I-MOS is operated in the depletion mode and Fig. 5.9 (a) shows the equivalent model.

The parasitic capacitance Cparasitic is dominated by the gate-to-source and gate-to-drain overlap capacitance; Cox is the gate-oxide capacitance; and Cd is the depletion capacitance. The conductance looking into terminal G in Fig. 5.8, Gdep, can be calculated as

where ω is the radian frequency and Gbulk is the inverse of the resistance of Rbulk. If

Gbulk is much smaller than ω(Cox||Cd) and ωCparasitic within the entire frequency tuning range, Gdep is approximately equal to jωCparasitic and the minimum capacitance Cmin

can be estimated by Cparasitic. However, if the NMOS bulk is connected directly to the ac ground (i.e. case of infinite Gs), Cmin will become Cparasitic+Cox||Cd. Thus, Cmin can be decreased by Cox||Cd by using a large resistance Rbulk in Fig. 5.8. When DS is biased at the negative end, a sheet of electrons accumulates at the surface of the channel and the IMOS is operated in the inversion mode. Fig. 5.9 (b) shows the equivalent model. Rch is the channel resistance, which can be estimated by following equation [86], (overdrive voltage). To simplify, assuming Rbulk goes to infinite, the conductance looking into terminal G, Ginv, in Fig. 5.9(b) is imaginary part of Ginv is approximately equal to ω(Cox+Cparasitic) and the maximum capacitance Cmax can be estimated by Cox+Cparasitic.

Using 0.18-μm CMOS technology, the HSPICE simulated C-V characteristics of an I-MOS varactor are shown in Fig. 5.10. The resistance of Rbulk is 10k in this simulation. The voltage of terminal G in Fig. 5.8 is set to a fixed voltage, 0.8 V, and the voltage of DS is swept from 0 to 0.8 V. The improvement of the C /C ratio

using the modified I-MOS varactor of Fig. 5.8(a) is close to 25%. It should be noted that the center voltage Vc in Fig. 5.10 can be right-shifted by increasing the bulk biased voltage, Vbulk in Fig. 5.8. In the simulation, Vbulk is 0.4V.

5.2.2 MULTI-BAND OPERATION

A large varactor sensitivity kv [87] degrades of phase noise performance. The effect of kv on phase noise can be shown by the following equation [87],

( )

where fo is the oscillating frequency, Q is the quality factor of the LC tank, Δf is the offset frequency from the carrier, F is the noise factor of the gain element, k is Boltzmann’s constant, T is the flicker noise corner frequency, and kCL is a function of C and L in the resonator. If the required tuning range is large, a bandswitching topology is suggested to reduce varactor sensitivity kv [87]. However, Fig. 5.11 shows the C-V characteristics of an A-MOS varactor with the same size and bias condition as the I-MOS varactor simulated in Fig. 5.10.The A-MOS varactor cannot be fully switched when tuned from 0 to 0.8V. Thus, there is no benefit to implement bandswitching topology with A-MOS varactors to reduce kv in the case of a low tuning voltage. On the other hand, from Fig. 5.10, the gradients of the I-MOS C-V curve are relatively small when the voltages at terminal DS is 0 and 0.8V. Therefore, it makes sense using I-MOS as on/off only varactors in a bandswitching topology to reduce kv and improve phase noise performance with low tuning voltages.

5.2.3 CIRCUIT DESIGN

The VCO is designed using 0.18-μm CMOS technology. Fig. 5.12 shows the circuit schematic for the VCO. It is an LC-tank VCO with an NMOS cross-coupled pair to generate the negative resistance for oscillation. The current source Idc draws 1.5mA. The bandswitching I-MOS varactor array consists of one continuous tuning varactor controlled by tuning voltage Vc1 and two on/off only digital switching varactors controlled by Vc2 and Vc3. Gate terminal (G in Fig. 5.8) of each IMOS connects to the oscillation ports and the drain and source terminal (DS in Fig. 5.8) connects to the tuning ports (Vc1 to Vc3 in Fig. 5.12). The equivalent C-V curve of the three varactors on each side is shown in Fig. 5.10.

Fig. 5.13 shows the detail layout and equivalent model of the spiral inductor. The spiral inductor is implanted using the thick top metal and the inner radius is 80 μm. A symmetrical architecture with center tapping is used to save chip area. ADS Momentum is used for EM simulation. The two-turn inductor provides 1.55nH of inductance, and the quality factor is from 9.5 to 11 across the entire tuning range.

5.3 EXPERIMENTAL AND SIMULATION RESULTS

5.3.1 MMW VCO

Fig. 5.14(a) shows the circuit schematic of the fabricated MMW VCO in 90-nm bulk-CMOS technology. The chip micrograph is shown in Fig. 5.14(b). However, all PMOS’s and MIM capacitors are failed in the shuttle. Therefore, the debug pad which connects node Y and VDD is used in the measurement. Moreover, FIB is used to connect the output node to the output GSG pad.

The measurement setup and environment is shown in Fig. 5.15. The core size is

0.28 × 0.36 mm². The chip is measured on-wafer on a high-frequency probe station.

With VDD = 0.7 V, the measured and simulated frequency tuning characteristics are shown in Fig. 5.16. The tuning voltages of Vb1-Vb6 and Vfine are tied together and varied from -0.3 to 1.2 V, and the VCO frequency is changed from 52.2 to 61.32 GHz.

The corresponding tuning percentage is 16.07%. If the tuning voltage range reduces to 0 to 0.7 V, the tuning percentage becomes 13.98%. The difference of the central frequency between measurement and simulation is about 1.14 GHz. After the loss from the output buffer, probes, cables, adapters, and external mixer have been deembedded, the measured single-end oscillating voltage amplitudes are also shown in Fig. 5.16, where the simulation results also are shown for comparison. From the measurement results, the oscillating voltage amplitude varies from -10.55 to -4.55 dBV within the entire frequency tuning range.

The oscillation of the VCO is started as VDD is larger than 0.37 V. The measured frequency tuning ranges for VDD from 0.4 to 0.9 V are shown in Fig. 5.17. When VDD = 0.5 V, the VCO has the maximum frequency tuning range from 53.21 to 62.78 GHz (i.e. 16.5% at 58 GHz).

Multi-band operation is achieved by digitally controlling Vb1-Vb6 and fine-tuning Vfine. By the mixed-mode frequency tuning scheme, the VCO manifests 64 frequency bands. The measured frequency tuning ranges of these 64 bands are shown in Fig.

5.18, where the bands are numbered from 1 to 64 according to the digitally controlling voltages of the binary-weight MOS’s. The KVCO of each band can be calculated using the measured data and is drawn in Fig. 5.19. The maximum KVCO is 720 MHz/V at band 8 which is more than 10 times less than that in single-band operation. If more digitally controlled NMOSFETs are used, the maximum KVCO can be reduced further.

In the case of multi-band operation, the measured phase noises at 10-MHz offset frequency within the entire frequency tuning range are plotted in Fig. 5.20. The phase noise ranges from -94 to -118.75 dBc/Hz within the frequency tuning range and the average phase noise is -102.44 dBc/Hz. The measured VCO output spectrums at different frequencies are also shown in Fig. 5.20. For comparison, when Vb1-Vb6 and Vfine are tied together (i.e. single-band operation) for frequency tuning, the measured phase noises are also shown in Fig. 5.20. It can be observed that phase noise performance can be significantly improved by the multi-band operation at high-KVCO

region.

When VDD = 0.7 V, the measured average power consumptions of the VCO core within the frequency tuning range is 8.7 mW. The buffer stage dissipates 5.6 mW.

The performance benchmark of the proposed VCO and the prior works [15]-[19]

are summarized in Table 5.1. Three different figures of merits are illustrated to investigate their advantages. They are

⎟⎠

where PN is the phase noise at the offset frequency Δf, fo is the oscillating frequency, Pcons is the power consumption, TP is the frequency tuning percentage, and ΔVt is tuning voltage range. At over 50-GHz operating frequency, the proposed VCO has the widest frequency tuning range, and is the only one with the feature of

multi-band frequency tuning. Thus, the proposed VCO can be integrated in fundamental front-end system for low noise and high linearity broadband applications.

Moreover, when the VCO is used in a sub-harmonic front-end system, the operating frequency can be boosted even higher while a wide operating frequency range can be maintained.

5.3.2 RF VCO

With a 0.8-V supply voltage, Fig. 5.21 shows the tuning characteristics of the VCO when Vc1, Vc2 and Vc3 are connected together and tuned from 0 to 0.8 V. From the simulation results shown in Fig. 5.21, the frequency tuning range can be improved by 500MHz (i.e. 50%) through the large resistance Rbulk connected to the NMOS bulk.

Multi-band operation is achieved by digitally controlling Vc2-Vc3 and continuously controlling Vc1. As shown in Fig. 5.22, the oscillating frequency can be tuned from 4.4 to 5.9 GHz, achieving 29.12% tuning range with the center frequency at 5.15 GHz.

Fig. 5.23 shows the simulated phase noise when the VCO operates at a carrier frequency 5.52GHz. It has -88.01 dBc/Hz at 100-kHz offset and -109.65 dBc/Hz at 1-MHz offset. The phase noise is simulated when Vc1 is 0.3V and Vc2 and Vc3 are 0.8 V.

When the supply and tuning voltage is reduced to 0.6 V, the tuning range becomes 22.64% from 4.7 to 5.9 GHz. The phase noise is 81.52 dBc/Hz at 100KHz offset and -105.24dBc/Hz at 1 MHz offset from the carrier at 5.65GHz.

Figures of merits in (5.13)-(5.16) are used in Table 5.2 for comparison with some published RF VCOs. It can be seen that the proposed VCO has good tuning capability even if the tuning voltage is lower than 1V.

5.4 SUMMARY

In this chapter, a novel variable inductor and a modified I-MOS varactor are proposed and analyzed. By using the proposed variable inductor, a VCO is designed in the MMW frequency band. Because the minimum frequency tuning range of the VCO is independent of the oscillating frequency, it has a wider tuning range than the conventional VCO using A-MOS varactors. Moreover, in comparison with conventional capacitor bank, multi-band operation can be achieved without severely decreasing the oscillating frequency and increasing the area occupation. Simulation results show that a PMOS current source can be used to raise the VDD to 1V without degrading the frequency tuning range. Moreover, if 0.13-μm CMOS technology is used, the same method can be used to raise the VDD to 1.2V to integrate with other circuit. Therefore, the VCO using the proposed tuning strategy manifests strong potential to be applied in the MMW UWB system.

On the other hand, by using the proposed I-MOS varactor, a VCO is designed around 5 GHz for low-voltage applictions. The VCO has a fine frequency tuning capability even the supply voltage is lower than 1 V. Besides conventional RF applications, it also can be used as an LO signal generator in a heterodyne receiver for MMW applications to downconvert the IF signals to the baseband.

Table 5.1 Performance Benchmark

References [15] [16] [17] [18] [19] This

Work CMOS process .25μm .12μm .13μm 90nm 90nm 90nm

Multi-band

operation without without without without without with VDD/ΔVt (V) 1.3/2.5 1/1.6 1.5/1.5 1/N.A. 0.7/1.1 0.7/1.5

* Simulation data (PMOS current source is used to raise the VDD to 1V with the same DC current)

Table 5.2 Performance Benchmark FOMT/V(dBc/Hz) -199.1 -173.7 -168.6 -184.1 -162.8 -194.9

* Simulation data

L ₁ L ₂ R _v k

L _eq (R _v ,ω) (a)

R _eq (R _v ,ω) (b)

C _v VID

VID

Fig. 5.1 (a) The proposed variable inductor (b) equivalent circuit model.

25μm 9μm

3μm

primary coil secondary

coil

(a)

(b)

L ₂ M _v V _tune X

L ₁

k

Fig. 5.2 (a) Variable inductor circuit schematic (b) 1:1 transformer layout view.

-0.3 0.0 0.3 0.6 0.9 1.2

Fig. 5.4 Multi-band variable inductor.

V

_b1

V

_b6

V

_fine

k L

₂

L

₁

VDD M

_f

M

_c1

M

_c6

M

₁

M

₂

M

₃

M

₄

Output GSG pad

50Ω Output

buffer

transformer T

₁

Fig. 5.5 VCO circuit schematic.

-R _neg C _t L _eq R _eq

Fig. 5.6 VCO small-signal model.

V_b1

VDD=0.7V without PMOS current source Using PMOS current source to raise VDD to 1V

-120

Fig. 5.7 (a) Circuit schematic using PMOS current source. (b) simulation results.

G

Fig. 5.8 Circuit schematic of the I-MOS varactor.

G

Fig. 5.9 Equivalent model of the I-MOS varactor in (a) depletion (b) inversion mode.

1.37p

Voltage of DS terminal (volt) Vc

Fig. 5.10 C-V curves of theI-MOS varactor.

1.19p

535f

-1.8 0 0.8 1.8

Capacitance (F)

Voltage of AMOS bulk terminal (volt) Voltage at A-MOS bulk terminal (V)

Fig. 5.11 C-V curves of the corresponding A-MOS varactor.

VDD

V_c3

I-MOS varactors

I_dc V_c2 V_c1

VDD

50Ω 50Ω

OUT⁺ OUT

-VDD

Output buffer Output buffer

Fig. 5.12 VCO schematic.

L

^s1

R

s1

R

s2

L

^s2

C

^t

C

^ox1

C

^sub1

R

^sub1

C

^ox2

R

^sub2

C

^sub2

C

^ox3

C

^sub3

R

^sub3

p

¹

p2

p3

9μm 80μm

Fig. 5.13 Layout and equivalent model of the spiral inductor.

V_b1 V_b6

V_fine

k L₂

L₁ M_f VDD M_c1 M_c6

M₁ M₂

M₃ M₄

Output GSG pad

50Ω transformer T₁

C_load

V_bias M_p

Y

MIM

failed

(a)

(b)

Fig. 5.14 (a) Fabricated VCO circuit schematic. (b) chip micrograph.

DUT

MMW probe Spectrum Analyzer

DC probe Power Supply

Bias Tee Pre Amplifier

DC board

Ext. Mixer

Fig. 5.15 Measurement setup and environment.

-0.3 0.0 0.3 0.6 0.9 1.2

Oscillat ing Amplit ude (dBV)

Fig. 5.16 Measured and simulated frequency tuning ranges and oscillating amplitudes.

-0.3 0.0 0.3 0.6 0.9 1.2 52

54 56 58 60 62 64

VDD = 0.4V VDD = 0.5V VDD = 0.6V VDD = 0.7V VDD = 0.8V VDD = 0.9V

Oscillating Frequency (GHz)

Tuning Voltage (V)

Fig. 5.17 Measured frequency tuning ranges with different supply voltages.

-0.3 0.0 0.3 0.6 0.9 1.2 52

53 54 55 56 57 58 59 60

61

⁶⁴

7 6 5 43

Oscillating Frequency (GHz)

2

V

fine

(V)

Band Number

1

Fig. 5.18 Measured frequency tuning ranges of all bands.

0 8 16 24 32 40 48 56 64 0

100 200 300 400 500 600 700 800

K

VCO

(MHz/V)

Band Number

Fig. 5.19 KVCO of all bands.

52 54 56 58 60 62 -125

-120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65

Phase Noise at 10-MHz Offset (dBc/Hz)

Oscillating Frequency (GHz)

Multi-band operation Single-band operation

(a)

(b) (c)

(d)

(a) 52.19 GHz

(b) 54.55 GHz

(c) 59.58 GHz

(d) 61.3 GHz

Fig. 5.20 Measured phase noises and spectrums within the frequency tuning range.

0.0 0.2 0.4 0.6 0.8 4.2

4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

Frequency (GHz)

Tuning Voltage (V)

R_bulk connects I-MOS bulk and ground I-MOS bulk connects to ground without R_bulk

500MHz

Fig. 5.21 Simulated frequency tuning ranges of the VCO.

0.0 0.2 0.4 0.6 0.8 4.2

4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

F requency (GH z)

V

c1

(V)

Vc2 = Vc3 = 0 V Vc2 = 0.8 V, Vc3 =0 V Vc2 = Vc3 = 0.8 V

Fig. 5.22 Simulated frequency tuning range of each band.

0.1 1 10 -140

-120 -100 -80 -60

-109.65

Phase Noise (dBc/Hz)

Offset Frequency (MHz)

-88.01

Fig. 5.23 Simulated phase noise curve.

CHAPTER 6

CONCLUSIONS AND FUTURE WORK

6.1 MAIN RESULTS OF THIS THESIS

In this thesis, design methodologies and implementation techniques of several CMOS MMW RF ICs including a direct injection-locked frequency divider, a sub-harmonic mixer, a homodyne receiver, and a multi-band VCO for MMW UWB applications are presented.

Firstly, an analytical model of a direct ILFD is presented to optimize the frequency locking range. From the proposed model, it is shown that maximizing the quality factor of the passive LC resonator in a direct ILFD can reduce the power consumption without degrading the frequency locking range. Moreover, both maintaining low output voltage amplitude and increasing the DC overdrive voltage of the input device can increase the frequency locking range. Based on these design guidelines, a direct ILFD is proposed and fabricated by using 0.13-μm bulk-CMOS technology. In the proposed structure, a PMOS current source is used to restrict the output voltage amplitude and increase the DC overdrive voltage of the input device to improve the frequency locking range. Additionally, through a resistor which connects the input device substrate and the center tapped node of the inductor, the threshold voltage of the input device can be kept low for a higher overdrive voltage such that the locking range can be improved further. For comparison purpose, the other direct ILFD designed by using an LC resonator with a lower quality factor is also fabricated and comparisons on measurement results are made. It has been shown from measurement results that the proposed ILFD has a wider frequency locking range than

the low-Q ILFD when their output amplitudes are the same. The proposed ILFD has frequency locking range of 13.6%, power consumption of 4.4 mW and its input device size is 3.6μm/0.12μm. Therefore, it is suitable for the integration with a phase-locked loop system for MMW UWB applications.

Secondly, a third-order sub-harmonic mixer is designed and analyzed. The mixer consists of two common-gate amplifiers whose gate terminals are connected to the VCO oscillation signals to modulate the transconductances for frequency conversion.

The required LO frequency of the proposed mixer is 3 times less than that of the fundamental mixer. From the derived frequency tuning range of a VCO with A-MOS varators, it is shown that the frequency tuning range is inversely proportional to the square of the oscillating frequency. Therefore, by using the proposed mixer, the frequency tuning range of the integrated VCO for LO-signal generation can be significantly extended. Moreover, because the third harmonic component of the LO signal has the same polarity as the fundamental component, the third-order sub-harmonic mixer can retain the balanced structure as a fundamental counterpart with a single-phase RF signal and differential LO signals. Therefore, it has better LO-to-RF isolation in comparison with second-order sub-harmonic mixers. The proposed mixer with an on-chip VCO is fabricated by using 0.13-μm bulk-CMOS technology. The measurement results show that the frequency tuning range of the on-chip VCO is 13.35% and the corresponding RF frequency is from 54.54 to 62.34 GHz. The LO-to-RF (2LO-to-RF) power leakage is -42.5 dBm (-35 dBm). Moreover, the mixer has conversion gain of 7.8 dB and power consumption of 0.36 mW.

Thirdly, a homodyne receiver using the proposed third-order sub-harmonic mixer is proposed and designed for MMW UWB applications. The receiver includes a

broadband-matching LNA, active sub-harmonic mixers, a quadrature VCO, IF amplifiers, and output buffers. A 3-stage LNA is used to amplify the input signal and suppress the noise for the following stages. The first stage of the LNA consists of a single common-source NMOS structure with a source degeneration inductor. In comparison with the conventional cascode structure, it provides better noise figure and input matching bandwidth in the MMW band. Two double-balanced active sub-harmonic mixers are used for quadrature down conversion. Because the required LO frequency is reduced, the frequency tuning range of the integrated quadrature VCO can be significantly extended. Two-stage IF amplifiers following the mixers are used to enhance the voltage gain and bandwidth of the receiver. The final stage of the receiver is output buffers to drive off-chip 50-Ω load. It is shawn from the ADS post-simulation results that the frequency tuning range of the integrated quadrature VCO is 19.87% at 20.35 GHz and is sufficient to cover the entire MMW unlicensed band (i.e. 57-64 GHz). The voltage gain of the receiver within the unlicensed band is from 25 dB to 29.25 dB and the noise figure is from 11.1 to 13.4 dB. The receiver totally consumes 35.6 mW. In conclusion, the proposed homodyne receiver provides a solution to extend the operating frequency range for MMW UWB applications while maintaining a compact structure.

Fourthly, a new frequency tuning strategy using a single variable inductor is proposed for an MMW VCO. The variable inductor consists of a transformer and a variable resistor. The lower bound of the tuning ratio of the variable inductor is determined by the coupling factor of the transformer when the operating frequency is lower than the resonant frequency at the second coil. Therefore, the frequency tuning range of the VCO using the variable inductor is not degraded even when the oscillating frequency is increased to MMW band. Moreover, the proposed variable

inductor can be modified for multi-band operation without sacrificing the oscillating frequency. The experimental prototype of the VCO is fabricated in 90-nm CMOS technology. The measurement results show that the VCO has a frequency tuning range of 16.07% at 56.75 GHz while achieving multi-band operation. The average phase noise at 10-MHz offset is 102.4 dBc/Hz. Therefore, the VCO is suitable for MMW UWB applications.

Finally, the modified I-MOS varactors are proposed. Because of the natural abrupt gradient C-V characteristic of the I-MOS varactor, it is an attractive choice in the design of an RF multi-band VCO for a wide frequency tuning range in the case of a low tuning voltage. With a large resistor connecting ground node and I-MOS bulk node, the tuning range can be improved further. The experimental prototype of the RF multi-band VCO is designed in 0.18-μm CMOS technology. The simulation results show that the VCO has a frequency tuning range of 29.12% at 5.15 GHz when the supply and tuning voltage is 0.8 V. Such RF VCO can be used in an MMW heterodyne receiver to downconvert the IF signals to baseband.

In summary, as the bulk-CMOS technology rapidly advances toward the nanometer nodes, the CMOS ICs can be operated in the MMW band with good

In summary, as the bulk-CMOS technology rapidly advances toward the nanometer nodes, the CMOS ICs can be operated in the MMW band with good

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