H OT -C ARRIER E FFECT

The mechanism of hot-carrier effect and the hot-carrier issue in the mixed-voltage I/O buffers are described in the following.

1.3.1 The Mechanism of Hot-Carrier Effect

A cross section of a typical enhancement-mode n-channel MOS (NMOS) transistor is shown in Fig. 1.4 where the source terminal is connected to ground.

Heavily doped n-type source and drain regions are fabricated in a p-type substrate. A thin layer of silicon dioxide is grown over the substrate material and a conductive gate material covers the oxide between source and drain. In operation, the gate-source voltage modifies the conductance of the region under the gate, allowing the gate voltage to control the current following between source and drain. Now in Fig. 1.4, the positive voltages, VG and VD, are applied to the gate and drain, respectively. An inversion layer is produced as the VG is equal to or larger than the Vth of NMOS device. When the value of VD is increased, the induced conducting channel narrows at the drain end. The induced electron charge at the drain end approaches zero as VD approaches (VG - Vth). That is, the channel is no longer connected to the drain when VD > VG – Vth, which is known as pinch-off. At this time, the electric field starts rise dramatically at the pinch-off point of the NMOS device. In the high electric field, carriers are accelerated to high velocities, reaching a maximum kinetic energy (hot) near the device drain. If the carrier energy is high enough, impact ionization can occur, creating electron-hole pair. The generated electrons called secondary electrons tend to be swept to the drain and generated holes called secondary holes swept into the substrate in the NMOS device.

Fig. 1.4 The diagram of hot-carrier effect.

Some of the electrons generated in the space charge region are attracted to the oxide due to the electric field induced by the positive gate voltage, VG. These generated electrons have energies far greater than the thermal-equilibrium value and are called hot electrons (or hot carriers) [11]. If the electrons have energies on the order of 1.5 eV, they may be able to tunnel into the oxide. In some cases the generated holes and electrons can attain enough energy to surmount the Si–SiO2 barrier and become trapped in the gate oxide. In general, injection from Si into SiO2 is much more likely for hot electrons than for hot holes because (a) electrons can gain energy from the electric field much more readily than holes due to their smaller effective mass, and (b) the interface energy barrier is larger for holes (≈4.6 eV) than for electrons (≈3.1 eV) [12]. The charge trapping in interface states causes a shift in threshold voltage, additional surface scattering, and reduced mobility. The hot electron charging effects are continuous processes, so the device degrades over a period of time. There are several techniques used to reduced maximum electric field in process and device structures, such as the lightly doped drain (LDD) structure [11]

and grooved gate MOSFETs [13]. In this thesis, the mixed-voltage I/O buffers are designed without suffering hot-carrier effect in circuit techniques.

1.3.2 Hot-Carrier-Induced Lifetime Issue

The hot-carrier degradation effect depends among others on the transistor’s length and its biasing conditions [14]:

z The relation between the drain–source voltage and lifetime is exponential:

exp( / )

life A Vds

τ

, where A is 80-120 V for deep submicron processes. This relation assumes worst-case settings of the gate-source voltage.

z The length-lifetime dependency is relatively weak:

, where B = 1-5.

B

life L

τ

z The relation between gate-source voltage and lifetime is more complex. For low gate-source voltages the transistor is “off” resulting in no current and hence in no hot carriers. For very high gate-source voltages (and fixed rain–source voltage) the transistor is in the linear region resulting in no hot carriers either. Somewhere in the middle, both the drain current is large and the transistor is well in saturation. In this region, the hot-carrier degradation is worst and hence the lifetime is poorest.

A typical hot-carrier-based lifetime versus biasing plot for a minimum length transistor is given in Fig. 1.5, where Vdd,nom is the normal power supply voltage in a given process. Note that especially the drain-source voltage of a MOS transistor

strongly affects the lifetime. It is recommended that the maximum terminal voltages of a MOS transistor (Vgs, Vgd and Vds) which can be applied to the device at worst case DC stress conditions are below Vdd,nom to ensure a device lifetime of 10 years [15].

Fig. 1.5 Channel-hot-carrier lifetime as a function of Vds and Vgs. (typical behavior for 0.25-μm CMOS process)

1.3.3 Hot-Carrier Issue in Typical Mixed-Voltage I/O Buffers

The hot-carrier induced degradation or gate-oxide reliability in typical 2xVDD-tolerant I/O buffer shown in Fig. 1.3 may exist in the following two states: (1) the state of receiving 2xVDD input signal, and (2) the state of a transition from receiving 2xVDD input signal to transmitting 0-V output signal.

When such 2xVDD-tolerant I/O buffer receives 2xVDD input signals, PU and PD signals are kept at VDD and 0 V, respectively, to disable the output circuit. Since the transistor MN1 in Fig. 1.3 is turned off, the transistor MN0 is weakly “on”. This results in a voltage of about VDD at the source of MN0. In each of these two-stacked transistors, the voltages drop across the gate-oxide and the drain-source voltage are

both lower than or equal to the supply voltage (VDD). Therefore, there is neither hot-carrier degradation nor gate-oxide overstress issues in the mixed-voltage I/O buffer when receiving 2xVDD input signal.

When the 2xVDD-tolerant I/O buffer has the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the I/O PAD originally has a voltage of 2xVDD before being pulled down. At this transition moment, the transistor MN1 is turned on by PD signal from pre-driver, and the transistor MN0 is subsequently switched on when its source is pulled down by the MN1. The voltage at the drain of MN1 can be approximated as the saturation drain voltage (V^DSAT) [16]. For example, the voltage at the source of the transistor MN0 is about ~0.5V in a 0.18-μm CMOS process. Since the original 2xVDD voltage at I/O PAD is not pulled down immediately, the drain-source voltage of MN0 would be larger than the normal supply voltage (VDD) during this transition, which results in the significant hot-carrier degradation on the transistor MN0. From this point, the traditional I/O buffer with two-stacked transistors in Fig. 1.3 is difficult to build a reliable 2xVDD-tolerant I/O buffer with only 1xVDD devices in a given CMOS technology, unless an additional circuit is provided to prevent such hot-carrier degradation during signal transition.

There are several ways to boost the voltage handling capabilities of the circuit in Fig. 1.3 without using any process modification include:

„ using different aspect ratios for the lower and for the cascode transistor;

„ using longer transistors to limit channel hot-carrier degradation;

„ using a nonstationary gate voltage for the cascode transistor;

„ using more stacked transistors.

In this thesis, an external circuit is proposed to suppress hot-carried degradation without increasing the number of stacked transistors.