T HESIS O RGANIZATION

In chapter 2, two prior designs of mixed-voltage I/O buffers which tolerate 2xVDD signals will be introduced. Thesis two mixed-voltage I/O buffers are designed

with only thin-oxide devices in a given CMOS process and do not suffer gate-oxide degradation and hot-carrier degradation in both steady states of receive mode and transmit mode. The I/O buffers, however, suffer hot-carrier degradation in transitions from switching receive mode to transmit mode which will be pointed out in chapter 2.

Two new mixed-voltage I/O buffers without suffering hot-carrier degradation in transitions will be proposed in chapter 3. The simulation and experimental results are also shown in this chapter. In chapter 4, the mixed-voltage I/O buffers proposed in chapter 3 are redesigned with slew-rate control to improve ground bounce effects.

Besides, some techniques for further improving ground bounce are pronounced. The last chapter recapitulates the major consideration of this thesis and concludes with suggestion for future investigation.

Chapter 2

Prior Designs on Mixed-Voltage I/O Buffer with a Tolerant Voltage of 2xVDD

In this chapter, two mixed-voltage I/O buffers reported in [10] and [18] are introduced before the proposed reliable mixed-voltage I/O buffers in the thesis. These two mixed-voltage I/O buffers are designed to be tolerant of 2xVDD.

2.1 PRIOR DESIGN I:AMIXED-VOLTAGE I/OBUFFER WITH

GATE-TRACKING CIRCUIT AND DYNAMIC N-WELL BIAS CIRCUIT

2.1.1 Design Concept

Fig. 2.1 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit [7]-[8], [19]-[22]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig. 2.1 is used to prevent the leakage current path which is resulted from the incorrect conduction of the pull-up PMOS device when the input signal is higher than VDD. As the mixed-voltage I/O buffer is operating in the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device, MP0, exactly.

In the receive mode (tri-state input mode) with an input signal of 2xVDD, the gate-tracking circuit will charge the gate terminal of the MP0 to 2xVDD to turn off the MP0 completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the MP0 at VDD to turn off the MP0 completely, and to prevent the overstress on the

gate oxide of the MP0 when the 0-V input signal is received from I/O PAD. Moreover, the dynamic n-well bias circuit shown in Fig. 2.1 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device MP0. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at VDD so that the threshold voltage of the pull-up PMOS device isn’t increased due to the body effect. In the receive mode with an input signal of 2xVDD, the dynamic n-well bias circuit will charge the floating n-well to 2xVDD to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. On the other hand, the dynamic n-well bias circuit will bias the floating n-well at VDD when the input signal at the I/O pad is 0V.

Fig. 2.1 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.

As shown in Fig. 2.1, the extra transistors, MN2 and MP1, which are compared to Fig. 1.2, are added in the input circuit. The transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The

transistor MP1 is used to prevent unnecessary leakage current in the inverter INV1.

Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV1 will rise up to “VDD-Vth” when the input signal at the I/O pad is 2xVDD in the receive mode. The transistor MP1 will pull the input node of inverter INV1 up to VDD when the output node of inverter INV1 is pulled down to 0V. Therefore, the gate-oxide reliability problem of the input buffer can be solved. Moreover, the circuit implementation of pre-driver composed of a NAND gate and NOR gate is shown in Fig. 2.2. The operations of pre-driver are list in Table 2.1. When the output enable signal OE is 0V, the mixed-voltage I/O buffer is operated in receive mode. The pull-up signal (PU) and pull-down signal (PD) are set to VDD and 0V, respectively, to turn off pull-up device and pull-down devices. On the contrary, both PU and PD are set to VDD to turn off pull-up device and turn on pull-down devices, respectively, in transmitting 0-V output signal, and they are set to 0V to switch on pull-up device and switch off pull-down devices, respectively, in transmitting VDD output signal.

Fig. 2.2 The circuit implementation of pre-driver.

Table 2.1

Fig. 2.3 shows the mixed-voltage I/O buffer with the dynamic n-well bias circuit and gate-tracking circuit proposed in [10]. For clear illustration, this mixed-voltage I/O buffer is called GTCMXIO in this thesis. When the output control signal OE is at VDD (logic “1”), the mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad rises or falls according to signal Dout, which is controlled by the internal circuits of IC. The pull-down signal, PD, produced by pre-driver is directly connected to the gate terminal of the pull-down NMOS device, MN1. The pull-up signal, PU, is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit which is composed of NMOS transistors MN2-MN4 and PMOS transistors MP2, MP3 and MP5. The transistors MN2 and MP2 comprise a transmission gate. The transistor MN3 in Fig. 2.3 is used to protect the transistor MN4 from gate-oxide reliability problem. The dynamic n-well bias circuit is composed of transistors MP4 and MP6. If the mixed-voltage I/O buffer is operating in transmit mode (OE = VDD), the gate terminal of MP4 will be biased at 0V to bias the floating n-well at VDD by turning on the transistor MP4. At this time, the PU signal is fully transmitted to the gate terminal of the pull-up PMOS device MP0 through the

transmission gate, MN2 and MP2. As 0-V output signal is transmitted, the PD signal is set to VDD to turn on the transistor MN1. In the meanwhile, the PU signal is set to VDD to turn off the pull-up device MP0. Consequently, the voltage at the I/O pad and the gate voltage of transistor MP5 are discharged to 0V through transistors MN0 and MN1. Transistor MP5 is turned on until the gate terminal of transistor MP2 is discharged to |Vtp|, where Vtp is the threshold voltage of PMOS device, through transistors MN3 and MN4.

Fig. 2.3 The mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit proposed in [9].

When the proposed I/O buffer is operated in the receive mode, the PU and PD signals are kept at VDD and 0V, respectively, to turn off transistors MP0 and MN1.

Signal Din rises or falls according to the signal at the I/O pad in the receive mode. In order to prevent the undesired leakage current from the I/O pad to the power supply (VDD) through the pull-up PMOS device MP0, transistor MP3 is used to track the signal at the I/O pad and to control the gate voltage of transistor MP0. When the

voltage level at the I/O pad exceeds “VDD+|Vtp|,” such as 2xVDD, transistor MP3 is turned on to charge the gate terminal of transistor MP0 up to 2xVDD. Thus, transistor MP0 is completely turned off to prevent the leakage current through its channel. If a 0-V input signal is received at I/O PAD, the floating n-well is biased at VDD through the transistor MP4. As the mixed-voltage I/O is operating in the receive mode with an input signal of 2xVDD, another PMOS device MP6 is turned on to bias the floating n-well at 2xVDD. Also, transistor MP4 is turned off to prevent the leakage path by pulling up the gate terminal of MP4 to 2xVDD through transistor MP5. As a result, there is no leakage current path from the I/O pad to the power supply (VDD).

Whenever the proposed mixed-voltage I/O buffer is in the transmit mode or the receive mode, the floating n-well is biased at VDD or 2xVDD directly. Thus, the subthreshold leakage problems do not occur in this proposed I/O buffer. Besides, transistor MP5 is also turned on to keep transistor MP2 off in order to prevent another leakage path from the gate terminal of transistor MP0 to the UP signal when the signal at the I/O pad is 2xVDD.

Transistors MN0 and MP1 with inverters INV1 and INV2 are used to transfer the input signal from the I/O pad to the internal node Din in the receive mode. Transistor MN0 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The signal at the I/O pad can be successfully transferred to the internal input node Din. This I/O buffer can be correctly operated with neither gate-oxide reliability problem nor any circuit leakage issue in the receive mode.

2.1.3 Hot-Carrier Issues in GTCMXIO

Although the mixed-voltage I/O buffer proposed in [10] does not suffer gate-oxide degradation and leakage issue, it still suffers hot-carrier degradation under the I/O signal transitions. During the transition from receiving 2xVDD input signal to

transmitting 0-V output signal, the transistor MN0 suffers the hot-carrier degradation mentioned in chapter 1. The hot-carrier degradation will also occur on MN3 device in this traditional 2xVDD-tolerant I/O buffer during this transition since the gate terminal of MP4 is originally biased at 2xVDD through transistor MP5. Besides, the transistors MN2 and MP2 also suffer hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal since the gate terminal of transistor MP0 is initially kept at 2xVDD but the PU signal has been pull down to 0V by the pre-driver to turn on transistor MP0.

2.2 PRIOR DESIGN II:AMIXED-VOLTAGE I/OBUFFER WITH

BLOCKING NMOS AND DYNAMIC GATE-CONTROLLED CIRCUIT

2.2.1 Circuit Description

Fig. 2.4 depicts the mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit proposed in [18], which is called SBNMXIO in this thesis. In Fig. 2.4, VDDH has a high voltage of 2xVDD, which can be generated by the on-chip charge pump circuit [23] or other high-voltage generators. Transistor MNS1 is used to protect the conventional I/O buffer from the high-voltage overstress. The operations of the dynamic gate-controlled circuit in the I/O buffer with blocking NMOS are listed in Table 2.2. When the I/O buffer is in the receive mode, the gate terminal of MNS1 (node 2) is biased at VDD by the dynamic gate-controlled circuit, whereas the pull-up device MP0 and pull-down device MN0 are both turned off by the pre-driver. At this moment, if an input signal of logic ‘0’ (0V) is received from the I/O PAD, node 1 is discharged to 0 V through the transistor MNS1, and this input signal can be successfully transferred to the node Din. When a logic ‘1’ (VDDH) signal is received at the I/O pad, the gate terminal of transistor MNS1 is still biased at VDD, so the

voltage on node 1 is pulled to “VDD−Vth”. A feedback device MP1 is added to restore the voltage level on node 1 to VDD, which avoids the undesired static dc current through the inverter INV1. In this design, MNS1, MP1, and inverter INV1 can convert the VDDH input signal to VDD signal successfully. Therefore, MNS1 can protect the I/O buffer without suffering high-voltage overstress in both steady states of transmit mode and receive mode.

Fig. 2.4 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit.

Table 2.2

Operations of the dynamic gate-controlled circuit in the mixed-voltage I/O buffer with blocking NMOS [18].

Operating Modes Signals at I/O

PAD Vg of MP0 (PU) Vg of MNS1 (Node 2)

Receive X VDD VDD

Transmit Low (0V) VDD VDD

Transmit High (VDD) 0V VDDH (2xVDD)

Fig. 2.5 Circuit implementation of the dynamic gate-controlled circuit in the SBNMXIO.

Fig. 2.5 depicts the dynamic gate-controlled circuit of the I/O buffer in Fig. 2.4, where MP2 and MP3 are designed with the cross-coupled structure. If the gate voltage of MP2 (or MP3) is pulled down, this transistor is turned on and pulls up the gate voltage of the other transistor to VDDH (2xVDD) to turn it off. For example, if the voltage on node 5 is lower than “VDDH−|Vtp|” and the voltage on node 6 is VDDH, MN2 is turned on to keep the node 5 at VDD. Capacitors C1 and C2 are used to couple the signals from nodes 3 and 4 to nodes 5 and 6, respectively. The voltages across these capacitors are always VDD, because the voltage levels on the top plate and bottom plate of capacitors C1 and C2 are either VDD and 0V or 2xVDD and VDD. With these capacitors, when node 3 converts the voltage level from VDD to 0V, the voltage on node 5 is pulled down to VDD and then the voltage level on node 6 is pulled up to 2xVDD by transistor MP3. On the contrary, when the voltage level on node 4 is converted from VDD to 0V, the voltage on node 6 is pulled down to VDD, and that on node 5 is pulled up to 2xVDD by MP2. Initially, the voltages on nodes 3, 4, 5, and 6 could be unknown. If the voltages on nodes 5 and 6 are 2xVDD and VDD, and the voltages on nodes 3 and 4 are 0V and VDD, the voltages across capacitors C1 and C2 are 2xVDD and 0V, respectively, instead of both VDD. In order to overcome this

problem, diode strings DS1 and DS2 are added. The turn-on voltages of the diode strings are designed to a little higher than VDD by using multiple diodes in stacked configuration. In order to prevent the leakage current path to the grounded p-type substrate, the diode-connected MOSFET or poly diode [24] is suggested. With these diode strings, if the voltage on node 3 is at 0V and that on node 4 is at VDD initially, the voltage on node 5 is clamped at the turn-on voltage (~VDD) of DS1. Therefore, MP3 is turned on to pull up the voltage on node 6 to 2xVDD. Thus, the voltages across capacitors C1 and C2 are both VDD.

In this mixed-voltage I/O buffer, the bulk of the blocking NMOS MNS1 can be coupled to 0V (GND) without any gate-oxide reliability problem, even if the gate voltage of MNS1 may be as high as VDDH (2xVDD). The reason is that this blocking NMOS MNS1 is always turned on and the voltage across the gate oxide of MNS1 is from the gate to the conducting channel, but not from the gate to its bulk. The gate oxides of all NMOS devices in the dynamic gate-controlled circuit are also safe because these NMOS devices are turned on when their gates are pulled up to VDDH.

2.2.2 Hot-Carrier Issues in SBNMXIO

There is no reliability issue for this mixed-voltage I/O buffer proposed in [18] in the steady states of receive mode and transmit mode. However, when the mixed-voltage I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the I/O PAD originally has an initial voltage of 2xVDD before being pulled down. At this transition moment, the transistor MN0 is turned on by PD signal from pre-driver, and the transistor MNS1 is subsequently switched on when its source is pulled down by the MN0. Since the original 2xVDD voltage at I/O PAD is not pulled down immediately, the drain-source voltage of MNS1 would be larger than the normal supply voltage (VDD) during this transition, which results in the

hot-carrier degradation on the transistor MNS1. With consideration of hot-carrier reliability for long-time reliable applications in microelectronic products, the 2xVDD I/O buffer designed with single blocking NMOS device in Fig. 2.4 with only 1xVDD devices is somewhat weak to reliably receive the 2xVDD-tolerant input signals in a given CMOS technology.

Chapter 3

Reliability Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Effect

3.1 INTRODUCTION

Since the hot-carrier degradation threats the lifetime of ICs more seriously with newer CMOS generations, the mixed-voltage I/O buffers must be designed not only with consideration of gate-oxide reliability but also with consideration of hot-carrier effect. A 2xVDD-tolerant I/O buffer fabricated in 0.25-μm CMOS process was reported in [14]. This 2xVDD-tolerant I/O buffer uses double-cascode structure to overcome hot-carrier degradation although it consumes larger silicon area and propagation delay. In this chapter, two robust mixed-voltage I/O buffers based on the prior designs, GTCMXIO and SBNMXIO, mentioned in chapter two have been proposed. The reliable designs of mixed-voltage I/O buffers do not suffer gate-oxide degradations and hot-carrier degradations in both transmit mode and receive mode and the transitions.

3.2 2XVDD-TOLERANT I/OBUFFER WITH DOUBLE-CASCODE

STRUCTURE [14],[25]

Fig. 3.1 shows a circuit using three-stacked (double-cascode) transistors to suppress hot-carrier degradation for the 2xVDD-tolerant I/O buffer [14], [25]. The transistors MPT0 and MPT1 comprise a tracking circuit for gate terminal of transistor MN2. The corresponding voltages of the 2xVDD-tolerant I/O buffer in two operating modes

(transmit and receive modes) are list in Table 3.1. When the I/O buffer receives 2xVDD input signal, the gate terminal of transistor MN2 is biased at 2xVDD through transistor MPT0. Consequently, the source terminal is biased at “2xVDD-ΔV” due to the diode-connected MN2. On the contrary, the gate terminal of transistor MN2 is biased at VDD through transistor MPT1 if a 0-V signal is received or transmitted at I/O PAD. When the I/O buffer transmits VDD output signal to I/O PAD, the gate terminal of transistor MN2 is biased at ~VDD due to weakly turn-on transistors MPT0 and MPT1. Therefore, this 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors suffers neither gate-oxide degradation nor hot-carrier effect in both transmit and receive modes. As the I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal is biased at

“2xVDD-ΔV” initially. In the meanwhile, the source terminal of MN0 is pulled down to ~0.5V by the MN1 in a 0.18-μm technology. The ΔV can be controlled such that all the drain-source voltages of MN0, MN1 and MN2 are below maximum operating voltage, Vdd,nom in a give COMS process. Thus, this 2xVDD-tolerant I/O buffer proposed in [14] can successfully solve the hot-carried degradation during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

According to logic transistor sizing, each of the stacked transistors in Fig. 3.1 is 1.5 times larger in device size than that of the two-stacked transistors in Fig. 1.3 for

According to logic transistor sizing, each of the stacked transistors in Fig. 3.1 is 1.5 times larger in device size than that of the two-stacked transistors in Fig. 1.3 for