Summary

Two new mixed-voltage I/O buffers, HCPMXIO and TBNMXIO, have been proposed in this chapter without suffering hot-carrier degradation. Both two designs have been fabricated in a 0.18-μm CMOS process with only thin-oxide devices and designed to meet PCI-X 2.0 applications. The hot-carrier degradation on mixed-voltage I/O buffers is eliminated by using circuit technique. The circuit techniques to solve hot-carrier degradation can be applied to the general 2xVDD-tolerant I/O buffers.

Chapter 4

Mixed-Voltage I/O Buffers with Slew-Rate Control

4.1 INTRODUCTION

Signal and power integrity are crucial problems in VLSI systems. Modern trends in deep sub-micron circuit designs, such as high operating frequencies, short rise/fall times, and lower supply voltage, exacerbate this problem. Output buffers provide an interface for driving mainly capacitive and inductive external loads. The capacitive load typically consists of the bonding wire, the pin, the conductors on the PCB and the input capacitances of the connected gates. The inductive load usually comprises the package parasitic series inductances of the power and ground lines supplying the output buffer, connected to the external power and ground rails on the PCB. A major component of the circuit noise is the inductive noise. Ground bounce, also known as simultaneous switching noise (SSN) or delta-I noise, is a voltage glitch induced at power/ground (P/G) distribution connections due to switching currents passing through either wire/substrate inductance or package lead inductance associated with power or ground rails. When the current flows through the inductance L, a voltage drop as eq. (4-1 is induced.

V Ldi

= dt (4-1)

In output buffer design, the transistors sizing is imposed by DC interfacing constraints. This leads to several problems [27]:

„ unacceptable high current peaks which occur with the simultaneous

switching of many output buffers;

„ inductive power supply noise which results in large voltage drops;

„ electromagnetic interference (EMI) due to high output edge switching rates.

The resulting noise voltage can potentially cause spurious transitions at the inputs of devices sharing the same power and ground rails. Therefore, controlling the output voltage variations is generally required to limit the crosstalk and reduce the inductive power supply noise to an acceptable value. Besides, the effect of ground bounce in output buffer can be simply modeled as an inductor shown in Fig. 4.1 [28].

Fig. 4.1 The model for ground bounce effect.

4.2 SLEW-RATE CONTROL IN TYPICAL I/OBUFFERS

4.2.1 Conventional Slew-Rate Control

To solve these problems, a reduction of the slew rate in the output edges is preferred as far as the speed specification is satisfied [29]. A simple approach is to slow down the turn-on time of the output switching transistor through an access resistor to the transistor gate. Furthermore, the output driver can be divided into

several parallel output drivers for ground bounce reduction and slew-rate control. An output buffer with conventional slew-rate control, which is a three-step slew-rate control circuit, is shown in Fig. 4.2 [19]. The parallel output transistors of slew-rate controlled output buffer turn on progressively through delay elements implemented by resistors or transmission gates. This helps reduce the slew rate of output buffer and therefore the ground and power bounce. However, the output transistors turn off step by step as output transistors turn on. Therefore, the circuit consumes unnecessary power resulting from short-circuit current. For low power consideration, another slew-rate controlled topology should be introduced.

Fig. 4.2 Output buffer with conventional slew-rate control.

4.2.2 Improved slew-rate control to reduce short-circuit current

Fig. 4.3 shows an output buffer with improved slew-rate control to reduce short-circuit current [19]. The output transistors are divided into three parts with their corresponding gate-controlled signals generated by slew-rate control. The transistors MN1 and MP1 in Fig. 4.3 are used to control CMOS output driver to turn it on. Note that the pull-up signal (PUb) and pull-down signal (PDb) are the inverse of those (PU and PD) in previously mentioned designs, such as the designs in Fig. 3.5 and Fig. 3.13.

When the output buffer is operating in transmit mode (OE=VDD), the transmission

gates are used as resistive elements to turn on each individual output transistor gradually. As the output buffer is operating in tri-state mode, the output transistors are quickly turned off by the transistors MP2-MP4 and MN2-MN4. As a result, this slew-rate control is compatible for low power design. This structure of slew-rate control is redesigned for mixed-voltage I/O buffers proposed in this thesis.

Fig. 4.3 Output buffer with an improved slew-rate control to reduce short-circuit current.

4.3 SLEW-RATE CONTROL ON THE TBNMXIO

4.3.1 Circuit Implementation

In section 3.4, a 2xVDD-tolerant I/O buffer with two blocking NMOS devices and dynamic gate-controlled circuit (TBNMXIO) has been proposed without

hot-carrier degradation. The blocking NMOS devices protect the I/O buffer from gate-oxide degradation and hot-carrier degradation. In Fig. 3.13, since the gate terminals of transistor MP0 and MN0 are switched either to VDD or to 0V, the mechanism of slew rate control in Fig. 4.3 can be applied into TBNMXIO without modifications. The TBNMXIO with slew-rate control is shown in Fig. 4.4 and its dynamic gate-controlled circuit has been shown in Fig. 3.14. This 2xVDD-tolerant I/O buffer with slew-rate control is labeled as TBNMXIO-SR to be a contrast with TBNMXIO, which has no slew-rate control.

Fig. 4.4 The TBNMXIO with slew-rate control.

4.3.2 Simulation Results

Again, this I/O buffer with slew-rate control is designed to meet PCI-X 2.0 applications, thus VDD is 1.5V and VDDH is 3.3V. The TBNMXIO-SR has been verified in a 0.18-μm CMOS process by SPICE simulation. The simulation waveforms of the TBNMXIO-SR with an operating speed of 266 MHz in transmit

mode are shown in Fig. 4.5. The gate-controlled signals of MPD1-MPD3, VPC1, VPC2 and VPC3, are pulled to 0V one by one as the 2xVDD-tolerant I/O buffer transmits VDD output signal to I/O PAD. On the contrary, when 0-V output signal is transmitted to I/O PAD, the VPC1, VPC2 and VPC3 are quickly pulled up to VDD to turn off transistors MPD1-MPD3. Similarly, the gate-controlled signals of MND1-MND3, VNC1, VNC2 and VNC3, are progressively pulled up to VDD in transmitting 0-V output signal and quickly pulled down to 0V to turn off transistors MND1-3 in transmitting VDD output signal. As a result, the TBNMXIO-SR transmits data with mitigated switching current and consumes extra power a little for slew-rate controlled circuit.

Table 4.1 summarizes the simulation results of the TBNMXIO-SR with the TBNMXIO, which has no slew-rate control. The timing specifications of mixed-voltage I/O buffer with slew-rate control are some what larger than those of mixed-voltage I/O buffer without slew-rate control. Also, the driving currents of TBNMXIO-SR are smaller than those of TBNMXIO due to the slew-rate control. As shown in Table 4.1, the slew rate control in TBNMXIO-SR does not consume extra power too much.

Fig. 4.5 Simulation waveforms of the TBNMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD.

Table 4.1

The simulation results of TBNMXIO with/without slew-rate control.

Parameters TBNMXIO

Power Consumption 31 μW/MHz 31 μW/MHz

Trise 664 ps 846 ps

Tfall 627 ps 825 ps

Tpt 784 ps 925 ps

Transmit Mode

Power Consumption 67 μW/MHz 68 μW/MHz

4.3.3 Ground Bounce

In order to verify the reduction of ground bounce by slew-rate control, a model for ground bounce effects is shown in Fig. 4.6. The inductances of wire bonds vary from 7 nH to 15 nH in the simulation for typical cases. Since the switching currents of mixed-voltage I/O buffers in transmit mode are much larger than that in receive mode, the ground bounce effects are simulated in transmit mode for clear illustration. The simulation waveforms of ground bounce effects on power lines are shown in Fig. 4.7 and several parameters are defined as follows:

z VDD_ext/GND_ext: External power supply;

z VDD_max/VDD_min: maximum/minimum value of VDD power line;

z GND_max/GND_min: maximum/minimum value of GND power line;

z ΔVVDD_over: overshoot on VDD power line (VDD_max-VDD_ext);

z ΔVVDD_under: undershoot on VDD power line (VDD_ext-VDD_min);

z ΔVGND_over: overshoot on GND power line (GND_max-GND_ext);

z ΔVGND_under: undershoot on GND power line (GND_ext-GND_min).

The ΔVVDD_under and ΔVGND_over among these parameters are the major concerns since these two terms may result in increasing timing delay and even logic errors on transmitted signals.

The simulation waveforms of TBNMXIO-SR which is operated in transmit mode with an operating speed of 266 MHz are shown in Fig. 4.8. The signals on I/O PAD are like sine wave due to the ground bounce effect. The simulation results with variation of wire bond inductance on VDD power line and GND power line are shown in Fig. 4.9 and Fig. 4.10, respectively. Since the current supplied from VDDH is much smaller than that from VDD, only ground bounce effect on VDD is shown. As shown in Fig. 4.9 and Fig. 4.10, the TBNMXIO-SR improves the ground bounce effects greatly.

Fig. 4.6 Simulated model of ground bounce.

Fig. 4.7 Simulation waveforms of ground bounce effects on power lines.

Fig. 4.8 Simulation waveforms of the TBNMXIO-SR with ground bounce effect in transmit mode.

The simulation waveforms of TBNMXIO-SR which is operated in transmit mode with an operating speed of 266 MHz are shown in Fig. 4.8. The signals on I/O PAD are like sine wave due to the ground bounce effect. The simulation results with variation of wire bond inductance on VDD power line and GND power line are shown in Fig. 4.9 and Fig. 4.10, respectively. Since the current supplied from VDDH is much smaller than that from VDD, only ground bounce effect on VDD is shown. As shown in Fig. 4.9 and Fig. 4.10, the TBNMXIO-SR improves the ground bounce effects greatly. From Fig. 4.9, it is found that the overshoot of power noise in the TBNMXIO-SR was not improved greatly since the PMOS devices in output driver were turned off simultaneously by slew-rate control.

(a)

(b)

Fig. 4.9 The relation between ground bounce on VDD power line and wire bond inductance on the TBNMXIO and TBNMXIO-SR. (a) The overshoot and (b) the undershoot on VDD power line.

(a)

(b)

Fig. 4.10 The relation between ground bounce on GND power line and wire bond inductance on the TBNMXIO and TBNMXIO-SR. (a) The overshoot and (b) the undershoot on GND power line.

4.4 SLEW-RATE CONTROL ON THE HCPMXIO

4.4.1 Reliability Issues

Fig. 4.11 shows the HCPMXIO with the structure of slew rate control in Fig. 4.3.

Also, the output transistors MN0, MN1 and MP0 are divided into three individual parts. The transistors MN2 and MP2 in Fig. 3.5 are omitted since the gate terminal of transistor MP0 has been connected to the slew-rate control. The hot-carrier-prevented circuit for transistors MN0 and MN3 are shown in Fig. 4.11 (b) and (c), respectively.

Note that the bulks of the PMOS transistors MPSR2-MPSR4 in slew-rate control are connected to the floating n-well bias circuit (nwell) to avoid leakage paths from drain terminals of transistors MPSR2-4 to power supply (VDD) through the parasitic drain-to-well pn-junction diode in the MPSR2-4.

When the 2xVDD signal is received at I/O PAD, the gate-controlled signals of transistors MPD1-MPD3 are pulled up to 2xVDD through transistors MP31-MP33.

However, the gate-controlled signal of transistors MPSR2-MPSR4, PUb, is set to 0V by pre-driver at this time. Thus, the absolute gate-drain voltages (|Vgd|) of transistors MPSR2-MPSR4 are as high as 2xVDD resulting in gate-oxide degradation. Besides, the transistors MPR1 and MPR2 suffer gate-oxide degradation as the I/O buffer receives 2xVDD input signals. In the transition from receiving 2xVDD input signal to transmitting VDD output signal the MPR1, MPR2, MNR1, and MNR2 suffer hot-carrier degradation. Since the gate-controlled signal of transistor MPD1 is pulled up to 2xVDD through transistor MP31 and PUb is set to 0V in this condition, the transistor MNSR1, which is used to control CMOS output driver, suffers gate-oxide degradation and hot-carrier degradation, too. As a result, the slew-rate control should be redesigned to be compatible with the HCPMXIO without suffering gate-oxide degradation and hot-carrier degradation.

(a)

(b)

(c)

Fig. 4.11 (a) The mixed-voltage I/O buffer based on the HCPMXIO with slew-rate control. (b) The hot-carrier-prevented circuit for transistor MN0 ,and (c) the hot-carrier-prevented circuit for transistor MN3.

4.4.2 New Slew-Rate Control on Mixed-Voltage I/O Buffer

A robust mixed-voltage I/O buffer with modified slew-rate control is proposed in Fig. 4.12 and called HCPMXIO-SR. The hot-carrier-prevented circuits for transistors

MN0 and MN3 have been shown in Fig. 4.11 (b) and (c). The NMOS transistors MNSR6-MNSR8 are used to protect transistors MPSR2-MPSR4 from gate-oxide degradation and avoid leakage currents as the HCPMXIO-SR receives 2xVDD input signals. The gate-controlled signal of transistors MPSR6-MPSR8, PDH, is high-level version of pull down signal, PD, shifted by the level shifter. Furthermore, the transistor MNSR2 is used to protect transistor MNSR1 from gate oxide degradation and hot-carrier degradation as the mixed-voltage I/O buffer receives 2xVDD input signal. Since the transmission gates MNR1/MPR1 and MNR2/MPR2 are mainly used to propagate 0-V signal to turn on PMOS output transistors, MPD1-MPD3, one by one, the PMOS transistors MPR1 and MPR2 can be omitted and consequently only NMOS transistors are used as resistive elements. As a result, the resistive elements do not suffer gate-oxide degradation mentioned in the previous section. Similarly, the transistors MNR3 and MNR4 can be omitted. When the mixed-voltage I/O buffer receives 0-V input signal at I/O PAD, the PD signal is set to 0V and consequently PDH signal is set to VDD. At this time, the gate-controlled signals of transistors MPD1-MPD3, VPC1-VPC3, are biased at “VDD-Vth” due to weakly turned-on transistors MPSR6-8, thus results in subthreshold leakage currents on transistors MPD1-MPD3. To avoid this problem, the gate-controlled signals of transistors MPD1-MPD3 are pulled up to VDD through the transistors MP34-MP36 in Fig. 4.12 as 0-V input signal is received at I/O PAD. Note that the bulks of PMOS devices and NMOS devices in the new slew rate control are connected to VDD and GND, respectively. The bulks of transistors from MP31 to MP36 are connected to the n-well bias circuit (nwell).

The operations of this HCPMXIO-SR are list in Table 4.2. When the HCPMXIO-SR is operated in receive mode, the PUb and PDb signal are 0V and VDD, respectively, to turn off output driver. In the meanwhile, the PDH signal is set

to VDD by level shifter. The transistors MP31 and MP34 comprise the gate tracking circuit of transistor MPD1 as the I/O buffer is operating in receive mode. Similarly, transistors MP32/MP35 and MP33/MP36 are the gate-tracking circuit of transistor MPD2 and MPD3, respectively. As 2xVDD input signal is receive at I/O PAD, the VPC1, VPC2 and VPC3 are set to 2xVDD through transistors MP31, MP32 and MP33. On the contrary, the VPC1, VPC2 and VPC3 are set to VDD through transistors MP34, MP35 and MP36. As a result, the input signals can be received successfully without gate-oxide reliability problem and leakage currents. If the mixed-voltage I/O buffer is transmitting 0-V output signal, the PDb signal is set to 0V, and consequently transistor MPSR1 is turned on to propagate VDD signal to gate terminals of transistors MND1-MND3 through transistors MPR3 and MPR4. In the meanwhile, the PDH signal is set to 2xVDD, thus the VDD signals can be transmitted to the gate terminals of transistors MPD1-MPD3 through transistors MNSR6-MNSR8 successfully. As a result, transistors MPD1-MPD3 are quickly turned off. On the other hand, if VDD output signal is transmitted from Dout to I/O PAD, the PUb signal is pulled up to VDD to turn on transistor MNSR1. The 0-V signal consequently is propagated to VPC2 and VPC3 through transistors MNR1 and MNR2. The PMOS transistors MPD1, MPD2 and MPD3 are turned on one by one to pull up I/O PAD to VDD. In the same condition, the PDb signal is set to VDD to turn on transistors MNSR3-MNSR5, thus NMOS transistors MND1, MND2 and MND3 are quickly turned off. As the foregoing descriptions, this HCPMXIO-SR can be successfully operated in both receive mode and transmit mode without gate-oxide degradation and hot-carrier degradation. Furthermore, the mechanism of hot-carrier-prevented circuit in Fig. 3.4 can be applied in transistor MNSR2 to avoid hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 4.12 The HCPMXIO with modified slew-rate control.

Table 4.2

The operations of the HCPMXIO-SR

Operating Modes

Signals at

I/O PAD PUb PDb PDH VPC1-VPC3 VNC1-VNC3

Receive Low (0V) 0V VDD VDD VDD 0V

Receive High

(2xVDD) 0V VDD VDD 2xVDD 0V

Transmit Low (0V) 0V 0V 2xVDD VDD VDD

Transmit High

(VDD) VDD VDD VDD 0V 0V

4.4.3 Simulation Results

This HCPMXIO with slew-rate control is designed to meet PCI-X 2.0 applications, thus VDD is 1.5V and VDDH is 3.3V. The HCPMXIO-SR has been verified in a 0.18-μm CMOS process by SPICE simulation. The simulation waveforms of the new HCPMXIO-SR with an operating speed of 266 MHz in transmit mode are shown in Fig. 4.13. When the I/O buffer transmits VDD output

signal to I/O PAD, the gate-controlled signals of MPD1-MPD3, VPC1, VPC2 and VPC3, are pulled to 0V one by one. In the meanwhile, the gate-controlled signals of MND1-MND3, VNC1, VNC2 and VNC3, are pulled down to 0V to turn off transistors MND1-MND3 quickly. On the contrary, when 0-V output signal is transmitted to I/O PAD, the VPC1, VPC2 and VPC3 are quickly pulled up to VDD to turn off transistors MPD1-MPD3. The VNC1, VNC2 and VNC3 are progressively pulled up to VDD to turn on transistors MND1-MND3. As a result, the HCPMXIO-SR successfully transmits data with a reduced slew rate.

Fig. 4.13 Simulation waveforms of the HCPMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD.

The simulation results of the HCPMXIO-SR and HCPMXIO, which has no slew-rate control, are summarized in Table 4.3. The propagation delay and rise/fall time of this HCPMXIO-SR are larger than those of the HCPMXIO. Also, the driving currents of HCPMXIO-SR are smaller than those of the HCPMXIO due to the

slew-rate control. The power consumption of this HCPMXIO-SR is larger than that of HCPMXIO due to the slew-rate controlled circuit, which is more complex than the slew-rate control circuit in the TBNMXIO-SR.

The ground bounce effects on GND and VDD power lines are shown in Fig. 4.14 and Fig. 4.15, respectively, which are the comparisons between the HCPMXIO and HCPMXIO-SR. As shown in Fig. 4.14 and Fig. 4.15, the ground bounce effects are reduced by the HCPMXIO-SR.

Table 4.3

The simulation results of the HCPMXIO and HCPMXIO-SR.

Parameters HCPMXIO

Power Consumption 28 μW/MHz 29 μW/MHz

Power Consumption 28 μW/MHz 29 μW/MHz