具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計

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(1)國立交通大學電子工程學系碩. 電子研究所碩士班士. 論. 文. 具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計. Mixed-Voltage I/O Buffers with Slew-Rate Control in Nanoscale CMOS Processes. 研究生. : 胡芳綾. 指導教授. : 柯明道. 教授. 中華民國九十五年七月.

(2) 具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計 Mixed-Voltage I/O Buffers with Slew-Rate Control in Nanoscale CMOS Processes. 研究生：胡芳綾. Student : Fang-Ling Hu. 指導教授：柯明道教授. Advisor : Prof. Ming-Dou Ker. 國立交通大學電子工程學系電子研究所碩士班碩士論文 A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical and Computer Engineering National Chiao-Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electronics Engineering July 2006 Hsin-Chu, Taiwan, Republic of China. 中華民國九十五年七月.

(3) 具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計. 學生: 胡芳綾. 指導教授: 柯明道教授國立交通大學. 電子工程學系. 電子研究所碩士班. ABSTRACT (CHINESE). 摘要隨著製程的進步，電晶體所能承受的最大節點電壓，包括閘極-源極電壓 (Vgs)，閘極-汲極電壓 (Vgd) 及汲極-源極電壓 (Vds)，必須隨著變小以確保電路有足夠大的生存時間。此外電路的操作速度越來越快，使得接地彈跳 (ground bounce) 越來越嚴重，影響電路的操作表現變差。在微電子系統中，以較早的 CMOS 製程技術所設計的電路，使用相對於先進製程所能容忍的較大工作電壓。因此在傳輸介面上，以先進製程設計的晶片可能會接收比它正常工作電壓更大的電壓訊號。而混合電壓輸出入緩衝器 (mixed-voltage I/O buffers) 普遍的應用在傳輸介面上，在確保生存時間的情況下接收較高電壓的訊號，並且以較低的操作電壓工作來達到高速、低功率的電路需求。而在製程中使用具較薄閘極氧化層 (gate-oxide) 的電晶體來設計混合電壓輸出入緩衝器可以有較低的成本、較短的電路製造時間以及較高的操作速度。雖然這樣的混合電壓輸出入緩衝器在傳送及接收模式下，不會遭受到閘極氧化層劣化 (gate-oxide degradation) 、熱載子效應 (hot-carrier effect) 的問題，但是當電路在接收高電壓訊號模式轉換為傳送模式的過程，電晶體可能會因熱載子效應劣化。在深次微米製程下，電晶體通道越來越短，使得電場強度變強，因而熱載 -i-.

(4) 子效應更加嚴重，成為設計穩定可靠電路的重要議題之一。在本篇論文當中，提出了兩個混壓電路設計，無論在接收、傳送模式，或是接收轉傳送的過程都不會有閘極氧化層劣化及熱載子效應的問題。其中一個電路具有抑制熱載子效應的電路，並且可以維持原本電路的電流驅動能力。另一個則是應用阻絕的 NMOS 電晶體 (blocking NMOS) 來避免熱載子效應造成劣化。此兩電路以 0.18-μm 1P6M CMOS 製程技術實現，操作速度高至 266 MHz，並且接收 1.5-V/3.3-V 輸入訊號，傳送 1.5-V 輸出訊號，可與具 PCI-X 2.0 規格應用相容。在論文最後，提出在混壓介面電路上的控制電壓迴轉率 (slew-rate control)的電路設計。這樣的電路設計可以幫助改善在電源線上的接地彈跳效應，藉此達到較高表現的高速輸出入電路設計 (high speed I/O circuit)。此外，進一步改善接地彈跳效應的電路設計技巧在此篇論文中做了討論及整理。. - ii -.

(5) Mixed-Voltage I/O Buffers with Slew-Rate Control in Nanoscale CMOS Processes Student: Fang-Ling Hu. Advisor: Prof. Ming-Dou Ker. Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University. ABSTRACT (ENGLISH) ABSTRACT. Transistors fabricated with thin gate oxides are vulnerable to dielectric damage and reliability problems due to excessive electric fields. The difference between operating voltage and maximum allowed terminal voltages including gate-source voltage (Vgs), gate-drain voltage (Vgd) and drain-source voltage (Vds) of MOS transistors have decreased drastically with the advancement of CMOS process. Also, the ground bounce effects get worse with increasing operating speed. These present special challenges for I/O designers. With compatibility to the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes will face to the interface of input signals with voltage levels higher than their normal supply voltage (VDD). As a result, mixed-voltage I/O buffers with only thin-oxide devices have been designed with advantages of less fabrication time in process, less cost and higher operating speed to communicate the advanced circuits with the earlier ones.. -iii-.

(6) Although such mixed-voltage I/O buffers have overcome several problems, such as gate-oxide reliability [1], hot-carrier degradation [2], and the undesired circuit leakage paths between chips [3], in receive mode and transmit mode, they often suffer from hot-carrier degradation during the transition from receiving high-level voltage to transmitting low-level voltage. The hot-carrier induced degradation, however, becomes one of the most important reliability concerns since the MOSFET devices feature extremely short channel length and high electric field in the nano-meter CMOS technologies. In this thesis, two mixed-voltage I/O buffers realized with only thin-oxide devices to receive 2xVDD-tolerant input signals without suffering the hot-carrier reliability issue are proposed. The mixed-voltage I/O buffer using two-stacked NMOS transistors are designed with new proposed hot-carrier prevented circuit. In this design, the driving capacity will be sustained. The other I/O buffer is designed with two blocking NMOS devices and dynamic gate-controlled circuit to overcome gate-oxide reliability problem and hot-carrier degradation. These two I/O buffers have been fabricated in a 0.18-μm 1P6M CMOS process. From experimental results, the fabricated 2xVDD-tolerant I/O buffers can support the operating speed of up to 266 MHz, which can meet the applications of PCI-X 2.0. Furthermore, the mixed-voltage I/O buffers with slew-rate control are proposed to reduce ground bounce and achieve high circuit performance in high-speed interfaces. The design based on the mixed-voltage I/O buffer with blocking NMOS devices and dynamic gate-controlled circuit has been fabricated in a 0.18-μm 1P6M CMOS process. The other circuit techniques to further reduce ground bounce are also introduced in last part of the thesis.. -iv-.

(7) 誌謝. ACKNOWLEDGEMENT 碩士二年轉眼間就要畢業了，在這二年當中，首先要感謝的是我的指導教授，柯明道博士的殷殷教誨，在研究上給予指導與建議，遇到挫折時給予我鼓勵，使我對自己更有信心；教導我們做事情要抱持嚴謹的態度，待人處事要圓融等，平常也會關心我們的生活狀況，亦師亦友，讓我獲益良多。此外，由於老師的努力，讓我們常有晶片驗證的機會，在研究上不會有後顧之憂，也常常為了修改我們的論文而廢寢忘食。因此，我要向柯明道博士致上我最深的謝意，謝謝您讓我有今天的成長。其次我要感謝已經從本實驗室畢業的莊凱嵐學長，在我剛進實驗室時，耐心地指導我量測、電路設計等，給予我很大的幫助，使我在碩士生涯一開始不至於手足無措。特別感謝陳世倫博士這二年來給予我研究上最大的幫助，指導我電路設計、模擬與量測，給予我建議使我不限於瓶頸，謝謝您的幫助使得我能夠順利完成碩士論文。而在這段求學的過程中，『工研院系統晶片技術發展中心』的『電路設計部』、『混合式積體電路設計部』及『高頻積體電路設計部』，給予我許多研究資源，從實驗晶片的下線及量測設備的支援協助，使我實驗順利完成。在此特別感謝吳文慶組長、簡丞星副組長、陳世宏、黃柏獅、徐育達、張伯瑋、梁詠智、洪項彬、黃清吉、甘瑞銘、劉嘉俊、林崇偉、吳思賢、余永凌等諸位學長以及田季平小姐、熊櫻霞及劉玉珠女士，在實驗、量測設備的協助以及量測上遇到困難時，所給予我的幫忙。也感謝『奈米晶片與系統實驗室』的許勝福、顏承正、陳榮昇、陳世宏、張瑋仁、蕭淵文、吳建樺、周宗信、黃靖驊、王資閔、李宇軒、廖宏泰等諸位實驗室學長以及學弟們，在各方面給予我許多幫助使我能順利完成碩士論文。感謝『奈米晶片與系統實驗室』及助理卓慧貞小姐給予我在研究上的資源及行政上的幫助，讓我完成學業。接著要感謝的是一起打拼的同學們，怡凱、佳惠、泰翔、志遠、宛儀、豪傑、汝玉、志賢、立龍、國慶、允斌、仲朋及必超，大家一起修課、熬夜，出遊、拍照玩鬧，讓我的碩士生活充滿歡樂；互相扶持，加油打氣讓我能充電再繼續努力。謝謝蘭友會的伙伴們，毛龍、小黑、柏村、黃帝、阿睿、卡球和胖中，謝謝你們一直以來的陪伴。最後要致上萬分的感謝，謝謝我的父母、家人，感謝他們一直以來的關心與支持，栽培我讀書讓我有今天的成就。最後祝福我的師長、家人、朋友及學弟妹們事事順心、身體健康。胡芳綾九十五年七月 -v-.

(8) CONTENTS ABSTRACT (CHINESE) .......................................................... i ABSTRACT (ENGLISH)........................................................iii ACKNOWLEDGEMENT ....................................................... v TABLE CAPTIONS ................................................................ ix FIGURE CAPTIONS ............................................................... x Chapter 1 Introduction ............................................................ 1 1.1 1.2 1.3. MOTIVATION .................................................................................................1 MIXED-VOLTAGE I/O BUFFERS .....................................................................2 HOT-CARRIER EFFECT ..................................................................................5 1.3.1 The Mechanism of Hot-Carrier Effect ...........................................6 1.3.2 Hot-Carrier-Induced Lifetime Issue ..............................................8 1.3.3 Hot-Carrier Issue in Typical Mixed-Voltage I/O Buffers...............9 1.4 BRIEF INTRODUCTION TO PCI-X 2.0 [17]....................................................11 1.5 THESIS ORGANIZATION ...............................................................................11. Chapter 2 Prior Designs on Mixed-Voltage I/O Buffer with a Tolerant Voltage of 2xVDD .................................. 13 2.1 PRIOR DESIGN I: A MIXED-VOLTAGE I/O BUFFER WITH GATE-TRACKING CIRCUIT AND DYNAMIC N-WELL BIAS CIRCUIT ...................................................13 2.1.1 Design Concept............................................................................13 2.1.2 Circuit Description ......................................................................16 2.1.3 Hot-Carrier Issues in GTCMXIO ................................................18 2.2 PRIOR DESIGN II: A MIXED-VOLTAGE I/O BUFFER WITH BLOCKING NMOS AND DYNAMIC GATE-CONTROLLED CIRCUIT ........................................................19 2.2.1 Circuit Description ......................................................................19 2.2.2 Hot-Carrier Issues in SBNMXIO .................................................22. Chapter 3 Reliability Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Effect .......... 24 -vi-.

(9) 3.1 INTRODUCTION ...........................................................................................24 3.2 2XVDD-TOLERANT I/O BUFFER WITH DOUBLE-CASCODE STRUCTURE [14], [25] ……………………………………………………………………………24 3.3 NEW DESIGN I:MIXED-VOLTAGE I/O BUFFER WITH NEW PROPOSED HOT-CARRIER-PREVENTED CIRCUIT ....................................................................27 3.3.1 Design Concept............................................................................27 3.3.2 Circuit Implementation ................................................................29 3.3.3 Whole 2xVDD-Tolerant I/O Buffer With Hot-Carrier-Prevented Circuit ..........................................................................................31 3.3.4 Simulation Results........................................................................33 3.3.5 Summary for Simulation Results..................................................38 3.4 NEW DESIGN II: MIXED-VOLTAGE I/O BUFFER WITH TWO BLOCKING NMOS DEVIES AND DYNAMIC GATE-CONTROLLED CIRCUIT ..............................40 3.4.1 Design Concept............................................................................40 3.4.2 Circuit Implementation ................................................................42 3.4.3 Simulation Results........................................................................44 3.5 EXPERIMENTAL RESULTS ............................................................................47 3.5.1 Measurement Settings ..................................................................47 3.5.2 Experimental Results for HCPMXIO...........................................50 3.5.3 Experimental Results for TBNMXIO ...........................................54 3.6 DISCCUSION AND SUMMARY .......................................................................58 3.6.1 Discussion ....................................................................................58 3.6.2 Summary ......................................................................................59. Chapter 4 Mixed-Voltage I/O Buffers with Slew-Rate Control ................................................................... 60 4.1. INTRODUCTION ...........................................................................................60. 4.2. SLEW-RATE CONTROL IN TYPICAL I/O BUFFERS .........................................61 4.2.1 Conventional Slew-Rate Control .................................................61 4.2.2 Improved slew-rate control to reduce short-circuit current.........62 4.3 SLEW-RATE CONTROL ON THE TBNMXIO .................................................63 4.3.1 Circuit Implementation ................................................................63 4.3.2 Simulation Results........................................................................64 4.3.3 Ground Bounce ............................................................................67 4.4 SLEW-RATE CONTROL ON THE HCPMXIO .................................................72 4.4.1 Reliability Issues ..........................................................................72 4.4.2 New Slew-Rate Control on Mixed-Voltage I/O Buffer .................73 -vii-.

(10) 4.4.3 Simulation Results........................................................................76 4.5 PRINCIPLES FOR FURTHER REDUCING GROUND BOUNCE ............................80 4.5.1 Distributed Technique ..................................................................81 4.5.2 Weighted Technique......................................................................83 4.5.3 Separate Power Pad ....................................................................86 4.6 EXPERIMENTAL RESULTS ............................................................................88 4.7 DISCUSSION AND SUMMARY .......................................................................95 4.7.1 Discussion ....................................................................................95 4.7.2 Summary ......................................................................................96. Chapter 5 Conclusion and Future Works............................. 97 5.1 5.2. CONCLUSION...............................................................................................97 FUTRUE WORKS ..........................................................................................98. REFERENCES ....................................................................... 99 VITA. 102. -viii-.

(11) TABLE CAPTIONS Table 1.1 The specification for PCI-X 266 in mixed-voltage I/O buffer ..................11 Table 2.1 Operations of the pre-driver ......................................................................16 Table 2.2 Operations of the dynamic gate-controlled circuit in the mixed-voltage I/O buffer with blocking NMOS [18]. .............................................................20 Table 3.1 The operations of the 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors. .....................................................................................26 Table 3.2 The operations of the proposed hot-carrier-prevented circuit in 2xVDD-tolerant I/O buffer. .......................................................................29 Table 3.3 The simulation results of mixed-voltage I/O buffers with/without hot-carrier-prevented mechanisms.............................................................39 Table 3.4 The operations of the dynamic gate-controlled circuit in TBNMXIO ......41 Table 3.5 The simulated results of mixed-voltage I/O buffers with blocking NMOS devices. ......................................................................................................46 Table 3.6 The measured parameters of prior designs, GTCMXIO and TSTMXIO, and HCPMXIO.................................................................................................54 Table 3.7 The measured parameters of SBNMXIO and TBNMXIO........................58 Table 4.1 The simulation results of TBNMXIO with/without slew-rate control. .....66 Table 4.2 The operations of the HCPMXIO-SR .......................................................76 Table 4.3 The simulation results of the HCPMXIO and HCPMXIO-SR. ................78 Table 4.4 Simulation results of the HCPMXIO-SR with different number of parallel output drivers in transmit mode.................................................................82 Table 4.5 Simulation results of the TBNMXIO-SR with different transistor sizes of output transistors in transmit mode. ..........................................................85 Table 4.6 The measured parameters of the TBNMXIO and TBNMXIO-SR............93. -ix-.

(12) FIGURE CAPTIONS Fig. 1.1 Fig. 1.2 Fig. 1.3 Fig. 1.4 Fig. 1.5 Fig. 2.1 Fig. 2.2 Fig. 2.3 Fig. 2.4 Fig. 2.5 Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6. Fig. 3.7 Fig. 3.8 Fig. 3.9. Block diagram of bidirectional I/O buffer....................................................3 Block diagram of a mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias voltage.........................................................................4 Simplified mixed-voltage I/O buffer with two-stacked transistors. .............5 The diagram of hot-carrier effect. ................................................................7 Channel-hot-carrier lifetime as a function of Vds and Vgs. (typical behavior for 0.25-μm CMOS process) .......................................................................9 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices......................................................................................14 The circuit implementation of pre-driver. ...................................................15 The mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit proposed in [9].........................................................................17 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit................................................................................20 Circuit implementation of the dynamic gate-controlled circuit in the SBNMXIO.................................................................................................21 The brief schematic of 2xVDD-tolerant I/O buffer with three-stacked transistors to overcome hot-carrier issue. ..................................................26 The mixed-voltage I/O buffer using three-stacked NMOS transistors (TSTMXIO)...............................................................................................27 The new design concept to overcome the hot-carrier issue in the 2xVDD-tolerant I/O buffer with only two-stacked transistors..................28 The implementation of the new proposed hot-carrier-prevented circuit for 2xVDD-tolerant I/O buffer with two-stacked transistors. .........................28 The new mixed-voltage I/O buffer with hot-carrier-prevented circuits (HCPMXIO). .............................................................................................32 The corresponding hot-carrier-prevented circuits in HCPMXIO. (a) The hot-carrier-prevented circuit for the MN0. (b) The hot-carrier-prevented circuit for the MN3. (c) The hot-carrier-prevented circuit for the MN2 and MP2. ..........................................................................................................32 The simulation environment.......................................................................33 Simulation waveforms of the HCPMXIO in receiving mode with 3.3-V 266-MHz input signals. .............................................................................34 Simulation waveforms of the HCPMXIO in transmitting mode with 266-MHz output signals. ...........................................................................35 -x-.

(13) Fig. 3.10 The drain-source voltages of the MN0 and MN3 during the transition from receiving 3.3V input signal to transmitting 0-V output signal. (a) The drain-source voltage of the MN0. (b) The drain-source voltage of the MN3. ...................................................................................................................36 Fig. 3.11 The drain-source voltages of MN2 during the transition from receiving 3.3-V input signal to transmitting 1.5-V output signal..............................37 Fig. 3.12 Simulation waveforms of the HCPMXIO in transition with increasing the delay of high level at OE signal.................................................................38 Fig. 3.13 The new proposed 2xVDD-tolerant I/O buffer with two blocking NMOS devices and dynamic gate-controlled circuit to solve the hot-carrier reliability issue (TBNMXIO). ...................................................................41 Fig. 3.14 Circuit implementation of the dynamic gate-controlled circuit in the TBNMXIO.................................................................................................43 Fig. 3.15 Simulation waveforms of the TBNMXIO operating at 266 MHz when receiving 0V-to-3.3V input signals at I/O PAD. .......................................44 Fig. 3.16 Simulation waveforms of the TBNMXIO operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD..................................45 Fig. 3.17 Comparisons of drain-source voltages between the prior design SBNMXIO and new design TBNMXIO during the transition from receiving 2xVDD input signal to transmitting 0-V output signal. ..........................................45 Fig. 3.18 The photograph of the new proposed 2xVDD-tolerant I/O buffer with hot-carrier-prevented circuits (HCPMXIO) in a 0.18-μm 1.8-V CMOS process. ......................................................................................................48 Fig. 3.19 The photograph of the new proposed 2xVDD-tolerant I/O buffer with blocking NMOS devices (TBNMXIO) in a 0.18-μm 1.8-V CMOS process. ...................................................................................................................48 Fig. 3.20 The measurement setup of mixed-voltage I/O buffer (a) in receive mode and (b) in transmit mode...................................................................................49 Fig. 3.21 The PCB view of tested mixed-voltage I/O buffers. ...................................50 Fig. 3.22 Measured waveforms of the HCPMXIO operating at (a) 266 MHz and (b) 1 MHz when receiving 0V-to-1.5V input signals at I/O PAD. .....................51 Fig. 3.23 Measured waveforms of the HCPMXIO operating at (a) 266 MHz and (b) 1 MHz when receiving 0V-to-3.3V input signals at I/O PAD. .....................52 Fig. 3.24 Measured waveforms of the HCPMXIO operating at (a) 266 MHz and (b) 1 MHz when transmitting 0V-to-1.5V output signals to I/O PAD...............53 Fig. 3.25 Measured waveforms of the TBNMXIO operating at (a) 266 MHz and (b) 1 MHz when receiving 0V-to-1.5V input signals at I/O PAD. .....................55 Fig. 3.26 Measured waveforms of the TBNMXIO operating at (a) 266 MHz and (b) -xi-.

(14) 1MHz when receiving 0V-to-3.3V input signals at I/O PAD. ...................56 Fig. 3.27 Measured waveforms of the TBNMXIO operating at (a) 266 MHz and (b) 1MHz when transmitting 0V-to-1.5V output signals to I/O PAD..............57 Fig. 3.28 Modified simulation model with bonding wire and transmission line effects. ...................................................................................................................59 Fig. 3.29 Simulation waveforms of the HCPMXIO with transmission line effect in transmit mode with an operating speed of 266 MHz. ................................59 Fig. 4.1 The model for ground bounce effect...........................................................61 Fig. 4.2 Output buffer with conventional slew-rate control. ....................................62 Fig. 4.3 Output buffer with an improved slew-rate control to reduce short-circuit current........................................................................................................63 Fig. 4.4 The TBNMXIO with slew-rate control.......................................................64 Fig. 4.5 Simulation waveforms of the TBNMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD. .................................66 Fig. 4.6 Fig. 4.7 Fig. 4.8. Simulated model of ground bounce. ...........................................................68 Simulation waveforms of ground bounce effects on power lines. .............68 Simulation waveforms of the TBNMXIO-SR with ground bounce effect in transmit mode. ...........................................................................................69 Fig. 4.9 The relation between ground bounce on VDD power line and wire bond inductance on the TBNMXIO and TBNMXIO-SR. (a) The overshoot and (b) the undershoot on VDD power line. ....................................................70 Fig. 4.10 The relation between ground bounce on GND power line and wire bond inductance on the TBNMXIO and TBNMXIO-SR. (a) The overshoot and (b) the undershoot on GND power line. ....................................................71 Fig. 4.11 (a) The mixed-voltage I/O buffer based on the HCPMXIO with slew-rate control. (b) The hot-carrier-prevented circuit for transistor MN0 ,and (c) the hot-carrier-prevented circuit for transistor MN3........................................73 Fig. 4.12 The HCPMXIO with modified slew-rate control........................................76 Fig. 4.13 Simulation waveforms of the HCPMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD. .................................77 Fig. 4.14 The relation between ground bounce on VDD power line and wire bond inductance on the HCPMXIO and HCPMXIO-SR. (a) The overshoot and (b) the undershoot on VDD power line...........................................................79 Fig. 4.15 The relation between ground bounce on GND power line and wire bond inductance on the HCPMXIO and HCPMXIO-SR. (a) The overshoot and (b) the undershoot on GND power line...........................................................80 Fig. 4.16 The undershoot on VDD power line with different number of parallel output drivers. .......................................................................................................82 -xii-.

(15) Fig. 4.17 The overshoot on GND power line with different number of parallel output drivers. .......................................................................................................83 Fig. 4.18 Current distributions of output transistors in the TBNMXIO-SR operated in receive mode..............................................................................................84 Fig. 4.19 The undershoot on VDD power line with different transistor sizes of output driver..........................................................................................................85 Fig. 4.20 The overshoot on GND power line with different transistor sizes of output driver..........................................................................................................86 Fig. 4.21 The second simulation model of ground bounce using two separate VDD pads............................................................................................................87 Fig. 4.22 The undershoot on VDD power line with different number of power pad. 87 Fig. 4.23 The overshoot on GND power line with different number of power pad. ..88 Fig. 4.24 Simulated currents from VDD1 and VDD2 power supply. ........................88 Fig. 4.25 The photograph of the TBNMXIO-SR in a 0.18-μm 1.8-V CMOS process. ...................................................................................................................89 Fig. 4.26 Measured waveforms of the TBNMXIO-SR operating at (a) 266 MHz and (b) 1 MHz when receiving 0V-to-1.5V input signals at I/O PAD. ..................90 Fig. 4.27 Measured waveforms of the TBNMXIO-SR operating at (a) 266 MHz and (b) 1 MHz when receiving 0V-to-3.3V input signals at I/O PAD. ..................91 Fig. 4.28 Measured waveforms of the TBNMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD. .................................92 Fig. 4.29 The setup for ground bounce measurement. ...............................................93 Fig. 4.30 Measured ground bounce on VDD pad of TBNMXIO (without slew-rate control).......................................................................................................94 Fig. 4.31 Measured ground bounce on VDD pad of TBNMXIO-SR (with slew-rate control).......................................................................................................94 Fig. 4.32 The measurement method of ground bounce effect where seven I/O cells switch simultaneously................................................................................96 Fig. 4.33 The measurement setting for testing the receiving operations of mixed-voltage I/O buffer. ..........................................................................96. -xiii-.

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(17) Chapter 1 Introduction. 1.1 MOTIVATION With new generations of CMOS technologies, the transistors’ dimensions have been scaled down to reduce the silicon cost, as well as, to increase circuit performance and operating speed. The thickness of gate oxide becomes much thinner in order to reduce the core power supply voltage (VDD) for resulting in lower power consumption. In the meanwhile, the maximum tolerable voltage across the transistor terminals (drain, source, gate, and bulk) should be correspondingly decreased to ensure lifetime. With compatibility to the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes will face to the interface of input signals with voltage levels higher than their normal supply voltage (VDD). Such mixed-voltage I/O interfaces must be designed to overcome several problems, such as gate-oxide reliability [1], hot-carrier degradation [2], and the undesired circuit leakage paths between chips [3]. Since the mixed-voltage I/O buffer communicates ICs in advanced process with those in earlier process, the mixed-voltage I/O buffers in this thesis will be designed to meet PCI-X 2.0 specification which is compatible with the prior PCI standards. The hot-carrier induced degradation, however, becomes one of the most important reliability concerns since the MOSFET devices feature extremely short channel length and high electric field in the deep sub-micron technologies. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. -1-.

(18) Such hot-carried induced degradation causes a lot of device degradation, such as the deviation of threshold voltage (Vth), transconductance (gm), and linear (IDLIN) and saturation (IDSAT) drain current [4]. In time, substantial device parameter degradation can occur, resulting in device failure. Thus, it is an important issue to provide a robust circuit design in circuit techniques with sufficient lifetime. In high-speed interface, the output buffer is a major contributor to the pin-to-pin delays because of output loading as well as package and board parasitics. The channel widths of output buffer are always increased to have high driving capacity and high speed, which results in large power/ground noise due to outputs switching simultaneously. Since the input pads are connected to the same power/ground bus, power/ground noise must be well controlled to avoid any false switching. Even though the internal power/ground buses are separated from the external (I/O buffers) power/ground buses, they are connected through a VDD/VSS package plane in multilayer package. Therefore, the out buffer must be designed with considerations of power/ground noise to achieve high performance.. 1.2 MIXED-VOLTAGE I/O BUFFERS Fig. 1.1 shows the block diagram of a bidirectional input/output (I/O) buffer in general. As the output enable signal OE is high (VDD), the mixed-voltage I/O buffer is operating in transmit mode to transmit output signals from Dout to I/O PAD. On the other hand, the mixed-voltage I/O is operating in receive mode to receive input signals from I/O PAD to Din (internal circuit) if the OE is low (0V). In dual-oxide (thin-oxide and thick oxide) CMOS process, the core circuits usually use thin-oxide devices using low power supply voltage to reduce power consumption and silicon area while the interface circuits use thick-oxide to tolerant higher voltages and prevent -2-.

(19) reliability problems in traditional mixed-voltage I/O buffers. A mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias voltage is shown in Fig. 1.2. The mixed-voltage I/O buffer transmits GND-to-VDD (low voltage level) output signals and receives GND-to-VDDH (high voltage level) input signals. The pre-driver circuit generates control signals of output transistors MN and MP. In the mixed-voltage I/O buffer, the output transistors, gate-tracking circuits, and input circuit, INV, are thick-oxide devices to overcome reliability problems. The pre-driver circuit uses thin-oxide devices since the input data come from internal core circuit which uses low voltage level. In order to avoid leakage current path from the I/O PAD to the power supply (VDD) through the parasitic drain-to-well pn-junction diode in the pull-up PMOS device, MP, a higher external voltage (VDDH) is used to bias the bulk of the MP. In addition, a gate-tracking circuit is required to avoid the leakage current path induced by the incorrect conduction of the MP. Such mixed-voltage interface applications with dual-oxide devices can successfully overcome the gate-oxide reliability and hot-carrier degradation problem [5]-[6].. Fig. 1.1. Block diagram of bidirectional I/O buffer.. -3-.

(20) Fig. 1.2 Block diagram of a mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias voltage.. Although the mixed-voltage I/O buffers with dual-oxide devices can successfully solve aforementioned problems, there are some drawbacks in these mixed-voltage I/O buffers. Fist of all, an extra pad and another power supply (VDDH) are required for the external bias voltage, which results in the increase of silicon area and cost. Second, the driving capacity is decreased due to higher threshold voltage of thick-oxide device when the gates of output transistors are controlled by pre-driver circuit with thin-oxide devices. Thirdly, the threshold voltage of the pull-up PMOS device (MP) is also increased since the bulk of the pull-up PMOS device (MP) is connected to a higher voltage (VDDH), which results in body effect. Because the driving capacity is decreased, the larger device dimension is required for the pull-up PMOS device to achieve the desired driving specifications. As a result, the silicon area in such I/O buffers is increased. Moreover, the manufacturing time of thick-oxide device is even. -4-.

(21) three times large than that of thin-oxide device. For these aforementioned reasons, the mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias is unsuitable for the low-cost commercial ICs. Considering these limitations, several mixed-voltage I/O buffers with only thin-oxide devices have been reported in [7]-[10]. A mixed-voltage I/O buffer with a 2xVDD tolerant voltage is often designed using cascode transistors without thick-oxide devices. Fig. 1.3 shows a simplified mixed-voltage I/O buffer with two-stacked transistors to be tolerant of 2xVDD, where pull-down signal (PD) and pull-up signal (PU) are the controlled signals from pre-driver. In Fig. 1.3, the input circuit and pull-up network of the mixed-voltage I/O circuit are simplified into block diagrams for convenience. The 2xVDD tolerant mixed-voltage I/O buffers typically receive 2xVDD input signals and transmit 1xVDD output signals.. Fig. 1.3 Simplified mixed-voltage I/O buffer with two-stacked transistors.. 1.3 HOT-CARRIER EFFECT The mechanism of hot-carrier effect and the hot-carrier issue in the mixed-voltage I/O buffers are described in the following.. -5-.

(22) 1.3.1 The Mechanism of Hot-Carrier Effect A cross section of a typical enhancement-mode n-channel MOS (NMOS) transistor is shown in Fig. 1.4 where the source terminal is connected to ground. Heavily doped n-type source and drain regions are fabricated in a p-type substrate. A thin layer of silicon dioxide is grown over the substrate material and a conductive gate material covers the oxide between source and drain. In operation, the gate-source voltage modifies the conductance of the region under the gate, allowing the gate voltage to control the current following between source and drain. Now in Fig. 1.4, the positive voltages, VG and VD, are applied to the gate and drain, respectively. An inversion layer is produced as the VG is equal to or larger than the Vth of NMOS device. When the value of VD is increased, the induced conducting channel narrows at the drain end. The induced electron charge at the drain end approaches zero as VD approaches (VG - Vth). That is, the channel is no longer connected to the drain when VD > VG – Vth, which is known as pinch-off. At this time, the electric field starts rise dramatically at the pinch-off point of the NMOS device. In the high electric field, carriers are accelerated to high velocities, reaching a maximum kinetic energy (hot) near the device drain. If the carrier energy is high enough, impact ionization can occur, creating electron-hole pair. The generated electrons called secondary electrons tend to be swept to the drain and generated holes called secondary holes swept into the substrate in the NMOS device.. -6-.

(23) Fig. 1.4. The diagram of hot-carrier effect.. Some of the electrons generated in the space charge region are attracted to the oxide due to the electric field induced by the positive gate voltage, VG. These generated electrons have energies far greater than the thermal-equilibrium value and are called hot electrons (or hot carriers) [11]. If the electrons have energies on the order of 1.5 eV, they may be able to tunnel into the oxide. In some cases the generated holes and electrons can attain enough energy to surmount the Si–SiO2 barrier and become trapped in the gate oxide. In general, injection from Si into SiO2 is much more likely for hot electrons than for hot holes because (a) electrons can gain energy from the electric field much more readily than holes due to their smaller effective mass, and (b) the interface energy barrier is larger for holes (≈4.6 eV) than for electrons (≈3.1 eV) [12]. The charge trapping in interface states causes a shift in threshold voltage, additional surface scattering, and reduced mobility. The hot electron charging effects are continuous processes, so the device degrades over a period of time. There are several techniques used to reduced maximum electric field in process and device structures, such as the lightly doped drain (LDD) structure [11]. -7-.

(24) and grooved gate MOSFETs [13]. In this thesis, the mixed-voltage I/O buffers are designed without suffering hot-carrier effect in circuit techniques.. 1.3.2 Hot-Carrier-Induced Lifetime Issue The hot-carrier degradation effect depends among others on the transistor’s length and its biasing conditions [14]: z. The relation between the drain–source voltage and lifetime is exponential:. τ life ∝ exp( A / Vds ). (1-1). , where A is 80-120 V for deep submicron processes. This relation assumes worst-case settings of the gate-source voltage. z. The length-lifetime dependency is relatively weak:. τ life ∝ LB. (1-2). , where B = 1-5. z. The relation between gate-source voltage and lifetime is more complex. For low gate-source voltages the transistor is “off” resulting in no current and hence in no hot carriers. For very high gate-source voltages (and fixed rain–source voltage) the transistor is in the linear region resulting in no hot carriers either. Somewhere in the middle, both the drain current is large and the transistor is well in saturation. In this region, the hot-carrier degradation is worst and hence the lifetime is poorest.. A typical hot-carrier-based lifetime versus biasing plot for a minimum length transistor is given in Fig. 1.5, where Vdd,nom is the normal power supply voltage in a given process. Note that especially the drain-source voltage of a MOS transistor. -8-.

(25) strongly affects the lifetime. It is recommended that the maximum terminal voltages of a MOS transistor (Vgs, Vgd and Vds) which can be applied to the device at worst case DC stress conditions are below Vdd,nom to ensure a device lifetime of 10 years [15].. Fig. 1.5. Channel-hot-carrier lifetime as a function of Vds and Vgs. (typical behavior. for 0.25-μm CMOS process). 1.3.3 Hot-Carrier Issue in Typical Mixed-Voltage I/O Buffers The hot-carrier induced degradation or gate-oxide reliability in typical 2xVDD-tolerant I/O buffer shown in Fig. 1.3 may exist in the following two states: (1) the state of receiving 2xVDD input signal, and (2) the state of a transition from receiving 2xVDD input signal to transmitting 0-V output signal. When such 2xVDD-tolerant I/O buffer receives 2xVDD input signals, PU and PD signals are kept at VDD and 0 V, respectively, to disable the output circuit. Since the transistor MN1 in Fig. 1.3 is turned off, the transistor MN0 is weakly “on”. This results in a voltage of about VDD at the source of MN0. In each of these two-stacked transistors, the voltages drop across the gate-oxide and the drain-source voltage are -9-.

(26) both lower than or equal to the supply voltage (VDD). Therefore, there is neither hot-carrier degradation nor gate-oxide overstress issues in the mixed-voltage I/O buffer when receiving 2xVDD input signal. When the 2xVDD-tolerant I/O buffer has the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the I/O PAD originally has a voltage of 2xVDD before being pulled down. At this transition moment, the transistor MN1 is turned on by PD signal from pre-driver, and the transistor MN0 is subsequently switched on when its source is pulled down by the MN1. The voltage at the drain of MN1 can be approximated as the saturation drain voltage (VDSAT) [16]. For example, the voltage at the source of the transistor MN0 is about ~0.5V in a 0.18-μm CMOS process. Since the original 2xVDD voltage at I/O PAD is not pulled down immediately, the drain-source voltage of MN0 would be larger than the normal supply voltage (VDD) during this transition, which results in the significant hot-carrier degradation on the transistor MN0. From this point, the traditional I/O buffer with two-stacked transistors in Fig. 1.3 is difficult to build a reliable 2xVDD-tolerant I/O buffer with only 1xVDD devices in a given CMOS technology, unless an additional circuit is provided to prevent such hot-carrier degradation during signal transition. There are several ways to boost the voltage handling capabilities of the circuit in Fig. 1.3 without using any process modification include: . using different aspect ratios for the lower and for the cascode transistor;. . using longer transistors to limit channel hot-carrier degradation;. . using a nonstationary gate voltage for the cascode transistor;. . using more stacked transistors.. In this thesis, an external circuit is proposed to suppress hot-carried degradation without increasing the number of stacked transistors.. -10-.

(27) 1.4 BRIEF INTRODUCTION TO PCI-X 2.0 [17]. PCI-X 2.0 is a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Migration to PCI-X 266 and PCI-X 533 is further simplified by retaining hardware and software compatibility with previous generations of PCI and PCI-X. As a result, new designs can immediately connect with hundreds of PCI and PCI-X products that are currently available. There are 4 speed grades in the PCI-X 2.0 specification: PCI-X 66, PCI-X 133, PCI-X 266, and PCI-X 533. The PCI-X 66 and PCI-X 133 speed grades were included in the PCI-X 1.0 specification. 100MHz PCI-X has been implemented in the market by using PCI-X 133 adapter cards. Both PCI-X 266 and PCI-X 533 are new to PCI-X 2.0; they are the 266MHz and 533MHz versions of the specification. PCI-X 266 and PCI-X 533 devices are electrically compatible with 3.3V and 1.5V I/O buffers only. They are not compatible with 5V PCI. The specification for PCI-X 266 in the mixed-voltage I/O buffer designed in this thesis is summarized in Table 1.1.. Table 1.1 The specification for PCI-X 266 in mixed-voltage I/O buffer Operating Modes. Voltage swing at I/O PAD. Receive mode. 1.5V/3.3V. Transmit mode. 1.5V. 1.5 THESIS ORGANIZATION In chapter 2, two prior designs of mixed-voltage I/O buffers which tolerate 2xVDD signals will be introduced. Thesis two mixed-voltage I/O buffers are designed -11-.

(28) with only thin-oxide devices in a given CMOS process and do not suffer gate-oxide degradation and hot-carrier degradation in both steady states of receive mode and transmit mode. The I/O buffers, however, suffer hot-carrier degradation in transitions from switching receive mode to transmit mode which will be pointed out in chapter 2. Two new mixed-voltage I/O buffers without suffering hot-carrier degradation in transitions will be proposed in chapter 3. The simulation and experimental results are also shown in this chapter. In chapter 4, the mixed-voltage I/O buffers proposed in chapter 3 are redesigned with slew-rate control to improve ground bounce effects. Besides, some techniques for further improving ground bounce are pronounced. The last chapter recapitulates the major consideration of this thesis and concludes with suggestion for future investigation.. -12-.

(29) Chapter 2 Prior Designs on Mixed-Voltage I/O Buffer with a Tolerant Voltage of 2xVDD In this chapter, two mixed-voltage I/O buffers reported in [10] and [18] are introduced before the proposed reliable mixed-voltage I/O buffers in the thesis. These two mixed-voltage I/O buffers are designed to be tolerant of 2xVDD.. 2.1 PRIOR DESIGN I: A MIXED-VOLTAGE I/O BUFFER WITH GATE-TRACKING CIRCUIT AND DYNAMIC N-WELL BIAS CIRCUIT 2.1.1 Design Concept Fig. 2.1 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit [7]-[8], [19]-[22]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig. 2.1 is used to prevent the leakage current path which is resulted from the incorrect conduction of the pull-up PMOS device when the input signal is higher than VDD. As the mixed-voltage I/O buffer is operating in the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device, MP0, exactly. In the receive mode (tri-state input mode) with an input signal of 2xVDD, the gate-tracking circuit will charge the gate terminal of the MP0 to 2xVDD to turn off the MP0 completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the MP0 at VDD to turn off the MP0 completely, and to prevent the overstress on the -13-.

(30) gate oxide of the MP0 when the 0-V input signal is received from I/O PAD. Moreover, the dynamic n-well bias circuit shown in Fig. 2.1 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device MP0. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at VDD so that the threshold voltage of the pull-up PMOS device isn’t increased due to the body effect. In the receive mode with an input signal of 2xVDD, the dynamic n-well bias circuit will charge the floating n-well to 2xVDD to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. On the other hand, the dynamic n-well bias circuit will bias the floating n-well at VDD when the input signal at the I/O pad is 0V.. Fig. 2.1 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.. As shown in Fig. 2.1, the extra transistors, MN2 and MP1, which are compared to Fig. 1.2, are added in the input circuit. The transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The. -14-.

(31) transistor MP1 is used to prevent unnecessary leakage current in the inverter INV1. Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV1 will rise up to “VDD-Vth” when the input signal at the I/O pad is 2xVDD in the receive mode. The transistor MP1 will pull the input node of inverter INV1 up to VDD when the output node of inverter INV1 is pulled down to 0V. Therefore, the gate-oxide reliability problem of the input buffer can be solved. Moreover, the circuit implementation of pre-driver composed of a NAND gate and NOR gate is shown in Fig. 2.2. The operations of pre-driver are list in Table 2.1. When the output enable signal OE is 0V, the mixed-voltage I/O buffer is operated in receive mode. The pull-up signal (PU) and pull-down signal (PD) are set to VDD and 0V, respectively, to turn off pull-up device and pull-down devices. On the contrary, both PU and PD are set to VDD to turn off pull-up device and turn on pull-down devices, respectively, in transmitting 0-V output signal, and they are set to 0V to switch on pull-up device and switch off pull-down devices, respectively, in transmitting VDD output signal.. Fig. 2.2 The circuit implementation of pre-driver.. -15-.

(32) Table 2.1 Operations of the pre-driver Operating Modes. OE. Signals at I/O PAD. PU. PD. Receive. 0V. X. VDD. 0. Transmit. VDD. Low (0V). VDD. VDD. Transmit. VDD. High (VDD). 0V. 0V. 2.1.2 Circuit Description Fig. 2.3 shows the mixed-voltage I/O buffer with the dynamic n-well bias circuit and gate-tracking circuit proposed in [10]. For clear illustration, this mixed-voltage I/O buffer is called GTCMXIO in this thesis. When the output control signal OE is at VDD (logic “1”), the mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad rises or falls according to signal Dout, which is controlled by the internal circuits of IC. The pull-down signal, PD, produced by pre-driver is directly connected to the gate terminal of the pull-down NMOS device, MN1. The pull-up signal, PU, is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit which is composed of NMOS transistors MN2-MN4 and PMOS transistors MP2, MP3 and MP5. The transistors MN2 and MP2 comprise a transmission gate. The transistor MN3 in Fig. 2.3 is used to protect the transistor MN4 from gate-oxide reliability problem. The dynamic n-well bias circuit is composed of transistors MP4 and MP6. If the mixed-voltage I/O buffer is operating in transmit mode (OE = VDD), the gate terminal of MP4 will be biased at 0V to bias the floating n-well at VDD by turning on the transistor MP4. At this time, the PU signal is fully transmitted to the gate terminal of the pull-up PMOS device MP0 through the. -16-.

(33) transmission gate, MN2 and MP2. As 0-V output signal is transmitted, the PD signal is set to VDD to turn on the transistor MN1. In the meanwhile, the PU signal is set to VDD to turn off the pull-up device MP0. Consequently, the voltage at the I/O pad and the gate voltage of transistor MP5 are discharged to 0V through transistors MN0 and MN1. Transistor MP5 is turned on until the gate terminal of transistor MP2 is discharged to |Vtp|, where Vtp is the threshold voltage of PMOS device, through transistors MN3 and MN4.. Fig. 2.3 The mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit proposed in [9].. When the proposed I/O buffer is operated in the receive mode, the PU and PD signals are kept at VDD and 0V, respectively, to turn off transistors MP0 and MN1. Signal Din rises or falls according to the signal at the I/O pad in the receive mode. In order to prevent the undesired leakage current from the I/O pad to the power supply (VDD) through the pull-up PMOS device MP0, transistor MP3 is used to track the signal at the I/O pad and to control the gate voltage of transistor MP0. When the. -17-.

(34) voltage level at the I/O pad exceeds “VDD+|Vtp|,” such as 2xVDD, transistor MP3 is turned on to charge the gate terminal of transistor MP0 up to 2xVDD. Thus, transistor MP0 is completely turned off to prevent the leakage current through its channel. If a 0-V input signal is received at I/O PAD, the floating n-well is biased at VDD through the transistor MP4. As the mixed-voltage I/O is operating in the receive mode with an input signal of 2xVDD, another PMOS device MP6 is turned on to bias the floating n-well at 2xVDD. Also, transistor MP4 is turned off to prevent the leakage path by pulling up the gate terminal of MP4 to 2xVDD through transistor MP5. As a result, there is no leakage current path from the I/O pad to the power supply (VDD). Whenever the proposed mixed-voltage I/O buffer is in the transmit mode or the receive mode, the floating n-well is biased at VDD or 2xVDD directly. Thus, the subthreshold leakage problems do not occur in this proposed I/O buffer. Besides, transistor MP5 is also turned on to keep transistor MP2 off in order to prevent another leakage path from the gate terminal of transistor MP0 to the UP signal when the signal at the I/O pad is 2xVDD. Transistors MN0 and MP1 with inverters INV1 and INV2 are used to transfer the input signal from the I/O pad to the internal node Din in the receive mode. Transistor MN0 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The signal at the I/O pad can be successfully transferred to the internal input node Din. This I/O buffer can be correctly operated with neither gate-oxide reliability problem nor any circuit leakage issue in the receive mode.. 2.1.3 Hot-Carrier Issues in GTCMXIO Although the mixed-voltage I/O buffer proposed in [10] does not suffer gate-oxide degradation and leakage issue, it still suffers hot-carrier degradation under the I/O signal transitions. During the transition from receiving 2xVDD input signal to -18-.

(35) transmitting 0-V output signal, the transistor MN0 suffers the hot-carrier degradation mentioned in chapter 1. The hot-carrier degradation will also occur on MN3 device in this traditional 2xVDD-tolerant I/O buffer during this transition since the gate terminal of MP4 is originally biased at 2xVDD through transistor MP5. Besides, the transistors MN2 and MP2 also suffer hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal since the gate terminal of transistor MP0 is initially kept at 2xVDD but the PU signal has been pull down to 0V by the pre-driver to turn on transistor MP0.. 2.2 PRIOR DESIGN II: A MIXED-VOLTAGE I/O BUFFER WITH BLOCKING NMOS AND DYNAMIC GATE-CONTROLLED CIRCUIT. 2.2.1 Circuit Description Fig. 2.4 depicts the mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit proposed in [18], which is called SBNMXIO in this thesis. In Fig. 2.4, VDDH has a high voltage of 2xVDD, which can be generated by the on-chip charge pump circuit [23] or other high-voltage generators. Transistor MNS1 is used to protect the conventional I/O buffer from the high-voltage overstress. The operations of the dynamic gate-controlled circuit in the I/O buffer with blocking NMOS are listed in Table 2.2. When the I/O buffer is in the receive mode, the gate terminal of MNS1 (node 2) is biased at VDD by the dynamic gate-controlled circuit, whereas the pull-up device MP0 and pull-down device MN0 are both turned off by the pre-driver. At this moment, if an input signal of logic ‘0’ (0V) is received from the I/O PAD, node 1 is discharged to 0 V through the transistor MNS1, and this input signal can be successfully transferred to the node Din. When a logic ‘1’ (VDDH) signal is received at the I/O pad, the gate terminal of transistor MNS1 is still biased at VDD, so the -19-.

(36) voltage on node 1 is pulled to “VDD−Vth”. A feedback device MP1 is added to restore the voltage level on node 1 to VDD, which avoids the undesired static dc current through the inverter INV1. In this design, MNS1, MP1, and inverter INV1 can convert the VDDH input signal to VDD signal successfully. Therefore, MNS1 can protect the I/O buffer without suffering high-voltage overstress in both steady states of transmit mode and receive mode.. Fig. 2.4 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit.. Table 2.2 Operations of the dynamic gate-controlled circuit in the mixed-voltage I/O buffer with blocking NMOS [18].. Operating Modes. Signals at I/O PAD. Vg of MP0 (PU). Vg of MNS1 (Node 2). Receive. X. VDD. VDD. Transmit. Low (0V). VDD. VDD. Transmit. High (VDD). 0V. VDDH (2xVDD). -20-.

(37) Fig. 2.5 Circuit implementation of the dynamic gate-controlled circuit in the SBNMXIO.. Fig. 2.5 depicts the dynamic gate-controlled circuit of the I/O buffer in Fig. 2.4, where MP2 and MP3 are designed with the cross-coupled structure. If the gate voltage of MP2 (or MP3) is pulled down, this transistor is turned on and pulls up the gate voltage of the other transistor to VDDH (2xVDD) to turn it off. For example, if the voltage on node 5 is lower than “VDDH−|Vtp|” and the voltage on node 6 is VDDH, MN2 is turned on to keep the node 5 at VDD. Capacitors C1 and C2 are used to couple the signals from nodes 3 and 4 to nodes 5 and 6, respectively. The voltages across these capacitors are always VDD, because the voltage levels on the top plate and bottom plate of capacitors C1 and C2 are either VDD and 0V or 2xVDD and VDD. With these capacitors, when node 3 converts the voltage level from VDD to 0V, the voltage on node 5 is pulled down to VDD and then the voltage level on node 6 is pulled up to 2xVDD by transistor MP3. On the contrary, when the voltage level on node 4 is converted from VDD to 0V, the voltage on node 6 is pulled down to VDD, and that on node 5 is pulled up to 2xVDD by MP2. Initially, the voltages on nodes 3, 4, 5, and 6 could be unknown. If the voltages on nodes 5 and 6 are 2xVDD and VDD, and the voltages on nodes 3 and 4 are 0V and VDD, the voltages across capacitors C1 and C2 are 2xVDD and 0V, respectively, instead of both VDD. In order to overcome this -21-.

(38) problem, diode strings DS1 and DS2 are added. The turn-on voltages of the diode strings are designed to a little higher than VDD by using multiple diodes in stacked configuration. In order to prevent the leakage current path to the grounded p-type substrate, the diode-connected MOSFET or poly diode [24] is suggested. With these diode strings, if the voltage on node 3 is at 0V and that on node 4 is at VDD initially, the voltage on node 5 is clamped at the turn-on voltage (~VDD) of DS1. Therefore, MP3 is turned on to pull up the voltage on node 6 to 2xVDD. Thus, the voltages across capacitors C1 and C2 are both VDD. In this mixed-voltage I/O buffer, the bulk of the blocking NMOS MNS1 can be coupled to 0V (GND) without any gate-oxide reliability problem, even if the gate voltage of MNS1 may be as high as VDDH (2xVDD). The reason is that this blocking NMOS MNS1 is always turned on and the voltage across the gate oxide of MNS1 is from the gate to the conducting channel, but not from the gate to its bulk. The gate oxides of all NMOS devices in the dynamic gate-controlled circuit are also safe because these NMOS devices are turned on when their gates are pulled up to VDDH.. 2.2.2 Hot-Carrier Issues in SBNMXIO There is no reliability issue for this mixed-voltage I/O buffer proposed in [18] in the steady states of receive mode and transmit mode. However, when the mixed-voltage I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the I/O PAD originally has an initial voltage of 2xVDD before being pulled down. At this transition moment, the transistor MN0 is turned on by PD signal from pre-driver, and the transistor MNS1 is subsequently switched on when its source is pulled down by the MN0. Since the original 2xVDD voltage at I/O PAD is not pulled down immediately, the drain-source voltage of MNS1 would be larger than the normal supply voltage (VDD) during this transition, which results in the -22-.

(39) hot-carrier degradation on the transistor MNS1. With consideration of hot-carrier reliability for long-time reliable applications in microelectronic products, the 2xVDD I/O buffer designed with single blocking NMOS device in Fig. 2.4 with only 1xVDD devices is somewhat weak to reliably receive the 2xVDD-tolerant input signals in a given CMOS technology.. -23-.

(40) Chapter 3 Reliability Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Effect. 3.1 INTRODUCTION. Since the hot-carrier degradation threats the lifetime of ICs more seriously with newer CMOS generations, the mixed-voltage I/O buffers must be designed not only with consideration of gate-oxide reliability but also with consideration of hot-carrier effect. A 2xVDD-tolerant I/O buffer fabricated in 0.25-μm CMOS process was reported in [14]. This 2xVDD-tolerant I/O buffer uses double-cascode structure to overcome hot-carrier degradation although it consumes larger silicon area and propagation delay. In this chapter, two robust mixed-voltage I/O buffers based on the prior designs, GTCMXIO and SBNMXIO, mentioned in chapter two have been proposed. The reliable designs of mixed-voltage I/O buffers do not suffer gate-oxide degradations and hot-carrier degradations in both transmit mode and receive mode and the transitions.. 3.2 2XVDD-TOLERANT I/O BUFFER WITH DOUBLE-CASCODE STRUCTURE [14], [25] Fig. 3.1 shows a circuit using three-stacked (double-cascode) transistors to suppress hot-carrier degradation for the 2xVDD-tolerant I/O buffer [14], [25]. The transistors MPT0 and MPT1 comprise a tracking circuit for gate terminal of transistor MN2. The corresponding voltages of the 2xVDD-tolerant I/O buffer in two operating modes -24-.

(41) (transmit and receive modes) are list in Table 3.1. When the I/O buffer receives 2xVDD input signal, the gate terminal of transistor MN2 is biased at 2xVDD through transistor MPT0. Consequently, the source terminal is biased at “2xVDD-ΔV” due to the diode-connected MN2. On the contrary, the gate terminal of transistor MN2 is biased at VDD through transistor MPT1 if a 0-V signal is received or transmitted at I/O PAD. When the I/O buffer transmits VDD output signal to I/O PAD, the gate terminal of transistor MN2 is biased at ~VDD due to weakly turn-on transistors MPT0 and MPT1. Therefore, this 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors suffers neither gate-oxide degradation nor hot-carrier effect in both transmit and receive modes. As the I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal is biased at “2xVDD-ΔV” initially. In the meanwhile, the source terminal of MN0 is pulled down to ~0.5V by the MN1 in a 0.18-μm technology. The ΔV can be controlled such that all the drain-source voltages of MN0, MN1 and MN2 are below maximum operating voltage, Vdd,nom in a give COMS process. Thus, this 2xVDD-tolerant I/O buffer proposed in [14] can successfully solve the hot-carried degradation during the transition from receiving 2xVDD input signal to transmitting 0-V output signal. According to logic transistor sizing, each of the stacked transistors in Fig. 3.1 is 1.5 times larger in device size than that of the two-stacked transistors in Fig. 1.3 for equal driving capacity. As a result, the 2xVDD-tolerant I/O buffer with three-stacked transistors can solve the hot-carrier degradation with the extra penalty of increased silicon area and longer propagation delay. The circuit technique using three-stacked transistors is applied into the mixed-voltage I/O buffer in Fig. 3.2 as a comparison with new proposed circuit in this these. The mixed-voltage I/O buffer using three-stacked transistors is shown in Fig. 3.2 and denoted as TSTMXIO. Note that the gate terminals of the MN5 and MN6 are floating when the I/O buffer is transmitting -25-.

(42) VDD output signal.. Fig. 3.1 The brief schematic of 2xVDD-tolerant I/O buffer with three-stacked transistors to overcome hot-carrier issue.. Table 3.1 The operations of the 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors. Operating Modes. Signals at I/O PAD. PD. Vg of MN2. Receive. Low (0V). 0V. VDD. Receive. High (2xVDD). 0V. 2xVDD. Transmit. Low (0V). VDD. VDD. Transmit. High (VDD). 0V. ~VDD. -26-.

(43) Fig. 3.2 The mixed-voltage I/O buffer using three-stacked NMOS transistors (TSTMXIO).. 3.3 NEW DESIGN I:MIXED-VOLTAGE I/O BUFFER WITH NEW PROPOSED HOT-CARRIER-PREVENTED CIRCUIT 3.3.1 Design Concept A new hot-carrier-prevented circuit t in 2xVDD-tolerant I/O buffer with only two-stacked transistors is proposed in Fig. 3.3. The gate-controlled signal on transistor MN1 is a delay version of PD signal from the pre-driver. The tracking circuit controlled by OE signal generates control signal VCTRL to control switch SW0 During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the switch SW0 will be turned on by the control signal VCTRL to pull down I/O PAD to VDD. The delay should be long enough to have I/O PAD pulled down to VDD before the MN1 is switched on. Thus, the drain-source voltage of MN0 during such transition is not larger than its maximum normal operation voltage range (VDD) in the given CMOS technology. Note that this delay somewhat results in increasing delay during the transition from receiving 2xVDD input signal to transmitting 0-V -27-.

(44) output signal, but has no effect in the steady states of transmit and receive modes. Hence, the 2xVDD-tolerant I/O buffer with the new proposed hot-carrier-prevented circuit in Fig. 3.3 does not suffer the hot-carrier degradation. The switch SW0 must be kept off in all states except the high-to-low transition, so that this 2xVDD-tolerant I/O buffer can be operated correctly in both receive mode and transmit mode.. Fig. 3.3 The new design concept to overcome the hot-carrier issue in the 2xVDD-tolerant I/O buffer with only two-stacked transistors.. Fig. 3.4 The implementation of the new proposed hot-carrier-prevented circuit for 2xVDD-tolerant I/O buffer with two-stacked transistors. -28-.

(45) The desired delay time Δt can be estimated as following equation:. ΔQ = CL ΔV = I SW 0 Δt. (3 - 1). The CL is the output loading, ΔV is “VDDH-VDD”, and ISW0 is the driving current of switch SW0.. 3.3.2 Circuit Implementation Fig.. 3.4. depicts. the. circuit. implementation. of. the. new. proposed. hot-carrier-prevented circuit. Note that the input circuit has been omitted for convenience. The delay cell can be implemented simply by inverter chain. Besides, a small capacitor can be inserted into the output of the inverter chain to meet the desired delay time. The switch SW0 in Fig. 3.3 is realized by the PMOS transistor MP0 with a tracking circuit which is composed of transistors MP1, MP2, MN2 and a level shifter. The level shifter in tracking circuit shifts a voltage level of 0/VDD to VDD/2xVDD and can be implemented by using the circuit in Fig. 2.5 [18]. The tracking circuit makes the VCTRL turn off the MP0 in receive and transmit modes, but turn it on in the transition (from receiving 2xVDD input signal to transmitting 0-V output signal).. Table 3.2 The operations of the proposed hot-carrier-prevented circuit in 2xVDD-tolerant I/O buffer.. Operating Modes. Signals at I/O PAD. PD. VCTRL. Receive. Low (0V). 0V. VDD. Receive. High (2xVDD). 0V. 2xVDD. Transmit. Low (0V). VDD. VDD. Transmit. High (VDD). 0V. VDD. -29-.

(46) The corresponding voltages in two operating modes (transmit and receive modes) of the proposed hot-carrier-prevented circuit are list in Table 3.2. The detailed operations of this hot-carrier-prevented circuit are described in the following. When the mixed-voltage I/O buffer is in the receive mode, the output enable signal, OE, is set to 0V, and PU and PD signals are VDD and 0V, respectively. The transistor MP1 is switched on to set VCTRL to 2xVDD thus there is no leakage path to VDD through transistor MP0 when receiving 2xVDD input signals. The transistor MP2 is switched on to set VCTRL to VDD when receiving 0-V input signals. As the 2xVDD-tolerant I/O buffer is operating in the transmit mode (OE=VDD), the gate voltage of MN2 will be pulled up to 2xVDD by the level shifter. Then, the transistor MP0 is switched off by setting VCTRL to VDD. As a result, the switch MP0 is turned off in both the steady-state receive mode and transmit mode and has no effect on the correct operations. In steady states, there is neither gate-oxide degradation nor hot-carrier degradation in this 2xVDD-tolerant I/O buffer. When the 2xVDD-tolerant I/O buffer has the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the gate terminal of MN1 originally stays at 0V while the PD signal is changing from 0V to VDD by the pre-driver. In the meanwhile, the VCTRL is set to VDD by switching on the MN2, and consequently the MP0 is turned on to discharge the initial voltage of 2xVDD at the I/O PAD. After hundreds of picoseconds, the voltage at I/O PAD has been pulled down to about VDD, and the gate voltage of MN1 increases to VDD after the delay induced by the inverter chain. Therefore, the drain-source voltage of MN0 can be kept within the maximum normal operating voltage (Vdd,nom) range during the transition, that resulting in no hot-carrier degradation.. -30-.

(47) 3.3.3 Whole 2xVDD-Tolerant I/O Buffer With Hot-Carrier-Prevented Circuit As mentioned in chapter two, the 2xVDD-tolerant I/O buffer shown in Fig. 2.3 suffers hot-carrier degradation under the I/O signal transitions. During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the transistor MN0 suffers the hot-carrier degradation. The hot-carrier degradation will also occur on MN3 device in this traditional 2xVDD-tolerant I/O buffer during this transition. The transistors MN2 and MP2 also suffer hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal, since the gate terminal of transistor MP0 is initially kept at 2xVDD but the PU signal has been pull down to 0V by the pre-driver to turn on transistor MP0. In Fig. 3.5, the mixed-voltage I/O buffer with three hot-carrier-prevented circuits is proposed to solve the hot-carrier reliability issues on MN0, MN3, MN2, and MP2 in the 2xVDD-tolerant I/O buffer shown in Fig. 2.3. This new mixed-voltage I/O buffer with hot-carrier-prevented circuit is so called HCPMXIO in this thesis. The corresponding hot-carrier-prevented circuits in HCPMXIO are shown in Fig. 3.6. Note that all the bulks of PMOS transistors in hot-carrier-prevented circuits are connected to the self-biased n-well (nwell) marked in Fig. 3.5 to avoid leakage paths. The delay added in the gate terminal of MN1 shown in Fig. 3.3 has been changed to the output enable signal. As a result, the gate-controlled signals of MN1 and MN4 and PU signal are the delay versions of that in the original I/O buffer shown in Fig. 2.3.. -31-.

(48) Fig. 3.5 The new mixed-voltage I/O buffer with hot-carrier-prevented circuits (HCPMXIO).. (a). (b). (c) Fig. 3.6 The corresponding hot-carrier-prevented circuits in HCPMXIO. (a) The hot-carrier-prevented circuit for the MN0. (b) The hot-carrier-prevented circuit for the MN3. (c) The hot-carrier-prevented circuit for the MN2 and MP2. -32-.

(49) 3.3.4 Simulation Results The new proposed 2xVDD-tolerant I/O buffer with the hot-carrier-prevented circuits (HCPMXIO) shown in Fig. 3.5 is designed to meet the PCI-X 2.0 applications in a given 0.18-μm CMOS process, thus the HCPMXIO transmits 0V-to-1.5V output signals and receives 0V-to-3.3V input signals. Besides, the HCPMXIO has an operating speed up to 266 MHz. It is difficult to observe the long term behavior of hot-carrier effect in mixed-voltage I/O buffers unless the saturation currents or turn-on resistances are measured under overstress conditions for a long time. Therefore, the hot-carrier effect is verified by SPICE simulation in a 0.18-μm CMOS process for convenience. For measuring consideration, a load capacitance of 10 pF is added in the outputs of mixed-voltage I/O buffer shown in Fig. 3.7. In this thesis, all the mixed-voltage I/O buffers are simulated with a temperature of 85°C at TT corner, which can result in close results to actual conditions.. Fig. 3.7 The simulation environment.. Fig. 3.8 shows the simulation waveforms of the HCPMXIO in receive mode to receive the input signal of 0-to-3.3V with a frequency of 266 MHz. The. -33-.

(50) gate-controlled signals VCTRL1, VCTRL2 and VCTRL3 are biased at 3.3V in receiving 3.3-V input signal, and they are biased at 1.5V in receiving 0-V input signal. In Fig. 3.9, the simulation waveforms of the I/O circuit in transmit mode to transmit a signal of 0-to-1.5V with a frequency of 266 MHz are shown. All the gate-controlled control signals are biased at 1.5V to turn off transistors MP7, MP10 and MP13 in transmit mode. As shown in Fig. 3.8 and Fig. 3.9, the proposed mixed-voltage I/O circuit with hot-carrier-prevented circuits can be operated correctly in both receive mode and transmit mode.. Fig. 3.8 Simulation waveforms of the HCPMXIO in receiving mode with 3.3-V 266-MHz input signals.. -34-.