Hot-Carrier Issues in SBNMXIO

There is no reliability issue for this mixed-voltage I/O buffer proposed in [18] in the steady states of receive mode and transmit mode. However, when the mixed-voltage I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the I/O PAD originally has an initial voltage of 2xVDD before being pulled down. At this transition moment, the transistor MN0 is turned on by PD signal from pre-driver, and the transistor MNS1 is subsequently switched on when its source is pulled down by the MN0. Since the original 2xVDD voltage at I/O PAD is not pulled down immediately, the drain-source voltage of MNS1 would be larger than the normal supply voltage (VDD) during this transition, which results in the

hot-carrier degradation on the transistor MNS1. With consideration of hot-carrier reliability for long-time reliable applications in microelectronic products, the 2xVDD I/O buffer designed with single blocking NMOS device in Fig. 2.4 with only 1xVDD devices is somewhat weak to reliably receive the 2xVDD-tolerant input signals in a given CMOS technology.

Chapter 3

Reliability Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Effect

3.1 INTRODUCTION

Since the hot-carrier degradation threats the lifetime of ICs more seriously with newer CMOS generations, the mixed-voltage I/O buffers must be designed not only with consideration of gate-oxide reliability but also with consideration of hot-carrier effect. A 2xVDD-tolerant I/O buffer fabricated in 0.25-μm CMOS process was reported in [14]. This 2xVDD-tolerant I/O buffer uses double-cascode structure to overcome hot-carrier degradation although it consumes larger silicon area and propagation delay. In this chapter, two robust mixed-voltage I/O buffers based on the prior designs, GTCMXIO and SBNMXIO, mentioned in chapter two have been proposed. The reliable designs of mixed-voltage I/O buffers do not suffer gate-oxide degradations and hot-carrier degradations in both transmit mode and receive mode and the transitions.

3.2 2XVDD-TOLERANT I/OBUFFER WITH DOUBLE-CASCODE

STRUCTURE [14],[25]

Fig. 3.1 shows a circuit using three-stacked (double-cascode) transistors to suppress hot-carrier degradation for the 2xVDD-tolerant I/O buffer [14], [25]. The transistors MPT0 and MPT1 comprise a tracking circuit for gate terminal of transistor MN2. The corresponding voltages of the 2xVDD-tolerant I/O buffer in two operating modes

(transmit and receive modes) are list in Table 3.1. When the I/O buffer receives 2xVDD input signal, the gate terminal of transistor MN2 is biased at 2xVDD through transistor MPT0. Consequently, the source terminal is biased at “2xVDD-ΔV” due to the diode-connected MN2. On the contrary, the gate terminal of transistor MN2 is biased at VDD through transistor MPT1 if a 0-V signal is received or transmitted at I/O PAD. When the I/O buffer transmits VDD output signal to I/O PAD, the gate terminal of transistor MN2 is biased at ~VDD due to weakly turn-on transistors MPT0 and MPT1. Therefore, this 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors suffers neither gate-oxide degradation nor hot-carrier effect in both transmit and receive modes. As the I/O buffer has a transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal is biased at

“2xVDD-ΔV” initially. In the meanwhile, the source terminal of MN0 is pulled down to ~0.5V by the MN1 in a 0.18-μm technology. The ΔV can be controlled such that all the drain-source voltages of MN0, MN1 and MN2 are below maximum operating voltage, Vdd,nom in a give COMS process. Thus, this 2xVDD-tolerant I/O buffer proposed in [14] can successfully solve the hot-carried degradation during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

According to logic transistor sizing, each of the stacked transistors in Fig. 3.1 is 1.5 times larger in device size than that of the two-stacked transistors in Fig. 1.3 for equal driving capacity. As a result, the 2xVDD-tolerant I/O buffer with three-stacked transistors can solve the hot-carrier degradation with the extra penalty of increased silicon area and longer propagation delay. The circuit technique using three-stacked transistors is applied into the mixed-voltage I/O buffer in Fig. 3.2 as a comparison with new proposed circuit in this these. The mixed-voltage I/O buffer using three-stacked transistors is shown in Fig. 3.2 and denoted as TSTMXIO. Note that the gate terminals of the MN5 and MN6 are floating when the I/O buffer is transmitting

VDD output signal.

Fig. 3.1 The brief schematic of 2xVDD-tolerant I/O buffer with three-stacked transistors to overcome hot-carrier issue.

Table 3.1

The operations of the 2xVDD-tolerant I/O buffer using three-stacked NMOS transistors.

Operating Modes Signals at I/O PAD PD Vg of MN2

Receive Low (0V) 0V VDD

Receive High (2xVDD) 0V 2xVDD

Transmit Low (0V) VDD VDD

Transmit High (VDD) 0V ~VDD

Fig. 3.2 The mixed-voltage I/O buffer using three-stacked NMOS transistors (TSTMXIO).

3.3 NEW DESIGN I:MIXED-VOLTAGE I/OBUFFER WITH NEW

PROPOSED HOT-CARRIER-PREVENTED CIRCUIT

3.3.1 Design Concept

A new hot-carrier-prevented circuit t in 2xVDD-tolerant I/O buffer with only two-stacked transistors is proposed in Fig. 3.3. The gate-controlled signal on transistor MN1 is a delay version of PD signal from the pre-driver. The tracking circuit controlled by OE signal generates control signal VCTRL to control switch SW0 During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the switch SW0 will be turned on by the control signal VCTRL to pull down I/O PAD to VDD. The delay should be long enough to have I/O PAD pulled down to VDD before the MN1 is switched on. Thus, the drain-source voltage of MN0 during such transition is not larger than its maximum normal operation voltage range (VDD) in the given CMOS technology. Note that this delay somewhat results in increasing delay during the transition from receiving 2xVDD input signal to transmitting 0-V

output signal, but has no effect in the steady states of transmit and receive modes.

Hence, the 2xVDD-tolerant I/O buffer with the new proposed hot-carrier-prevented circuit in Fig. 3.3 does not suffer the hot-carrier degradation. The switch SW0 must be kept off in all states except the high-to-low transition, so that this 2xVDD-tolerant I/O buffer can be operated correctly in both receive mode and transmit mode.

Fig. 3.3 The new design concept to overcome the hot-carrier issue in the 2xVDD-tolerant I/O buffer with only two-stacked transistors.

Fig. 3.4 The implementation of the new proposed hot-carrier-prevented circuit for 2xVDD-tolerant I/O buffer with two-stacked transistors.

The desired delay time Δt can be estimated as following equation:

Fig. 3.4 depicts the circuit implementation of the new proposed hot-carrier-prevented circuit. Note that the input circuit has been omitted for convenience. The delay cell can be implemented simply by inverter chain. Besides, a small capacitor can be inserted into the output of the inverter chain to meet the desired delay time. The switch SW0 in Fig. 3.3 is realized by the PMOS transistor MP0 with a tracking circuit which is composed of transistors MP1, MP2, MN2 and a level shifter.

The level shifter in tracking circuit shifts a voltage level of 0/VDD to VDD/2xVDD and can be implemented by using the circuit in Fig. 2.5 [18]. The tracking circuit makes the VCTRL turn off the MP0 in receive and transmit modes, but turn it on in the transition (from receiving 2xVDD input signal to transmitting 0-V output signal).

Table 3.2

The operations of the proposed hot-carrier-prevented circuit in 2xVDD-tolerant I/O buffer.

Operating Modes Signals at I/O

PAD PD VCTRL

Receive Low (0V) 0V VDD

Receive High (2xVDD) 0V 2xVDD

Transmit Low (0V) VDD VDD

Transmit High (VDD) 0V VDD

The corresponding voltages in two operating modes (transmit and receive modes) of the proposed hot-carrier-prevented circuit are list in Table 3.2. The detailed operations of this hot-carrier-prevented circuit are described in the following. When the mixed-voltage I/O buffer is in the receive mode, the output enable signal, OE, is set to 0V, and PU and PD signals are VDD and 0V, respectively. The transistor MP1 is switched on to set VCTRL to 2xVDD thus there is no leakage path to VDD through transistor MP0 when receiving 2xVDD input signals. The transistor MP2 is switched on to set VCTRL to VDD when receiving 0-V input signals. As the 2xVDD-tolerant I/O buffer is operating in the transmit mode (OE=VDD), the gate voltage of MN2 will be pulled up to 2xVDD by the level shifter. Then, the transistor MP0 is switched off by setting VCTRL to VDD. As a result, the switch MP0 is turned off in both the steady-state receive mode and transmit mode and has no effect on the correct operations. In steady states, there is neither gate-oxide degradation nor hot-carrier degradation in this 2xVDD-tolerant I/O buffer.

When the 2xVDD-tolerant I/O buffer has the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the gate terminal of MN1 originally stays at 0V while the PD signal is changing from 0V to VDD by the pre-driver. In the meanwhile, the VCTRL is set to VDD by switching on the MN2, and consequently the MP0 is turned on to discharge the initial voltage of 2xVDD at the I/O PAD. After hundreds of picoseconds, the voltage at I/O PAD has been pulled down to about VDD, and the gate voltage of MN1 increases to VDD after the delay induced by the inverter chain. Therefore, the drain-source voltage of MN0 can be kept within the maximum normal operating voltage (Vdd,nom) range during the transition, that resulting in no hot-carrier degradation.

3.3.3 Whole 2xVDD-Tolerant I/O Buffer With Hot-Carrier-Prevented Circuit

As mentioned in chapter two, the 2xVDD-tolerant I/O buffer shown in Fig. 2.3 suffers hot-carrier degradation under the I/O signal transitions. During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the transistor MN0 suffers the hot-carrier degradation. The hot-carrier degradation will also occur on MN3 device in this traditional 2xVDD-tolerant I/O buffer during this transition. The transistors MN2 and MP2 also suffer hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal, since the gate terminal of transistor MP0 is initially kept at 2xVDD but the PU signal has been pull down to 0V by the pre-driver to turn on transistor MP0. In Fig. 3.5, the mixed-voltage I/O buffer with three hot-carrier-prevented circuits is proposed to solve the hot-carrier reliability issues on MN0, MN3, MN2, and MP2 in the 2xVDD-tolerant I/O buffer shown in Fig. 2.3. This new mixed-voltage I/O buffer with hot-carrier-prevented circuit is so called HCPMXIO in this thesis. The corresponding hot-carrier-prevented circuits in HCPMXIO are shown in Fig. 3.6. Note that all the bulks of PMOS transistors in hot-carrier-prevented circuits are connected to the self-biased n-well (nwell) marked in Fig. 3.5 to avoid leakage paths. The delay added in the gate terminal of MN1 shown in Fig. 3.3 has been changed to the output enable signal. As a result, the gate-controlled signals of MN1 and MN4 and PU signal are the delay versions of that in the original I/O buffer shown in Fig. 2.3.

Fig. 3.5 The new mixed-voltage I/O buffer with hot-carrier-prevented circuits (HCPMXIO).

(a)

(b)

(c)

Fig. 3.6 The corresponding hot-carrier-prevented circuits in HCPMXIO. (a) The hot-carrier-prevented circuit for the MN0. (b) The hot-carrier-prevented circuit for the MN3. (c) The hot-carrier-prevented circuit for the MN2 and MP2.

3.3.4 Simulation Results

The new proposed 2xVDD-tolerant I/O buffer with the hot-carrier-prevented circuits (HCPMXIO) shown in Fig. 3.5 is designed to meet the PCI-X 2.0 applications in a given 0.18-μm CMOS process, thus the HCPMXIO transmits 0V-to-1.5V output signals and receives 0V-to-3.3V input signals. Besides, the HCPMXIO has an operating speed up to 266 MHz. It is difficult to observe the long term behavior of hot-carrier effect in mixed-voltage I/O buffers unless the saturation currents or turn-on resistances are measured under overstress conditions for a long time. Therefore, the hot-carrier effect is verified by SPICE simulation in a 0.18-μm CMOS process for convenience. For measuring consideration, a load capacitance of 10 pF is added in the outputs of mixed-voltage I/O buffer shown in Fig. 3.7. In this thesis, all the mixed-voltage I/O buffers are simulated with a temperature of 85°C at TT corner, which can result in close results to actual conditions.

Fig. 3.7 The simulation environment.

Fig. 3.8 shows the simulation waveforms of the HCPMXIO in receive mode to receive the input signal of 0-to-3.3V with a frequency of 266 MHz. The

gate-controlled signals VCTRL1, VCTRL2 and VCTRL3 are biased at 3.3V in receiving 3.3-V input signal, and they are biased at 1.5V in receiving 0-V input signal. In Fig.

3.9, the simulation waveforms of the I/O circuit in transmit mode to transmit a signal of 0-to-1.5V with a frequency of 266 MHz are shown. All the gate-controlled control signals are biased at 1.5V to turn off transistors MP7, MP10 and MP13 in transmit mode. As shown in Fig. 3.8 and Fig. 3.9, the proposed mixed-voltage I/O circuit with hot-carrier-prevented circuits can be operated correctly in both receive mode and transmit mode.

Fig. 3.8 Simulation waveforms of the HCPMXIO in receiving mode with 3.3-V 266-MHz input signals.

Fig. 3.9 Simulation waveforms of the HCPMXIO in transmitting mode with 266-MHz output signals.

The drain-source voltages of the transistors MN0, MN3, MN2 and MP2 in HCPMXIO are compared to that in GTCMXIO (Fig. 2.3) during the transition from receiving 3.3-V input signal to transmitting 0-V or 1.5-V output signal. The drain-source voltages of MN0 and MN3 during the transition from receiving 3.3-V input signal to transmitting 0-V output signal are shown in Fig. 3.10. In Fig. 3.10 (a), the peak of drain-source voltage on MN0 in this work (HCPMXIO) is only ~1.8V, but that of the original design (GTCMXIO) is as high as 2.8V. As shown in Fig. 3.10 (b), the peak of drain-source voltage on MN3 is 1.7V in this work, but that in the GTCMXIO is 2.7V. Besides, the drain-source voltages of the transistor MN2 (or MP2) in this work and the original design during the transient from receiving 3.3-V input signal to transmitting 1.5-V output signal are compared in Fig. 3.11. The drain-source voltage across the transistor MN2 (or MP2) is lower than the maximum normal

operating voltage (1.8V) in the HCPMXIO. However, the drain-source voltage across the transistor MN2 (or MP2) in the original design is still as high as ~2.8V. Therefore, the hot-carrier effect has been suppressed by the proposed hot-carrier-prevented circuits in this work.

Fig. 3.10 The drain-source voltages of the MN0 and MN3 during the transition from receiving 3.3V input signal to transmitting 0-V output signal. (a) The drain-source voltage of the MN0. (b) The drain-source voltage of the MN3.

GTCMXIO (prior design I) 2.8V

Vds of MN2/MP2

Voltage (V)

HCPMXIO (new design I) 1.6V

Fig. 3.11 The drain-source voltages of MN2 during the transition from receiving 3.3-V input signal to transmitting 1.5-V output signal.

Moreover, a delay of 1.166ns is required in GTCMXIO when the 2xVDD-tolerant I/O buffer switches from receive mode to transmit mode. A corresponding delay of 1.692ns is required in the HCPMXIO under the same switching condition. It should be noted that the additional delay in the HCPMXIO would result in undesired glitch at I/O PAD which may cause logic error in the following circuit if the additional delay resulted from inverter chain is too large. As shown in Fig. 3.12, the glitch gets serious with increasing the delay of high level at OE signal. Therefore, the delay in gate-controlled signal of MN1 in Fig. 3.4 should be carefully controlled.

Fig. 3.12 Simulation waveforms of the HCPMXIO in transition with increasing the delay of high level at OE signal.

3.3.5 Summary for Simulation Results

The comparisons of new proposed mixed-voltage I/O buffer with prior designs are list in Table 3.3. The parameters of mixed-voltage I/O buffers are simulated with an operating speed of 266 MHz at TT corner and 85°C. Several parameters are defined in this thesis as follows:

z IOH: The source current of mixed-voltage I/O buffer when the voltage at I/O pad is pulled up to 0.9xVDD.

z IOL: The sink current of mixed-voltage I/O buffer when the voltage at I/O pad is pulled down to 0.1xVDD.

z Tpr: The propagation delay signal with a voltage swing of 3.3 V received from I/O PAD to Din.

z Tpt: The propagation delay signal transmitted from Dout to I/O PAD in the mixed-voltage I/O buffer.

z Tdrt: The delay time for the voltage at I/O PAD pulled down from 3.3V to 0V when the mixed-voltage I/O buffer has a transition from receiving 3.3V input signal to transmitting 0-V output signal.

Table 3.3

The simulation results of mixed-voltage I/O buffers with/without hot-carrier-prevented mechanisms.

Hot-Carrier Degradation Yes (387 ps) No No

Tdrt 1.166 ns 1.205 ns 1.692 ns

As shown in Table 3.3, the GCTMXIO suffers hot-carrier degradation in the transition from receiving 3.3-V input signal to transmitting 0-V output signal. The drain-source voltage of transistor are larger than the maximum operating voltage (Vdd,nom) for 387 ps in a given 0.18-μm CMOS process. The TSTMXIO and HCPMXIO with hot-carrier mechanisms solve the hot-carrier degradation successfully. The propagation delays and rise/fall time of TSTMXIO, however, are larger than that of HCPMXIO in this thesis due to three-stacked transistors.

3.4 NEW DESIGN II:MIXED-VOLTAGE I/OBUFFER WITH TWO

BLOCKING NMOSDEVIES AND DYNAMIC GATE-CONTROLLED CIRCUIT

3.4.1 Design Concept

As mentioned in chapter two, the SBNMXIO (Fig. 2.4) suffers hot-carried degradation during the transition from receiving 2xVDD input signal to transmitting 0-V output signal. A new mixed-voltage I/O buffer with two blocking NMOS devices (called TBNMXIO) is proposed in Fig. 3.13 to tolerate 2xVDD I/O signals. Fig. 3.13 depicts the new proposed 2xVDD-tolerant I/O buffer with two blocking NMOS devices and dynamic gate-controlled circuit, where VDDH represents a voltage of 2xVDD and can be implemented by on-chip charge pump with only 1xVDD devices [26] or other high-voltage generators. This 2xVDD-tolerant I/O buffer is designed to receive 0V-to-2xVDD input signals and transmit 0V-to-VDD output signals. The 0V-to-2xVDD input signals will be transferred into core circuits with a voltage swing of only VDD. The blocking NMOS devices, MNS1 and MNS2, in Fig. 3.13 are used to protect the 2xVDD-tolerant I/O buffer from gate-oxide and hot-carrier reliability issues. The corresponding node voltages in the dynamic gate-controlled circuit during the two operating modes (transmit and receive) are list in Table 3.4.

Fig. 3.13 The new proposed 2xVDD-tolerant I/O buffer with two blocking NMOS devices and dynamic gate-controlled circuit to solve the hot-carrier reliability issue (TBNMXIO).

Table 3.4

The operations of the dynamic gate-controlled circuit in TBNMXIO

Operating Modes Signals at I/O PAD Vg of MNS1 (Vgc1)

Vg of MNS2 (Vgc2)

Receive Low (0 V) VDD VDD

Receive High (2xVDD) VDD High (2xVDD)

Transmit Low (0 V) VDD VDD

Transmit High (VDD) 2xVDD 2xVDD

When the 2xVDD-tolerant I/O buffer is operating in the receive mode (OE=0), the gate-controlled signal (Vgc2) on MNS2 will be changed corresponding to the voltage at I/O PAD. In the meanwhile, the Vgc1 on MNS1 is always biased at VDD by gate-controlled circuit. The Vgc2 is biased at VDD to receive 0-V input signal, but it will be biased at 2xVDD to receive 2xVDD input signal. Besides, the output transistors MP0 and MN0 are turned off by pre-driver in the receive mode. If an input signal of logic low (0V) is received at I/O PAD, nodes 7 and 8 will be discharged to 0