D ISCUSSION AND S UMMARY

4.7.1 Discussion

In this chapter, the measured ground bounce effects are not reduced greatly by the slew-rate control. For experimental measurement of ground bounce effect, seven or eight I/O buffers must be switched on simultaneously resulting in large instantaneous current [29]. Fig. 4.32 shows the connecting diagram for measuring ground bounce. Moreover, a test circuit for measuring ground bounce should be developed.

In this thesis, tapper buffers were used to drive Din pads in this thesis as the mixed-voltage I/O buffers are operated in receive mode. As a result, the switching current may be dominated by the tapper buffer such that the difference of switching currents induced by output transistors between the mixed-voltage I/O buffer with slew-rate control and that without slew-rate control is indistinct. A better method to measure the receiving operation is shown in Fig. 4.33 where one I/O cell is connected as in receive mode and the other is connected as in transmit mode. Therefore, the silicon area and power consumption of one mixed-voltage I/O buffer will be reduced.

The ground bounce effect will not be affected by the tapper buffer, too. There is another way to eliminate the effect of tapper buffer on ground bounce. That is adding an enable pin (IE) to input buffer. As the mixed-voltage I/O buffer is operated in transmit mode, the IE is set to 0V to disable input circuit. Therefore, the tapper buffer can drive Din pad successfully without affecting ground bounce in transmit mode at a cost of extra pad and silicon area.

Fig. 4.32 The measurement method of ground bounce effect where seven I/O cells switch simultaneously.

Fig. 4.33 The measurement setting for testing the receiving operations of mixed-voltage I/O buffer.

4.7.2 Summary

In this chapter, two new mixed-voltage I/O buffers with slew-rate control have been proposed with only thin-oxide devices. The reduction on ground bounce effects by slew-rate control has been verified in a 0.18-μm CMOS process. The TBNMXIO-SR has been fabricated in a 0.18-μm CMOS process. Several circuit techniques for further reducing ground bounce are summarized in this chapter.

Chapter 5

Conclusion and Future Works

5.1 CONCLUSION

A hot-carrier-prevented circuit with only-thin oxide devices which can successfully solve the hot-carrier degradation during the transitions was proposed in chapter 3. This circuit can be applied in the general 2xVDD-tolerant I/O buffer to solve hot-carrier degradation on devices without reducing the driving capacity. The whole mixed-voltage I/O buffer with hot-carrier-prevented circuits was designed in chapter 3 without suffering hot-carrier degradation in both steady states of receive mod and transmit mode and the transitions. Furthermore, a new 2xVDD-tolerant I/O buffer with two blocking NMOS devices and dynamic gate-controlled circuit was proposed without hot-carrier degradation in both steady states of receive mode and transmit mode and the transition from receiving 2xVDD input signal to transmitting 0-V output signal. Although the stacked number of output transistors in mixed-voltage I/O buffer was increased, the overall circuit design is less complex than the mixed-voltage I/O buffers with floating n-well bias circuit. Both proposed designs have been fabricated in a 0.18-μm 1P6M CMOS process and are suitable for the PCI-X 2.0 applications.

In chapter 4, two mixed-voltage I/O buffers based on the prior designs in chapter 3 with slew rate control were proposed. The slew-rate controls on mixed-voltage I/O buffers can effectively reduce the ground bounce effects without gate-oxide reliability problems and hot-carrier degradation issues. Several technique including distributed and weighted technique and separate power pad were discussed to further reduce

ground bounce. The mixed-voltage I/O buffer using two blocking NMOS devices and dynamic gate-controlled circuit with slew-rate control has been fabricated in a 0.18-μm 1P6M CMOS process.

5.2 FUTRUE WORKS

Since the proposed mixed-voltage I/O buffers in this thesis are designed with an operating speed of up to 266 MHz, the transmission line effect should be considered.

Thus transmission model should be added into simulation to have more accurate results. Besides, the circuit techniques for reducing short circuit current can be applied in the designs to further reduce the power consumption induced by short current. Also, the slew-rate control in mixed-voltage I/O buffer should be carefully designed without hot-carrier degradation during the transitions from receiving high input signal to transmitting low output signal. Finally, the measured methods for verifying the operations of mixed-voltage I/O buffer which have been mentioned in 4.7 should be used to have clear verifications.

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簡歷

VITA

姓 名：胡芳綾

學 歷：

台灣省立蘭陽女子高級中學 (86 年 9 月~89 年 6 月)

國立交通大學電機與控制工程學系 (89 年 9 月~93 年 6 月)

國立交通大學電子研究所碩士班 (93 年 6 月~95 年 6 月)

研究所修習課程：

類比積體電路I 吳介琮教授

類比積體電路II 吳介琮教授

數位積體電路 柯明道教授

有線傳輸通訊積體電路設計 陳巍仁教授

低功率與高速積體電路設計 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

計算機結構 黃俊達教授

顯示電子電路 戴亞翔教授

永久地址：宜蘭縣礁溪鄉礁溪路六段128 號

Email： fangling.ee93g@nctu.edu.tw fangling.ece89@nctu.edu.tw m9311593@alab.ee.nctu.edu.tw