Design Concept

Fig. 2.1 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit [7]-[8], [19]-[22]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig. 2.1 is used to prevent the leakage current path which is resulted from the incorrect conduction of the pull-up PMOS device when the input signal is higher than VDD. As the mixed-voltage I/O buffer is operating in the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device, MP0, exactly.

In the receive mode (tri-state input mode) with an input signal of 2xVDD, the gate-tracking circuit will charge the gate terminal of the MP0 to 2xVDD to turn off the MP0 completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the MP0 at VDD to turn off the MP0 completely, and to prevent the overstress on the

gate oxide of the MP0 when the 0-V input signal is received from I/O PAD. Moreover, the dynamic n-well bias circuit shown in Fig. 2.1 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device MP0. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at VDD so that the threshold voltage of the pull-up PMOS device isn’t increased due to the body effect. In the receive mode with an input signal of 2xVDD, the dynamic n-well bias circuit will charge the floating n-well to 2xVDD to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. On the other hand, the dynamic n-well bias circuit will bias the floating n-well at VDD when the input signal at the I/O pad is 0V.

Fig. 2.1 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.

As shown in Fig. 2.1, the extra transistors, MN2 and MP1, which are compared to Fig. 1.2, are added in the input circuit. The transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The

transistor MP1 is used to prevent unnecessary leakage current in the inverter INV1.

Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV1 will rise up to “VDD-Vth” when the input signal at the I/O pad is 2xVDD in the receive mode. The transistor MP1 will pull the input node of inverter INV1 up to VDD when the output node of inverter INV1 is pulled down to 0V. Therefore, the gate-oxide reliability problem of the input buffer can be solved. Moreover, the circuit implementation of pre-driver composed of a NAND gate and NOR gate is shown in Fig. 2.2. The operations of pre-driver are list in Table 2.1. When the output enable signal OE is 0V, the mixed-voltage I/O buffer is operated in receive mode. The pull-up signal (PU) and pull-down signal (PD) are set to VDD and 0V, respectively, to turn off pull-up device and pull-down devices. On the contrary, both PU and PD are set to VDD to turn off pull-up device and turn on pull-down devices, respectively, in transmitting 0-V output signal, and they are set to 0V to switch on pull-up device and switch off pull-down devices, respectively, in transmitting VDD output signal.

Fig. 2.2 The circuit implementation of pre-driver.

Table 2.1

Fig. 2.3 shows the mixed-voltage I/O buffer with the dynamic n-well bias circuit and gate-tracking circuit proposed in [10]. For clear illustration, this mixed-voltage I/O buffer is called GTCMXIO in this thesis. When the output control signal OE is at VDD (logic “1”), the mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad rises or falls according to signal Dout, which is controlled by the internal circuits of IC. The pull-down signal, PD, produced by pre-driver is directly connected to the gate terminal of the pull-down NMOS device, MN1. The pull-up signal, PU, is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit which is composed of NMOS transistors MN2-MN4 and PMOS transistors MP2, MP3 and MP5. The transistors MN2 and MP2 comprise a transmission gate. The transistor MN3 in Fig. 2.3 is used to protect the transistor MN4 from gate-oxide reliability problem. The dynamic n-well bias circuit is composed of transistors MP4 and MP6. If the mixed-voltage I/O buffer is operating in transmit mode (OE = VDD), the gate terminal of MP4 will be biased at 0V to bias the floating n-well at VDD by turning on the transistor MP4. At this time, the PU signal is fully transmitted to the gate terminal of the pull-up PMOS device MP0 through the