New Slew-Rate Control on Mixed-Voltage I/O Buffer

A robust mixed-voltage I/O buffer with modified slew-rate control is proposed in Fig. 4.12 and called HCPMXIO-SR. The hot-carrier-prevented circuits for transistors

MN0 and MN3 have been shown in Fig. 4.11 (b) and (c). The NMOS transistors MNSR6-MNSR8 are used to protect transistors MPSR2-MPSR4 from gate-oxide degradation and avoid leakage currents as the HCPMXIO-SR receives 2xVDD input signals. The gate-controlled signal of transistors MPSR6-MPSR8, PDH, is high-level version of pull down signal, PD, shifted by the level shifter. Furthermore, the transistor MNSR2 is used to protect transistor MNSR1 from gate oxide degradation and hot-carrier degradation as the mixed-voltage I/O buffer receives 2xVDD input signal. Since the transmission gates MNR1/MPR1 and MNR2/MPR2 are mainly used to propagate 0-V signal to turn on PMOS output transistors, MPD1-MPD3, one by one, the PMOS transistors MPR1 and MPR2 can be omitted and consequently only NMOS transistors are used as resistive elements. As a result, the resistive elements do not suffer gate-oxide degradation mentioned in the previous section. Similarly, the transistors MNR3 and MNR4 can be omitted. When the mixed-voltage I/O buffer receives 0-V input signal at I/O PAD, the PD signal is set to 0V and consequently PDH signal is set to VDD. At this time, the gate-controlled signals of transistors MPD1-MPD3, VPC1-VPC3, are biased at “VDD-Vth” due to weakly turned-on transistors MPSR6-8, thus results in subthreshold leakage currents on transistors MPD1-MPD3. To avoid this problem, the gate-controlled signals of transistors MPD1-MPD3 are pulled up to VDD through the transistors MP34-MP36 in Fig. 4.12 as 0-V input signal is received at I/O PAD. Note that the bulks of PMOS devices and NMOS devices in the new slew rate control are connected to VDD and GND, respectively. The bulks of transistors from MP31 to MP36 are connected to the n-well bias circuit (nwell).

The operations of this HCPMXIO-SR are list in Table 4.2. When the HCPMXIO-SR is operated in receive mode, the PUb and PDb signal are 0V and VDD, respectively, to turn off output driver. In the meanwhile, the PDH signal is set

to VDD by level shifter. The transistors MP31 and MP34 comprise the gate tracking circuit of transistor MPD1 as the I/O buffer is operating in receive mode. Similarly, transistors MP32/MP35 and MP33/MP36 are the gate-tracking circuit of transistor MPD2 and MPD3, respectively. As 2xVDD input signal is receive at I/O PAD, the VPC1, VPC2 and VPC3 are set to 2xVDD through transistors MP31, MP32 and MP33. On the contrary, the VPC1, VPC2 and VPC3 are set to VDD through transistors MP34, MP35 and MP36. As a result, the input signals can be received successfully without gate-oxide reliability problem and leakage currents. If the mixed-voltage I/O buffer is transmitting 0-V output signal, the PDb signal is set to 0V, and consequently transistor MPSR1 is turned on to propagate VDD signal to gate terminals of transistors MND1-MND3 through transistors MPR3 and MPR4. In the meanwhile, the PDH signal is set to 2xVDD, thus the VDD signals can be transmitted to the gate terminals of transistors MPD1-MPD3 through transistors MNSR6-MNSR8 successfully. As a result, transistors MPD1-MPD3 are quickly turned off. On the other hand, if VDD output signal is transmitted from Dout to I/O PAD, the PUb signal is pulled up to VDD to turn on transistor MNSR1. The 0-V signal consequently is propagated to VPC2 and VPC3 through transistors MNR1 and MNR2. The PMOS transistors MPD1, MPD2 and MPD3 are turned on one by one to pull up I/O PAD to VDD. In the same condition, the PDb signal is set to VDD to turn on transistors MNSR3-MNSR5, thus NMOS transistors MND1, MND2 and MND3 are quickly turned off. As the foregoing descriptions, this HCPMXIO-SR can be successfully operated in both receive mode and transmit mode without gate-oxide degradation and hot-carrier degradation. Furthermore, the mechanism of hot-carrier-prevented circuit in Fig. 3.4 can be applied in transistor MNSR2 to avoid hot-carrier degradation during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 4.12 The HCPMXIO with modified slew-rate control.

Table 4.2

The operations of the HCPMXIO-SR

Operating Modes

Signals at

I/O PAD PUb PDb PDH VPC1-VPC3 VNC1-VNC3

Receive Low (0V) 0V VDD VDD VDD 0V

Receive High

(2xVDD) 0V VDD VDD 2xVDD 0V

Transmit Low (0V) 0V 0V 2xVDD VDD VDD

Transmit High

(VDD) VDD VDD VDD 0V 0V

4.4.3 Simulation Results

This HCPMXIO with slew-rate control is designed to meet PCI-X 2.0 applications, thus VDD is 1.5V and VDDH is 3.3V. The HCPMXIO-SR has been verified in a 0.18-μm CMOS process by SPICE simulation. The simulation waveforms of the new HCPMXIO-SR with an operating speed of 266 MHz in transmit mode are shown in Fig. 4.13. When the I/O buffer transmits VDD output

signal to I/O PAD, the gate-controlled signals of MPD1-MPD3, VPC1, VPC2 and VPC3, are pulled to 0V one by one. In the meanwhile, the gate-controlled signals of MND1-MND3, VNC1, VNC2 and VNC3, are pulled down to 0V to turn off transistors MND1-MND3 quickly. On the contrary, when 0-V output signal is transmitted to I/O PAD, the VPC1, VPC2 and VPC3 are quickly pulled up to VDD to turn off transistors MPD1-MPD3. The VNC1, VNC2 and VNC3 are progressively pulled up to VDD to turn on transistors MND1-MND3. As a result, the HCPMXIO-SR successfully transmits data with a reduced slew rate.

Fig. 4.13 Simulation waveforms of the HCPMXIO-SR operating at 266 MHz when transmitting 0V-to-1.5V output signals to I/O PAD.

The simulation results of the HCPMXIO-SR and HCPMXIO, which has no slew-rate control, are summarized in Table 4.3. The propagation delay and rise/fall time of this HCPMXIO-SR are larger than those of the HCPMXIO. Also, the driving currents of HCPMXIO-SR are smaller than those of the HCPMXIO due to the

slew-rate control. The power consumption of this HCPMXIO-SR is larger than that of HCPMXIO due to the slew-rate controlled circuit, which is more complex than the slew-rate control circuit in the TBNMXIO-SR.

The ground bounce effects on GND and VDD power lines are shown in Fig. 4.14 and Fig. 4.15, respectively, which are the comparisons between the HCPMXIO and HCPMXIO-SR. As shown in Fig. 4.14 and Fig. 4.15, the ground bounce effects are reduced by the HCPMXIO-SR.

Table 4.3

The simulation results of the HCPMXIO and HCPMXIO-SR.

Parameters HCPMXIO

Power Consumption 28 μW/MHz 29 μW/MHz

Trise 702 ps 958 ps

Tfall 708 ps 938 ps

Tpt 815 ps 925 ps

Transmit Mode

Power Consumption 59 μW/MHz 66 μW/MHz

(a)

(b)

Fig. 4.14 The relation between ground bounce on VDD power line and wire bond inductance on the HCPMXIO and HCPMXIO-SR. (a) The overshoot and (b) the undershoot on VDD power line.

(a)

(b)

Fig. 4.15 The relation between ground bounce on GND power line and wire bond inductance on the HCPMXIO and HCPMXIO-SR. (a) The overshoot and (b) the undershoot on GND power line.