F UTRUE W ORKS

Since the proposed mixed-voltage I/O buffers in this thesis are designed with an operating speed of up to 266 MHz, the transmission line effect should be considered.

Thus transmission model should be added into simulation to have more accurate results. Besides, the circuit techniques for reducing short circuit current can be applied in the designs to further reduce the power consumption induced by short current. Also, the slew-rate control in mixed-voltage I/O buffer should be carefully designed without hot-carrier degradation during the transitions from receiving high input signal to transmitting low output signal. Finally, the measured methods for verifying the operations of mixed-voltage I/O buffer which have been mentioned in 4.7 should be used to have clear verifications.

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簡歷

VITA

姓 名：胡芳綾

學 歷：

台灣省立蘭陽女子高級中學 (86 年 9 月~89 年 6 月)

國立交通大學電機與控制工程學系 (89 年 9 月~93 年 6 月)

國立交通大學電子研究所碩士班 (93 年 6 月~95 年 6 月)

研究所修習課程：

類比積體電路I 吳介琮教授

類比積體電路II 吳介琮教授

數位積體電路 柯明道教授

有線傳輸通訊積體電路設計 陳巍仁教授

低功率與高速積體電路設計 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

計算機結構 黃俊達教授

顯示電子電路 戴亞翔教授

永久地址：宜蘭縣礁溪鄉礁溪路六段128 號

Email： fangling.ee93g@nctu.edu.tw fangling.ece89@nctu.edu.tw m9311593@alab.ee.nctu.edu.tw