Motivation

To realize SOP purposes, integrating pixel switching and peripheral driving ICs on single glass substrate are required [1.44]. However, it is a challenge to develop high-performance poly-Si TFTs for both pixel TFTs and display driving circuits [1.45]. To drive the liquid crystal, pixel TFTs operate at high voltages with low gate-leakage currents.

In contrast, TFTs with low operation voltages, low subthreshold swing, high driving capability, and low gate-leakage currents are required for approaching high-speed display driving circuits. However, traditional SPC poly-Si TFTs with continued scaling SiO2 gate dielectric can increase the driving currents of poly-Si TFTs. But, a thinner SiO2 gate dielectric cannot still satisfy these demands due to the high gate-leakage currents and poor electrical reliability [1.46]. With the same physical gate-dielectric thickness, introducing high dielectric constant (high-κ) material to replace SiO2 as the gate dielectric can increase the gate capacitance density and then induce much more mobile carrier density in the channel region. Therefore, several high-κ gate dielectrics including ONO gate stack, Al2O3,

HfO2, and LaAlO3, have been proposed as replacement for SiO2 gate dielectric to improve the electrical performances of poly-Si TFTs due to better gate controllability [1.47]-[1.50].

Unfortunately, the implementation of ONO gate stack and Al2O3 could not effectively improve the device performances due to their lower dielectric constant. On the other hand, these polycrystalline high-κ materials might not be sufficiently stable under post-annealing process. Recent studies reported that thermally robust praseodymium oxide (Pr2O3) appeared as a promising high-κ gate dielectric in MOSFET owing to its outstanding dielectric properties, including high dielectric constant value of about 31, ultra-low gate-leakage currents, and superior reliability characteristics [1.51], [1.52]. In Chapter 2, poly-Si TFTs with high-κ Pr2O3 gate dielectric are demonstrated and investigated.

Nevertheless, such high gate capacitance density contributes to a high electric field at the gate-to-drain overlap area, resulting in more undesirable gate-induced drain leakage (GIDL) currents [1.53]. To address this GIDL current issue, a hydrogen-based plasma treatment technique is mostly adopted for reducing the trap states because hydrogen atoms can easily passivate the trap states at the poly-Si /gate dielectric interface and in the poly-Si grain boundaries [1.54]-[1.57]. However, the hydrogenated poly-Si TFTs suffer from a serious instability issue due to the easily broken of weak Si-H bonds under electrical stress [1.58]. The other promising strategy, fluorine passivation technique, has been utilized to improve the device performance by eliminating the trap states at the grain boundaries. In addition, strong Si-F bonds, more stable than Si-H bonds, can significantly improve the device reliability under long-term electrical stress [1.59], [1.60]. In Chapter 3 and 4, both fluorine ion implantation and low-temperature CF4 plasma treatment on poly-Si films are developed to effectively introduce fluorine atoms into the poly-Si film. Incorporating these two fluorine-passivated techniques into poly-Si TFTs with Pr2O3 gate dielectric are proposed and studied.

Moreover, the SPC process plays an important role to affect the electrical characteristics

of poly-Si TFTs [1.61]-[1.63]. For the traditional SPC process, an interface-nucleation scehme with too many nucleation sites at the α-Si/underlying SiO2 interface results in a small grain size and a large number of grain-boundary trap states [1.64]-[1.67]. Thus, many studies have been proposed to improve the microstructure of poly-Si film by introducing oxygen rich region at the α-Si/underlying SiO2 interface [1.68], [1.69]. The interface nucleation is effectively suppressed, and then the nucleation process with fewer nucleation sites initiating on the top free surface of α-Si film results in large grain size of poly-Si film.

In Chapter 4 and 5, two kinds of grain-size enhancement techniques associating with the surface-nucleation scheme, including deep Argon ion implantation into the α-Si/underlying SiO2 interface and novel floating-channel structure are proposed. Poly-Si TFTs with deep Argon ion implantation and floating-channel structure are demonstrated and investigated.

In addition, a lot of efforts have been put forth to improve the gate controllability and device performance by changing device structure of poly-Si TFTs with complicated steps, such as gate-overlapped lightly doped drain (GO-LDD) TFT [1.70], double-gate TFT [1.71], and gate-all-around TFT [1.72]. Besides, poly-Si TFTs with nano-scale feature sizes have also been proposed to reduce the influences of grain-boundary defects [1.73]-[1.77]. In these studies, the electrical performances of poly-Si TFTs could be remarkably improved by decreasing the channel dimensions to be comparable to, or still smaller than, the grain size.

However, poly-Si TFTs with narrow-width channels are directly defined by using costly electron-beam lithography (EBL) technology [1.73]-[1.75], which could not be practicable in flat-panel displays (FPDs). On the other hand, for the poly-Si TFTs with nanowire (NW) channels and multiple-gate configuration reported in [1.76], [1.77], the gate-induced drain leakage (GIDL) currents resulted from large gate-to-drain overlapping area is high and must be addressed by additional processes. In Chapter 6, we demonstrate a simple sidewall spacer technique to fabricate poly-Si TFTs with self-aligned formation of twin NW channels without any expensive photolithography process. Poly-Si TFTs with NW channels

crystallized by traditional SPC technique and advanced MILC technique are proposed and investigated.