Chapter 7 Conclusions and Further Recommendations
7.2 Further Recommendations
There are some interesting and important topics about poly-Si TFTs that are worthy to be further investigated:
(1) As described in Chapter 2, high-κ Pr2O3 gate dielectric is a good gate-dielectric candidate for high-performance poly-Si TFTs. However, the off-state gate-induced drain leakage (GIDL) currents of the poly-Si Pr2O3 TFTs are somewhat large. The inferior GIDL currents and the on-state electrical characteristics could be further
improved by using different device structures such as lightly doped drain (LDD) and field-induced drain (FID), and adopting advanced crystallization techniques such as metal-induced lateral crystallization (MILC) and excimer-laser crystallization (ELC).
(2) Deposition of high-κ gate dielectric by electron-beam evaporation system is a promising method to characterize the dielectric quality. However, the fabrication of poly-Si TFTs with electron-beam deposited gate dielectric may be limited due to the large-scale glass substrate. Metal-organic chemical vapor deposition (MOCVD) based system or so-gel spin coating method could be promising ways to deposit any pure high-κ, mixed high-κ, and mixed silicates gate dielectrics for further studies.
(3) In Chapter 3, CF4 plasma treatments provide a good passivation of trap states near the Pr2O3 gate dielectric/poly-Si channel interface. However, in this thesis, the fluorine radicals are generated by conventional PECVD systems. High-density plasma (HDP) and electron-cyclotron resonance (ECR) plasma are suggested to further dissociate the CF4 molecule into fluorine radicals, and thus improve the efficiency of fluorine passivation. Furthermore, introducing fluorine radicals from remote plasma system can avoid plasma-induced damage in the poly-Si film. Some further studies on the CF4
plasma treatments can be done by adopting these plasma systems.
(4) In Chapter 4 and 5, the electrical performances of the SPC poly-Si TFTs can be improved by utilizing these two kinds of poly-Si grain-size enlargement techniques.
The increase of poly-Si grain size usually accompanies the decrease of trap-state density. Integrating high-κ gate dielectric and these grain-size enhancement techniques into poly-Si TFTs to further improve the electrical characteristics is worthy to be studied.
(5) In Chapter 6, a simple sidewall spacer technique is utilized to fabricate poly-Si NW TFTs. The gate electrode with a naturally tri-gate-like structure can exhibit a good electrostatic controllability on the channel potential due to the stronger fringing electric
field. Using tunnel oxide/trapping nitride/blocking oxide (ONO) to replace the traditional gate oxide in the poly-Si NW TFTs may be a feasible way for achieving nonvolatile memory applications.
References
Chapter 1
[1.1] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N.
Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda and T. Nagano,
“ Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1305–1313, 1995.
[1.2] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, no. 11 pp.
1930–1936, 1996.
[1.3] T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita and H. Andoh, “400 dpi integrated contact type linear image sensors with poly-Si TFT’s analog readout circuits and dynamic shift registers,” IEEE Trans. Electron Devices, vol. 38, no. 5 pp. 1086–1096, 1991.
[1.4] Y. Hayashi, H. Hayashi, M. Negishi and T. Matsushita, “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chop,” IEEE Solid-State Circuits Conference (ISSCC), pp. 266, 1988.
[1.5] N. Yamauchi, Y. Inada and M. Okamura, “An intergated photodetector-amplifier using a-Si p-i-n photodiodes and poly-Si thin-film transistors,” IEEE Photonic Tech.
Lett., vol. 5, pp. 319, 1993.
[1.6] M. G. Clark, “Current status and future prospects of poly-Si,” IEE Proc. Circuits Devices Syst., vol. 141, no. 1, pp. 3, 1994.
[1.7] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”
Journal of the SID, vol. 9, pp. 169–172, 2001.
[1.8] S. Morozumi, K. Oguchi, S. Yazawa, Y. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video display addressed by poly-Si TFTs,” in SID Tech. Dig., pp.156, 1983.
[1.9] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Guest-host active matrix liquid-crystal display using high-voltage polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 38, pp. 1781–1786, 1991.
[1.10] W. G. Hawkins, “Polycrystalline-silicon device technology for large-area electronics,” IEEE Trans. Electron Devices, vol. 33, pp. 477–481, 1986.
[1.11] I. W. Wu, “Cell design considerations for high-aperture-ratio direct-view and projection polysilicon TFT-LCDs,” in SID Tech. Dig., pp. 19, 1995.
[1.12] T. Aoyama, G. Kawachi, N. Konishi, T. Suzuki, Y. Okajima, and K. Miyata,
“Crystallization of LPCVD silicon films by low temperature annealing,” J.
Electrochem. Soc., vol. 136, pp. 1169–1173, 1989.
[1.13] K. Zellama, P. Germain, S. Squelard, J. C. Bourgoin, and P. A. Thomas,
“Crystallization in amorphous silicon,” J. Appl. Phys., vol. 50, pp. 6995–7000, 1979.
[1.14] V. Subramanian and K. C. Saraswat, “High-performance germanium-seeded laterally crystallized TFT’s for vertical device integration,” IEEE Trans. Electron Devices, vol. 45, pp. 1934–1939, 1998.
[1.15] K. Y. Choi and M. K. Han, “Two-step annealed polycrystalline silicon thin-film transistors,” J. Appl. Phys., vol. 80, pp. 1883–1890, 1996.
[1.16] S. W. Lee and S. K. Joo, “Low temperature poly-si thin-film transistor fabricated by metal-induced lateral crystallization,” IEEE Electron Device Lett., vol. 17, pp.
160–162, Apr. 1996.
[1.17] V. Subramanian and K. C. Saraswat, “High-performance germaniumseeded laterally crystallized TFTs for vertical device integration,” IEEE Trans. Electron Devices, vol.
45, pp. 1934–1939, Sept. 1998.
[1.18] O. Nast, S. Brehme, D. H. Neuhaus, and S. R.Wenham, “Polycrystalline silicon thin films on glass by aluminum-induced crystallization,” IEEE Trans. Electron Devices, vol. 46, pp. 2062–2067, Oct. 1999.
[1.19] K. H. Lee, Y. K. Fang, and S. H. Fan, “Au metal-induced lateral crystallization (MILC) of hydrogenated amorphous silicon thin film with very low annealing temperature and fast MILC rate,” Electron. Lett., vol. 35, no. 13, pp. 1108–1109, June 1999.
[1.20] S. W. Lee, Y. C. Jeon, and S. K. Joo, “Pb induced lateral crystallization of amorphous Si thin films,” Appl. Phys Lett., vol. 66, no. 13, pp. 1671–1673, Mar. 27, 1995.
[1.21] H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. Ko, “Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method,” IEEE Trans. Electron Devices, vol. 47, pp. 1580–1586, Aug.
2000.
[1.22] V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three dimensional CMOS SOI integrated circuits using high-temperature metal-induced lateral crystallization,”
IEEE Trans. Electron Devices, vol. 48, pp. 1394–1399, July 2001.
[1.23] K. C. Saraswat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, “Novel 3-D structures,” in IEEE SOI Conf., Oct. 1999, pp. 54–55.
[1.24] G. K. Guist, and T. W. Sigmon, “High-performance laser-processed polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77–79, 1999.
[1.25] N. Kudo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1876–1879, 1994.
[1.26] T. Sameshima, S. Usui and M. Sekiya, “XeCl excimer laser annealing used in the fabrication of poly-Si TFT’s,” IEEE Electron Device Lett., vol. 7, no. 5, pp. 276–278,
1986.
[1.27] D. H. Choi, E. Sadauyki, O. Sugiura and M. Matsumra, “Excimer-laser crystallized poly-Si TFT’s with mobility more than 600 cm2/V.s,” IEEE Trans. Electron Devices, vol. 40, no. 11, pp. 2129, 1993.
[1.28] K. Shimizu, O. Sugiura and M. Matsumra, “High-mobility poly-Si thin-film transistors fabricated by a novel excimer laser crystallization method,” IEEE Trans.
Electron Devices, vol. 40, no. 1, pp. 112–117, 1993.
[1.29] J. Levinson et al., “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, pp. 1193–1202, 1982.
[1.30] J. G. Fossum, A. Ortiz-Conde, H. Schichijo, and S. K. Banerjee, “Effects of grain boundaries on the channel conductance of SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, pp. 933–940, 1983.
[1.31] G. Y. Yang, S. H. Hur and C. H. Han, “A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation,” IEEE Trans. Electron Devices, vol. 46, pp. 165–172, 1999.
[1.32] K. R. Olasupo and M. K, Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, pp.
1218–1223, 1996.
[1.33] T. I. Kamins and D. J. Marcoux, “Hydrogenation of transistors fabricated in polycrystalline silicon films,” IEEE Electron Device Lett., vol. EDL-1, p. 159–161, 1980.
[1.34] H. L. Chen and C. Y. Wu, “An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistors,” IEEE Trans. Electron Devices, vol. 45, pp. 2245–2247, 1998.
[1.35] T. Unagami and O. Kogure, “Large on/off current ratio and low leakage current poly-Si TFTs with multichannel structure,” IEEE Trans. Electron Devices, vol. 35,
no. 11, pp. 1986–1989, 1988.
[1.36] B. H. Min, C. M. Park and M. K. Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device Lett., vol. 16, no.
5, pp. 161–163, 1995.
[1.37] Z. Xiong, H. Liu, C. Zhu and Sin, J. K. O., “Characteristics of high-k spacer offset-gated polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp.
1304–1308, 2004.
[1.38] P. S. Shih, C. Y. Chang, T. C. Chang, T. Y. Huang, D. Z. Peng and C. F. Yeh, “A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition,” IEEE Electron Device lett., vol. 20, no. 8, pp. 421–423, 1999.
[1.39] K. Y. Choi and M. K. Han, “A novel gate-overlapped LDD poly-Si thin-film transistor,” IEEE Electron Device lett., vol. 17, no. 12, pp. 566–568, 1996.
[1.40] A. Bonfiglietti, M. Cuscuna, A.Valletta, L. Mariucci, A. Pecora, G. Fortunato, S. D.
Brotherton and J. R. Ayres, “Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration,” IEEE Trans. Electron Devices, vol. 50, no. 12, pp.
2425–2433, 2003.
[1.41] Y. Mishima and Y. Ebiko, “Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” IEEE Trans. Electron Devices, vol. 49, no. 6, pp.
981–985, 2002.
[1.42] H. C. Lin, C.-M Yu, C.-Y. Lin, K.-L.Yeh, T. Y. Huang and T. F. Lei, “A novel thin-film transistor with self-aligned field induced drain,” IEEE Electron Device Lett., vol. 22, no. 1, pp. 26–28, 2001.
[1.43] C. S. Lai, C. L. Lee, T. F. Lei and H. N. Chern, “A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset,” IEEE Electron Device lett.,
vol. 17, no. 5, pp. 199–201, 1996.
[1.44] B. D. Choi, H. S. Jang, O. K. Kwon, H. G. Kim, and M. J. Soh, “Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV/XGA projection system,” IEEE Trans. Consum. Electron, vol. 21, no. 3, pp. 100–103, Mar. 2000.
[1.45] J. K. Lee, J. B. Choi, S. M. Seo, C. W. Han, and H. S. Soh, “The application of tetraethoxysilane (TEOS) oxide to a-Si: H TFT’s as the gate insulator,” in Proc. SID Dig., 1998, vol. 29, pp. 439–442.
[1.46] A. Takami, A. Ishida, J. Tsutsumi, T. Nishibe, and N. Ibaraki, “Threshold voltage shift under the gate bias stress in low-temperature poly-silicon TFT with the thin gate oxide film,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 2000, pp.45–48.
[1.47] C. K. Yang, C. L. Lee, and T. F. Lei, “Enhanced H2-plasma effects on polysilicon thin-film transistors with thin ONO gate-dielectrics,” IEEE Electron Device Lett., vol. 16, no. 6, pp. 228–229, June 1995.
[1.48] Z. Jin, H. S. Kwok, and M. Wong, “High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators,” IEEE Electron Device Lett., vol.
19, no. 12, pp. 502–504, Dec. 1998.
[1.49] C. P. Lin, B. Y. Tsui, M. J. Yang, R. H. Huang, and C. H. Chien, “High-performance poly-silicon TFTs using HfO2 gate dielectric,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 360–363, May 2006.
[1.50] B. F. Hung, K. C. Chiang, C. C. Huang, Albert Chin, and S. P. McAlister,
“High-performance poly-silicon TFTs incorporating LaAlO3 as the gate dielectric,”
IEEE Electron Device Lett., vol. 26, no. 6, pp. 384–386, June 2005.
[1.51] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide,” in IEDM Tech. Dig., 2000, pp. 653–656.
[1.52] H. J. Mussig, H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, T. Guminskaya, K.
Ignatovich, J. P. Liu, P. Zaumseil, and Zavodinsky, ”Can Praseodymium Oxide be an Alternative High-K Gate Dielectric Material for Silicon Integrated Circuits?”
IEEE IRW Final Report, pp. 1–10, Apr. 2001.
[1.53] G. K. Guist and T. W. Sigmon, “High-performance thin-film transistors fabricated using excimer laser processing and grain engineering,” IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 925–932, Apr. 1998.
[1.54] M. J. Tasi, F. S. Wang, K. L. Cheng, S. Y. Wang, M. S. Feng, and H. C. Chen,
“Characterization of H2/N2 plasma passivation process for poly-Si thin-film transistors (TFTs),” Solid State Electronics, vol. 38, no. 5, pp. 1233–1238, 1995.
[1.55] C. K. Yang, T. F. Lei, C. L. Lee, “The combined effects of low pressure NH3
annealing and H2 plasma hydrogenation on polysilicon thin-film-transistors,” IEEE Electron Device Lett., vol. 15, pp. 389–390, 1994.
[1.56] H. C. Cheng, F. S. Wang, and C. Y. Huang, “Effects of NH3 plasma passivation on n-channel Polycrystalline silicon thin-film-transistors,” IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 64–68, 1997.
[1.57] H. N. Chern, C. L. Lee, and T. F. Lei, “H2/O2 plasma on polysilicon thin film transistor,” IEEE Electron Device Lett., vol. 14, pp. 115–117, 1993.
[1.58] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,”
IEEE Electron Device Lett., vol. 11, pp. 167–170, Apr. 1990.
[1.59] H. N. Chern, C. L. Lee, and T. F. Lei, “The effects of fluorine passivation on poly-Si thin film transistors,” IEEE Trans. Electron Devices, vol. 41, pp. 698–702, May 1994.
[1.60] C. K. Yang, T. F. Lei, and C. L. Lee, “Charateristics of top-gate thin-film transistors fabricated on fluorine-implanted and crystallized amorphous silicon films,” J.
Electrochem. Soc., vol. 143, no. 10, pp. 3302–3307, 1996.
[1.61] W. G. Hawkins, “Polycrystalline-silicon device technology for large-area electronics,” IEEE Trans. Electron Devices, vol. 33, pp. 477–481, 1986.
[1.62] A. Nakamura, F. Emoto, E. Fujii, A. Yamamoto, Y. Uemoto, H. Hayashi, Y. Kato, and K. Senda, “A high-reliability, low-operation-voltage monolithic active-matrixLCD by using advanced solid-phase-growth technique,” in IEDM Tech.
Dig., 1990, pp. 847–850.
[1.63] N. Lifshitz and S. Luryi, “, Enhanced channel mobility in polysilicon thin film transistors,” IEEE Electron Device Lett., vol. 15, no. 8, pp. 274–276, 1994.
[1.64] A. T. Voutsas and M. K. Hatalis, “Deposition and Crystallization of aSi Low Pressure Chemically Vapor Deposited Films Obtained by LowTemperature Pyrolysis of Disilane,” J. Electrochem. Soc., vol. 140, no. 3, pp. 871–877, 1993.
[1.65] E. Adachi, T. Aoyama, N. Konishi, T. Suzuki, Y. Okajima, and K. Miyata, “TEM observations of initial crystallization states for LPCVD Si films,” Jpn. J. Appl. Phys., vol. 27, pp. 1809–1811, 1988.
[1.66] C. H. Hong, C. Y. Park, and H. J. Kim, “Structure and crystallization of low-pressure chemical vapor deposited silicon films using Si2H6 gas,” J. Appl. Phys., vol. 71, pp. 5427–5432, 1992.
[1.67] L. Haji, P. Joubert, J. Stoemenos, and N. A. Economou, “Mode of growth and microstructure of polycrystalline silicon obtained by solid-phase crystallization of an amorphous silicon film” J. Appl. Phys., vol. 75, pp. 3944–3952, 1994.
[1.68] M. K. Ryu, S. M. Hwang, T. H. Kim, K. B. Kim, and S. H. Min, “The effect of surface nucleation on the evolution of crystalline microstructure during solid phase crystallization of amorphous Si films on SiO2,” Appl. Phys. Lett., vol. 71, pp.
3063–3065, 1997.
[1.69] M. K. Ryu, J. Y. Kwon, and K. B. Kim, “Solid phase crystallization (SPC) behavior
of amorphous Si bilayer films with different concentration of oxygen: Surface vs.
Interface-nucleation,” Mat. Res. Soc. Symp. Proc., vol. 621, pp. Q6.3.1–Q6.3.6, 2000.
[1.70] K. Ohgata, Y. Mishima, and N. Sasaki, “A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” in IEDM Tech.
Dig., 2000, pp. 205–208.
[1.71] Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, “A new polysilicon CMOS self-aligned double-gate TFT technology,” IEEE Tran. Electron Devices, vol. 52, no. 2, pp.
2629–2633, Dec. 2005.
[1.72] S. Miyamoto, S. Maegawa, S. Maeda, T. Ipposhi, H. Kuriyama, T. Nishimura, and N.
Tsubouchi, “Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM’s,” IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1693–1698, Aug. 1999.
[1.73] C. P. Lin, B. Y. Tsui, M. J. Yang, R. H. Huang, and C. H. Chien, “High-performance poly-silicon TFTs using HfO2 gate dielectric,” IEEE Electron Devices Lett., vol. 27, no. 5, pp. 360–363, May. 2006.
[1.74] Y. C. Wu, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C.
Y. Chang, “Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels,” IEEE Trans. Electron Devices, vol. 52, no 10, pp.
2343–2346, Oct. 2005.
[1.75] Y. C. Wu, T. C. Chang, P. T. Liu, Y. C. Wu, C. W. Chou, C. H. Tu, J. C. Lou, and C.
Y. Chang, “Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization,” Appl.
Phys. Lett., no 87, pp. 143504-1–143504-3, 2005.
[1.76] H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, “Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channel,” IEEE Trans.
Electron Devices, vol. 53, no. 10, pp. 2471–2477, Oct. 2006.
[1.77] C. J. Su, H. C. Lin, H. H. Tsai, H. H. Hsu, T. M. Wang, T. Y. Huang, and W. X. Ni,
“Operations of poly-Si nanowire thin-film transistor with a multiple-gated configuration,” Nanotechnology, vol. 18, no. 215205, 2007.
Chapter 2
[2.1] H. Ohshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” in IEDM Tech. Dig., 1989, pp. 157–160.
[2.2] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile application,” in Symp. VLSI Circuits, Dig. Tech. Papers, 2001, pp. 85–90.
[2.3] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility poly-Si TFTs for large-area LCDs,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1929–1933, Sept. 1989.
[2.4] A. Takami, A. Ishida, J. Tsutsumi, T. Nishibe, and N. Ibaraki, “Threshold voltage shift under the gate bias stress in low-temperature poly-silicon TFT with the thin gate oxide film,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 2000, pp.45–48.
[2.5] S. B. Samavedam, H. H. Tseng, P. J. Tobin, J. Mogab, S. Dakshina-Murthy, L. B. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B.-Y. Nguyen, L. Hebert, 0. Adetutu, V.
Dhandapani, T-Y.Luo, R. Garcia, P. Abramowitz, M. Moosa, D. C. Gilmer, C.
Hobbs, W. J. Taylor, J. M. Grant, R. Hegde, S. Bagchi, E. Luckowski, V.
Arunachalam, M. Azrak, “Metal Gate MOSFETs with ;HfO2 Gate Dielectric,” in Symp. VLSI Circuits, Dig. Tech. Papers, 2002, pp. 24–25.
[2.6] Y. Liu, S. Kijima, E. Sugimata, M. Masahara, K. Endo, T. Matsukawa,
“Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication,” IEEE Trans. Nanotechnology, vol. 5, no. 6, pp.
723–730, Nov. 2006.
[2.7] F. S. Wang, M. J. Tsai, and H. C. Cheng, “The effects of NH3 plasma passivation on polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 16, no. 11, pp.
530–505, Nov. 1995.
[2.8] C. K. Yang, C. L. Lee, and T. F. Lei, “Enhanced H2-plasma effects on polysilicon thin-film transistors with thin ONO gate-dielectrics,” IEEE Electron Device Lett., vol.
16, no. 6, pp. 228–229, June 1995.
[2.9] Z. Jin, H. S. Kwok, and M. Wong, “High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators,” IEEE Electron Device Lett., vol. 19, no. 12, pp. 502–504, Dec. 1998.
[2.10] C. P. Lin, B. Y. Tsui, M. J. Yang, R. H. Huang, and C. H. Chien, “High-performance poly-silicon TFTs using HfO2 gate dielectric,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 360–363, May 2006.
[2.11] B. F. Hung, K. C. Chiang, C. C. Huang, Albert Chin, and S. P. McAlister,
“High-performance poly-silicon TFTs incorporating LaAlO3 as the gate dielectric,”
IEEE Electron Device Lett., vol. 26, no. 6, pp. 384–386, June 2005.
[2.12] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide,” in IEDM Tech. Dig., 2000, pp. 653–656.
[2.13] H. J. Mussig, H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, T. Guminskaya, K.
Ignatovich, J. P. Liu, P. Zaumseil, and Zavodinsky, ”Can Praseodymium Oxide be an Alternative High-K Gate Dielectric Material for Silicon Integrated Circuits?”
IEEE IRW Final Report, pp. 1–10, Apr. 2001.
[2.14] AU. Mane, C. Wenger, T. Schroeder, P. Zaumseil, G. Lippert, G. Weidner and H. J.
Müssig, “A CMOS process-compatible wet-etching recipe for the high-k gate dielectrics Pr2O3 and Pr2TiO3,” J. Electrochem. Soc., vol. 152, no.6, pp.
C399-C402, 2005.
[2.15] B. H. Lee, Y. Jeon, K. Zawadzki, W. J. Qi, and J. Lee, “Effects of interfacial layer growth on the electrical characteristics of thin titanium films on silicon,” Appl. Phys.
Lett., vol. 74, pp. 3143–3145, 1999.
[2.16] H. Ogasawara, A. Kotani, R. Potze, G. A. Sawatzky, and B. T. Thole, “Praseodymium 3d- and 4d-core photoemission spectra of Pr2O3,” Phys. Rev. B., vol. 44, no. 11, pp.
5465–5469, Sept. 1991.
[2.17] A. A. Orouji and M. J. Kumar, “Leakage current reduction techniques in poly-Si TFTs for active matrix liquid crystal displays: a comprehensive study,” IEEE Trans.
Device and Materials Reliability, vol. 6, no. 2, pp. 315–325, June 2006.
[2.18] M. Wong, Z. Jin, G. A Bhat, P. C. Wong, and H. S. Kwok, “Characterization of the MIC/MILC interface and its effects on the performance of MILC thin-film transistors,” IEEE Electron Devices., vol. 47, no. 5, pp. 1061–1067, May 2000.
[2.19] T. Noguchi, A. T. Tang, J. A. Tsai, and R. Reif, “Comparison of effects between large-area-beam ELA and SPC on TFT characteristics,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1454–1458, Sept. 1996.
[2.20] Y. C. Wu, T. C. Chang, P. T. Liu, C. W. Chou, Y. C. Wu, C. H. Tu, and C. Y. Chang,
“High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates,” IEEE Trans.
Nanotechnology, vol. 5, no. 3, pp. 157–162, May 2006.
Chapter 3
[3.1] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility poly-Si TFTs for large-area LCDs,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1929–1933, Sep. 1989.
[3.2] H. Ohshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” in IEDM Tech. Dig., 1989, pp. 157–160.
[3.3] B. D. Choi, H. S. Jang, O. K. Kwon, H. G. Kim, and M. J. Soh, “Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV/XGA projection system,” IEEE Trans. Consum. Electron., vol. 21, no. 3, pp. 100–103, Mar. 2000.
[3.4] T. Aoyama, G. Kawachi, N. Konishi, T. Suzuki, Y. Okajima, and K. Miyata,
“Crystallization of LPCVD silicon films by low temperature annealing,” J.
Electrochem. Soc., vol. 136, no. 4, pp. 1169–1173, Apr. 1989.
[3.5] A. Takami, A. Ishida, J. Tsutsumi, T. Nishibe, and N. Ibaraki, “Threshold voltage shift under the gate bias stress in low-temperature poly-silicon TFT with the thin gate oxide film,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 2000, pp.
45–48.
[3.6] C. K. Yang, C. L. Lee, and T. F. Lei, “Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics,” IEEE Electron Device Lett., vol.
16, pp. 228–229, Jun. 1995.
[3.7] Z. Jin, H. S. Kwok, and M. Wong, “High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators,” IEEE Electron Device Lett., vol. 19, no. 12, pp. 502–504, Dec. 1998.
[3.8] M. Y. Um, S.-K. Lee, and H. J. Kim, “Characterization of thin film transistor using Ta2O5 gate dielectric,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 1998, pp.
45–46.
[3.9] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide,” in IEDM Tech. Dig., 2000, pp. 653–656.
[3.10] H. J. Mussig, H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, T. Guminskaya, K.
Ignatovich, J. P. Liu, P. Zaumseil, and Zavodinsky, “Can praseodymium oxide be an
alternative high-k gate dielectric material for silicon integrated circuits?” IEEE IRW
alternative high-k gate dielectric material for silicon integrated circuits?” IEEE IRW