Overview of Polycrystalline Silicon Thin-Film Transistors

Over the past two decades, polycrystalline silicon Thin-film transistors (poly-Si TFTs) have been widely used in many industrial applications, such as high-density static random access memories (SRAMs) [1.1], electrical erasable programming read only memories (EEPROMs) [1.2], linear image sensors [1.3], thermal printer heads [1.4], photo-detector amplifier [1.5], scanner [1.6], and active-matrix liquid-crystal displays (AMLCDs) [1.7]-[1.9]. In particular, the application of AMLCDs is the major driving force to promote and advance the developments of poly-Si TFT technology.

AMLCD is one of the most promising candidates for realizing large-area flat-panel displays. The application of n-channel amorphous silicon (α-Si) TFTs is constrained in the aspect of pixel switching elements. Hence, it is difficult to integrate pixel switching elements and peripheral driving circuits on single glass substrate for system-on-panel (SOP) applications because of the low electron field-effect mobility (typically below 1 cm²/Vs).

Moreover, the electrical properties of p-channel α-Si TFTs are worse than those of n-channel α-Si TFTs, making α-Si TFT technology not practical for CMOS circuits. As a result, poly-Si TFT technology has been steadily growing and become a promising solution for realizing high-performance AMLCD applications due to the advantages of high field-effect mobility, low photocurrents, high driving currents, high CMOS capability, and SOP applications [1.10], [1.11].

The quality of poly-Si films plays a critical role in the device performance and

reliability. Three major crystallization techniques have been proposed to achieve low-temperature poly-Si TFTs, described as follows.

1.1.1 Traditional Solid-Phase Crystallization (SPC)

Solid-phase crystallization (SPC) technique is usually performed at 600 ^οC [1.12]-[1.15].

The SPC process is composed of grain nucleation and grain growth. For the traditional SPC of α-Si with homogenous grain nucleation at the α-Si/underlyling SiO2 interface, the activation energy of the grain growth (3.2 eV) is less than that of the grain nucleation (3.9 eV). Therefore, the amount of the nucleation relative to the grain growth decreases with decreasing temperature. Moreover, such crystallized poly-Si films have a high density of grain-boundary defects and intra-grain defects, which degrade the electrical properties of poly-Si TFTs. An improved SPC technique has been proposed to enlarge the grain size of poly-Si by decreasing the grain nucleation rate even if SPC process is a time-consuming (several hours) process for phase transformation from amorphous into polycrystalline.

1.1.2 Metal-Induced Lateral Crystallization (MILC)

Metal-induced crystallization (MIC) technique with crystallization temperature lower than 600 ^οC has been studied in the past using trace metals such as Ni, Ge, Al, Au, and Pb [1.16]-[1.20]. However, the grain size of poly-Si is small compared to the feature size of transistor, and an undesirable metal contamination may be introduced at the channel region, degrading the electrical properties of poly-Si TFTs. In addition, poly-Si film with large grain size can be formed by the crystallization of α-Si through metal-induced lateral crystallization (MILC) technique [1.21]-[1-23]. This MILC technique is simple, less contamination, and can be adopted in three-dimensional (3-D) CMOS integrated circuits. The grain size of resulting poly-Si film is significantly enhanced and much larger than the device dimension.

1.1.3 Excimer-Laser Crystallization (ELC)

Excimer-laser crystallization (ELC) of α-Si film on glass substrate gives a good-quality poly-Si with low defect density and no intra-grain defect. Hence, this technique is thought to

be the most preferable crystallization method for the fabrication of poly-Si TFTs [1.24]-[1.28]. While ELC technique is the most commonly used method to manufacture poly-Si TFTs for display applications, there are many ongoing issues, including high manufacturing cost, uniformity concerns over large areas, narrow process window, high process complexity, rough poly-Si/gate oxide interface, and stability of electric performances, need to be resolved to attain a mature ELC poly-Si TFT technology.

Among these three major crystallization techniques, the most widely used method for poly-Si preparation is the SPC technique. Traditional SPC poly-Si TFT has many advantages over ELC poly-Si TFT, such as simplicity, low-cost batch process, high uniformity, and large area capability. Although the maximum processing temperature of SPC poly-Si TFT is limited by the crystallization temperature of around 600 ^οC, the processing temperature is still considered to be acceptable.

Poly-Si material consists of silicon crystallites (grains). Between them, there are regions with high density of impurities, called grain boundaries. Grain-boundary defects and intra-grain defects existing in the poly-Si film result in a large amount of trap states. The detrimental effect of grain boundaries on the electrical performances of poly-Si TFT has been investigated and been well recognized [1.29], [1.30]. At the turn-on state, the trap states can trap carriers to form potential barriers, and thus affect the on-state carrier transport [1.31].

At the turn-off state, the trap states in the depletion region of drain side result in large off-state leakage currents. The generation of leakage currents can be attributed to a thermionic emission at a low electric field and a field-enhanced emission (i.e. F-P emission or trap-assisted band-to-band tunneling) at a high electric filed [1.32]. The presence of a high density of trap states at the grain boundaries are thought to be related to the Si dangling bonds and Si strain bonds, resulting in severe degradations on the electrical properties of poly-Si TFTs, such as high threshold voltage, low field-effect mobility, large subthreshold swing, and high leakage currents. The grain-boundary effects can be reduced mainly by two

techniques: (1) by passivating the Si dangling bonds at the grain boundaries with plasma treatments and thus reducing the density of the grain-boundary defects [1.33], [1.34]; (2) by enlarging the grain size of poly-Si and thus reducing the number of grain boundaries present within the active channel of poly-Si TFT.

In addition, the device performances could also be improved by adopting novel device structures, including multiple channel structures [1.35], offset source/drain [1.36], [1.37], lightly doped drain (LDD) [1.38], gate-overlapped LDD (GO-LDD) [1.39]-[1.41], field-induced drain (FID) [1.42], and vertical channel [1.43]. This novel device structures focus on decreasing the electric field near the drain junction, and thus suppresses the off-state leakage currents of poly-Si TFTs.