Trap-State Density and Activation Energy

The grain-boundary trap-state density (Ntrap) of the Argon-implanted and control poly-Si TFTs could be extracted according to the grain-boundary trapping model proposed by Levinson and Proano [4.23], [4.24]. Fig. 4.6 shows the plot of ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² at VDS = 0.5 V and high gate voltage. Ntrap is estimated from the slopes of these curves. It can be found that the Argon-implanted poly-Si TFT exhibits a Ntrap of around 3.44×10¹² cm^-2, whereas the control one possess a Ntrap of 6.48×10¹² cm^-2. This result further confirms that Argon implantation treatment can reduce grain-boundary trap states in the poly-Si film due to the enlarged grain size and the reduced grain boundaries.

Fig. 4.7 illustrates the activation energy (EA) of drain current as a function of gate voltage measured at VDS = 5 V for the Argon-implanted and control poly-Si TFTs. EA was extracted by the measurement of IDS–VGS characteristics at various temperatures from 25 to 150 ^οC. EA represents the carrier transportability, which is related to the barrier height in the poly-Si channel [4.25]. The Argon-implanted poly-Si TFT exhibits a higher EA in turned-off state but a lower EA in turned-on state, as compared to the control poly-Si TFT. The result infers that Argon implantation treatment can obtain a better crystallinity of silicon grain with reduced trap-state density. Moreover, a steeper curve can be found in the subthreshold region, which proves that the interface quality of the Argon-implanted poly-Si TFT is better than that of the control one.

4.3.4 Threshold-Voltage Rolloff

To investigate the short-channel effect of the poly-Si TFTs, the threshold voltages of the

Argon-implanted and control poly-Si TFTs with their channel width (W) of 10 µm as a function of channel length (L) are shown in Fig. 4.8. The threshold voltage of the control poly-Si TFTs is decreased with decreasing the channel length, dominated by the reduction of the grain-boundary trap states, called threshold voltage rolloff effect, [4.26], [4.27].

Nevertheless, in the case of the Argon-implanted poly-Si TFT, its threshold-voltage rolloff effect could be well suppressed because it has fewer grain-boundary trap states in the poly-Si channel film. Moreover, the Argon implantation treatment also leads to a smaller threshold voltage due to the reduced grain-boundary trap states.

4.3.5 Device Reliability

Additionally, hot-carrier stress was carried out to investigate the device reliability. The Argon-implanted and control poly-Si TFTs were stressed at VDS = 20 V and VGS = 20 V for 10000 s. The variations of threshold voltage (∆VTH) over hot-carrier stress time are shown in Fig. 4.9. Hot carrier multiplication occurred at the drain side of poly-Si TFTs causes the degradation of threshold voltage. Notably, the variation of VTH of the Argon-implanted poly-Si TFT is smaller than that of the control poly-Si TFTs after stress time of 10000 s. It has been reported that the degradations of VTH caused by hot-carrier stress could be attributed to two reasons: the generation of interface states at the poly-Si channel/gate dielectric interface and the formation of deep trap states originated from the broken of weak Si-Si or Si-H bonds at the grain boundaries [4.28], [4.29]. The result hints that the poly-Si film with Argon implantation treatment forms larger grain size accompanied with fewer grain boundaries. Therefore, the Argon-implanted poly-Si TFTs with fewer grain boundaries in its channel film possess a superior hot-carrier endurance.

4.4 Summary

In summary, we have investigated the modified SPC of α-Si film with surface-nucleation scheme by heavy Argon ion implantation. The interface-nucleation rate is suppressed in the Argon-implanted α-Si film, resulting in a better microstructural quality of poly-Si films. The electrical characteristics of the poly-Si TFTs, including threshold voltage, subthreshold swing, field-effect mobility, trap-state density, and ON/OFF current ratio, are significantly improved using Argon ion implatation technique. In addition, the Argon-implanted poly-Si TFTs also present a higher immunity against the hot-carrier stresses attributing to larger grain size of poly-Si film with fewer grain-boundary defects. Therefore, the Argon-implanted poly-Si TFTs are not only compatible with conventional fabrication processes but also possessing superior electrical characteristics for large flat-panel display applications.

(a) Thermal oxidation, and α-Si deposition.

(b) Argon ion implantation with projected range located beyond α-Si/buffer oxide interface.

(c) Solid-phase crystallization of α-Si, and patterning of active region.

(d) Gate oxide and poly-Si gate deposition, and patterning of gate electrode.

(e) Self-aligned phosphorous ion implantation, and dopant activation.

(f) Passivation oxide deposition, patterning of contact hole, and formation of metal pad.

Fig. 4.1. Schematic diagram of the fabrication processes of the poly-Si TFTs with Argon ion implantation.

(a) SEM image of the Argon-implanted poly-Si film.

(b) SEM image of the control poly-Si film.

Fig. 4.2. SEM images of the secco-etched poly-Si films with and without Argon ion implantation after SPC process.

Fig. 4.3. XRD patterns of the Argon-implanted and control poly-Si films after SPC process.

Fig. 4.4. The SIMS depth profiles of oxygen and silicon for the Argon-implanted and control α-Si samples.

Fig. 4.5. Typical transfer characteristics of the Argon-implanted and control poly-Si TFTs at VDS = 0.5 V and 5 V.

Table 4.1 Devices characteristics comparison of the Argon-implanted and control poly-Si TFTs with a dimension of W/L = 10 µm/10 µm.

Fig. 4.6. Plot of ln[(IDS/VGS−VFB)] versus 1/(VGS−VFB)² and the extracted grain-boundary trap-state densities for the Argon-implanted and control poly-Si TFTs.

Fig. 4.7. Activation energy (EA) of the Argon-implanted and control poly-Si TFTs.

Fig. 4.8. Threshold-voltage rolloff of the Argon-implanted and control poly-Si TFTs at VDS

= 0.5 V.

Fig. 4.9. Variation of threshold voltage as a function of stress time for the Argon-implanted and control poly-Si TFTs.

Chapter 5

High-Performance Solid-Phase Crystallized Polycrystalline Silicon Thin-Film Transistors

with Floating-Channel Structure

5.1 Introduction

In recent years, polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used for active-matrix liquid crystal displays (AMLCDs). High-performance and superior-reliability poly-Si TFTs have the potential to realize the integration of peripheral driving circuits and pixel switching elements on single glass substrate [5.1], [5.2]. To fabricate poly-Si TFTs on an inexpensive glass substrate, low-temperature technology is required for realizing flat-panel displays (FPDs) owing to the maximum process temperature of being lower than 600 ^οC. The solid-phase crystallization (SPC) process is widely used for phase transformation from amorphous to polycrystalline due to its low fabrication cost and good grain-size uniformity. However, the electrical characteristics of SPC poly-Si TFTs are strongly correlated to the microstructure of poly-Si channel film. It is well known that the presence of a large number of grain boundaries and intragranular defects acting as scattering centers and midgap traps in the poly-Si film degrades the electrical properties of poly-Si TFTs [5.3], [5.4]. Therefore, the SPC process plays an important role in determining the device performance. Unfortunately, the traditional SPC process is an interface-nucleation scheme generating too many nucleation sites at the amorphous silicon/underlying oxide (α-Si/SiO2) interface, resulting in a smaller poly-Si grain size and many grain-boundary

defects [5.5], [5.6]. Various techniques have been employed to improve the device performance either by reducing the trap-state density [5.7], [5.8] or increasing the grain size of SPC poly-Si film [5.9], [5.12]. The hydrogen plasma treatment is widely used to reduce the trap-state density due to the passivation of trap states. Although hydrogen plasma treatment can improve the electrical performances, it is difficult to control the optimal processing time for satisfactory performance improvements.In addition, the hydrogenated poly-Si TFTs also suffer from a serious instability in their electrical characteristics under long-term electrical stress due to the easy breaking of weak Si-H bonds at the grain boundaries [5.13]. Recently, many modified SPC processes associated with surface-nucleation scheme were proposed to improve the microstructure of poly-Si film by utilizing oxygen doping at the α-Si/underlying SiO2 interface [5.9], [5.11]. It has been known that oxygen atoms retard the crystallization process of an oxygen-implanted α-Si film during solid-phase epitaxial regrowth [5.12]. As interface nucleation is effectively suppressed by the incorporation of oxygen atoms at the α-Si/SiO2 interface, the nucleation process will initiate at another preferable nucleation site on the top free surface of the α-Si film. Because of fewer nucleation sites at the top free surface of the α-Si film, a larger poly-Si grain size can be obtained. However, these modified surface-nucleation SPC processes mentioned previously require relatively complicated fabrication procedures, and they are not practical for TFT applications.

In this chapter, we take advantage of the modified SPC process with surface-nucleation scheme proposed by Bo et al. [5.14], and then design the self-aligned formation of a floating-channel structure without any additional sacrificial pattern to form the air gap.

Experimental results also confirm that the grain size and trap-state density of the poly-Si film with floating-channel structure are markedly improved; moreover, relatively better electrical characteristics are also achieved. Therefore, the proposed fabrication procedure for floating-channel poly-Si TFTs (FC poly-Si TFTs) is very simple and low cost. It is also

reproducible and compatible with existing poly-Si TFT manufacturing processes.

5.2 Experiments

Figs. 5.1(a) and 5.1(g) depict the bird’s eye and cross-sectional views of the proposed FC poly-Si TFT, respectively. The schematic diagram of the fabrication processes is illustrated in Figs. 5.1(b)-5.1(g). First, a 150-nm silicon nitride (Si3N4) layer, a 20-nm tetraethooxysilane (TEOS) oxide, and a 50-nm α-Si film were successively deposited by low-pressure chemical vapor deposition (LPCVD) to serve as buffered layer, dummy oxide, and channel film [Fig. 5.1(b)], respectively. After individual α-Si active regions were anisotropically patterned and defined, an isotropic wet etching was performed using buffer oxide etchant (BOE) solution with a constituent ratio of HF : NH4F = 7 : 1 to remove the dummy TEOS oxide to form the floating-channel α-Si region [Fig. 5.1(a) and Fig. 5.1(c)].

The etching rates of BOE for dummy TEOS oxide and α-Si were 15 nm/s and 0.4 nm/min, respectively. Therefore, the dummy TEOS oxide was etched for 90 s to make sure the floating-channel structure could be easily created between the large areas of source/drain pads. Subsequently, the α-Si film with a floating-channel structure was recrystallized at 600

°C for 24 h in N2 ambient for phase transformation from amorphous to polycrystalline [Fig.

5.1(d)]. After Radio Corporation of America (RCA) cleaning, a 100-nm TEOS oxide and a 150-nm poly-Si film were deposited to serve as the gate dielectric and gate electrode, respectively [Fig. 5.1(e)]. A self-aligned phosphorous ion implantation was performed at dosage and energy values of 5×10¹⁵ cm^-2 and 15 keV, respectively [Fig. 5.1(f)]. A 300-nm passivation SiO2 layer was deposited by plasma-enhanced CVD (PECVD), followed by the realization of dopant activation at 600 °C for 12 h and the definition of contact holes. Finally, a 400 nm Al electrode was deposited and patterned [Fig. 5.1(g)]. An NH3 plasma treatment was performed at 350 °C for 30 min after the Al electrode formation. For comparison,

conventional poly-Si TFTs (CN poly-Si TFTs) without the removal of dummy TEOS oxide were also fabricated [Fig. 5.1(h)]. Therefore, the distinction between the Si atoms unbounded and bounded to the underlying dummy TEOS oxide could be easily observed for the poly-Si films with floating-channel and conventional structures, respectively.

5.3 Results and Discussion

5.3.1 Material Analyses

A cross-sectional transmission electron microscopy (XTEM) image of the proposed FC poly-Si TFT structure is shown in Fig. 5.2. From the XTEM image, it is clearly observed that the thicknesses of the floating-channel poly-Si film and the air gap are 47 and 20 nm, respectively. Thus, there really exists a floating-channel poly-Si film on the air gap.

SEM images of poly-Si films used in the FC poly-Si TFTs and CN poly-Si TFTs after secco etching are shown in Fig. 5.3(a) and 5.3(b), respectively. These images obviously show that the average grain sizes of poly-Si films for the FC poly-Si TFT and CN poly-Si TFT are approximately 150 and 50 nm, respectively. The result indicates that a better polycrystalline structure with larger grain size and fewer intragranular defects can be obtained in the floating-channel poly-Si film.

5.3.2 Device Characteristics

Fig. 5.4 presents typical transfer characteristics (IDS-VGS) of the FC poly-Si TFTs and CN poly-Si TFTs. The measurements are performed at two different drain voltages of VDS = 0.5 V and 3 V. The drawn channel width (W) and channel length (L) are 1 µm and 10 µm, respectively. The parameters of the devices, including threshold voltage (VTH), field-effect mobility (µFE), and subthreshold swing (SS), are extracted at VDS = 0.5 V, whereas the maximum on-state driving current (ION) is defined at VDS = 3 V. The ON/OFF current ratio

(ION/IOFF) is defined as the ratio of the maximum on-state driving current to the minimum off-state leakage current at VDS = 3 V. The threshold voltage is defined as the gate voltage required to achieve a normalized drain current of IDS = (W/L)×100 nA at VDS = 0.5 V. The measured and extracted device parameters of the FC poly-Si TFTs and CN poly-Si TFTs are summarized in Table 5.1. Accordingly, the electrical properties of the FC poly-Si TFTs are significantly improved compared with those of the CN poly-Si TFTs. The threshold voltage and subthreshold swing of the FC poly-Si TFTs are 1.62 V and 264 mV/dec, whereas the CN poly-Si TFTs has values of 6 V and 971 mV/dec, respectively. The threshold voltage and subthreshold swing of the FC poly-Si TFTs are found to be superior to those of the CN poly-Si TFTs. Some studies indicated that the Si dangling bonds originating from the deep trap states have energy states near the middle of the Si bandgap, greatly affecting the threshold voltage and subthreshold swing [5.3]. The floating-channel poly-Si film with the surface-nucleation scheme can improve the poly-Si crystallinity with fewer trap states at the grain boundaries. In addition, the maximum on-state driving current and ON/OFF current ratio of the FC poly-Si TFTs are better than those of the CN poly-Si TFTs. The FC poly-Si TFTs exhibit approximately one order of magnitude enhancement in the maximum on-state driving current compared with the CN poly-Si TFTs at VGS = 20 V and VDS = 3 V. Moreover, the ON/OFF current ratio of the FC poly-Si TFTs is about eight times larger than that of the CN poly-Si TFTs. The result suggests that there must be larger poly-Si grains existing in the floating-channel poly-Si film, and thereby the subthreshold and on-state characteristics can be significantly improved.

Fig. 5.4 also shows the field-effect mobility versus gate voltage for the FC and CN poly-Si TFTs. The field-effect mobility is calculated from the transconductance at VDS = 0.5 V. As can be seen, the maximum field-effect mobility of the FC poly-Si TFTs is around three times higher than that of the CN poly-Si TFTs. Note that the strain bonds associated with the tail states near the silicon band edge in the poly-Si film, and at the gate dielectirc/poly-Si

interface greatly affect the field-effect mobility. The improvement on the field-effect mobility could be attributed to the enhancement of grain size and the reduction of grain boundaries, thereby leading to better poly-Si grain crystallinity in the floating-channel poly-Si film.

5.3.3 Trap-State Density and Output Characteristics

To verify the effect of poly-Si grain enhancement, the effective trap-state density (Ntrap) was extracted from the square root of the slope of ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² plots according to the grain-boundary trapping model proposed by Levinson et al [5.15]. Fig.

5.5 shows the ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² characteristics at VDS = 0.5 V and a high gate voltage for the FC and CN poly-Si TFTs. It can be found that the FC poly-Si TFT exhibits a Ntrap of 7.1×10¹¹ cm^-2, whereas the CN poly-Si TFT possesses a Ntrap of 1.36×10¹² cm^-2. This result further confirms that the floating-channel poly-Si film has much fewer grain boundaries and microstructure defects than the conventional poly-Si film due to the enlarged grain size.

Fig. 5.6 shows the output characteristics (IDS-VDS) of the FC and CN poly-Si TFTs. As can be seen, the FC poly-Si TFT exhibits a great enhancement in the driving current at VDS = 10 V and common gate driving voltages of VGS−VTH = 3, 6, 9, and 12 V. The improvement can be attributed to the field-effect mobility and threshold voltage of the FC poly-Si TFTs being higher and lower than those of the CN poly-Si TFTs.

5.3.4 Interface Nucleation v.s. Surface Nucleation

These electrical performance improvements strongly related to the crystallinity of poly-Si film could be qualitatively explained as follows. While using the traditional SPC process with interface-nucleation scheme to crystallize α-Si into poly-Si, the rearrangement of interfacial Si atoms and volume contraction of bulk Si film induce tensile stress at the

α-Si film/underlying SiO2 interface. Hence, a large number of crystalline defects, such as microtwins and dislocations, are generated to relieve the tensile stress. Following, numerous nucleation sites could be produced to result in smaller poly-Si grain size [5.11], [5.14].

Nevertheless, in the case of poly-Si film with a floating-channel structure in this work, the removal of underlying dummy TEOS oxide makes the Si atoms barely bound. As a result, the stress formed during the crystallization process could be easily relieved from the free Si surface pursing for fewer nucleation sites, thereby yielding good-quality poly-Si film with lower trap-state density and larger poly-Si grain size.

5.3.5 Device Reliability

Additionally, hot-carrier stress analysis was applied to investigate the device reliability.

The poly-Si TFT devices were bias-stressed at VDS = 20 V and VGS = 20 V for 10⁴ s to examine the hot-carrier stress immunity. The threshold-voltage shifts over hot-carrier stressing time for the FC and CN poly-Si TFTs are shown in Fig. 5.7. Hot-carrier multiplication occurring on the drain side of poly-Si TFTs causes the degradation of threshold voltage. The poly-Si TFT with a floating-channel structure shows less degradation in threshold voltage. Notably, the threshold-voltage shift of the FC poly-Si TFTs after a stress time of 10⁴ s is found to be 3 V, which is superior to that of the CN poly-Si TFTs (5.4 V). It has been reported that the degradations of threshold voltage caused by hot-carrier stress could be attributed to two reasons: the generation of interface states at the gate dielectric/poly-Si interface and the formation of deep trap states originating from the broken of weak Si-H bonds at the grain boundaries [5.13]. The result indicates that the poly-Si film with floating-channel structure crystallized by SPC process demonstrates a good-quality poly-Si film with larger grain size and fewer grain boundaries, resulting in better hot-carrier endurances.

5.4 Summary

In this study, we have demonstrated that the α-Si film with floating-channel structure crystallized by SPC process exhibits a better crystallinity of poly-Si film with larger grain size and fewer microstructural defects. Poly-Si TFTs with the self-aligned formation of the floating-channel active region is firstly proposed. The electrical characteristics of the FC

In this study, we have demonstrated that the α-Si film with floating-channel structure crystallized by SPC process exhibits a better crystallinity of poly-Si film with larger grain size and fewer microstructural defects. Poly-Si TFTs with the self-aligned formation of the floating-channel active region is firstly proposed. The electrical characteristics of the FC