Chapter 1 Introduction
1.3 Thesis Organization
This thesis is organized as follows,
In Chapter 1, the overview of poly-Si TFTs and the motivations of this thesis are described.
In Chapter 2, TiN metal gate and high-κ Pr2O3 gate dielectric are integrated into the SPC poly-Si TFTs. The integrity of the high-κ Pr2O3 gate dielectric is explored. The electrical characteristics and the short-channel effects of the poly-Si TFTs with Pr2O3 gate dielectric are studied.
In Chapter 3, two kinds of fluorine passivation effects using fluorine ion implantation and low-temperature CF4 plasma treatments are applied to the poly-Si TFTs with Pr2O3 gate dielectric are investigated. Effects of fluorine ion implantation and various rf powers of CF4
plasma treatments on the poly-Si films are explored. The electrical characteristics and reliability of the fluorine-passivated poly-Si TFTs with Pr2O3 gate dielectric are investigated.
In Chapter 4, deep Argon ion implantation with projection range beyond on the a-Si/underlying SiO2 interface is proposed to investigate the microstructure of postcrystallized poly-Si film. The electrical characteristics and reliability of SPC poly-Si TFTs with Argon ion implantation are demonstrated and studied.
In Chapter 5, poly-Si TFTs with floating-channel structure crystallized by solid-phase crystallization process are proposed and fabricated. The grain size and trap-state density of poly-Si film with floating-channel structure are analyzed; moreover, the electrical characteristics and reliability of SPC poly-Si TFTs with floating-channel structure are explored and studied.
In Chapter 6, a simple sidewall spacer technique is proposed for the formation of nano-scale channel width (nanowire, NW) without advanced photolithography system. The crystallization of poly-Si NW channels is formed by the SPC and MILC techniques. Effects of gate controllability on the proposed SPC NW TFTs and standard planar TFTs are explored.
Besides, the electrical properties of the MILC NW TFTs and the SPC NW TFTs are demonstrated and investigated.
In Chapter 7, conclusions as well as some recommendations for further research are given.
Chapter 2
High-Performance Polycrystalline Silicon Thin-Film Transistors with High-κ Pr
2O
3Gate Dielectric
2.1 Introduction
Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much attention in active-matrix liquid crystal displays (AMLCDs) for the sake of realizing the integration of peripheral driving circuits and pixel switching elements on single glass substrate to accomplish system-on-panel (SOP) purposes [2.1]-[2.3]. High-performance poly-Si TFTs with low operation voltages, low subthreshold swing, high driving capability, and low gate-leakage currents are required for approaching high-speed display driving circuits. However, traditional solid-phase crystallized (SPC) poly-Si TFTs with continued scaling SiO2 gate dielectric can not satisfy these demands [2.4]. In order to address these issues, integrating metal gate on high dielectric constant (high-κ) gate dielectric with poly-Si TFTs has received lots of attention for maintaining a higher gate capacitance density, a lower gate-leakage current, and a much more induced carrier density [2.5]-[2.11]. Besides, the trap states at poly-Si grain boundaries also could be quickly filled up to improve the subthreshold swing even without additional hydrogenation treatments [2.7]. Therefore, several high-κ gate dielectrics including ONO gate stack, Al2O3, HfO2, and LaAlO3 have been investigated as replacement for SiO2 gate dielectric to improve the electrical performances owing to better gate controllability [2.8]-[2.11]. Unfortunately, the implementation of ONO gate stack and Al2O3 could not effectively improve the device performances due to their lower dielectric constant. On the other hand, these polycrystalline high-κ materials might not be sufficiently
stable under post-annealing process. Recent studies reported that thermally robust praseodymium oxide (Pr2O3) appeared as a promising high-κ gate dielectric in MOSFET owing to its outstanding dielectric properties, including high dielectric constant (~31), ultra-low gate-leakage currents, and superior reliability characteristics [2.12], [2.13].
In this chapter, integrating TiN metal gate on high-κ Pr2O3 gate dielectric with SPC poly-Si TFTs is successfully demonstrated for the first time. The proposed poly-Si Pr2O3
TFTs show outstanding electrical characteristics as compared to poly-Si tetraethoxysilane (TEOS) TFTs; hence, poly-Si Pr2O3 TFTs can satisfy the needs of peripheral driving circuit applications with low operation voltages.
2.2 Experiments
The cross section of the proposed poly-Si TFTs with TiN metal gate and Pr2O3 gate dielectric is depicted in Fig. 2.1. The detail device fabrication is summarized below. First, a 100-nm amorphous silicon (α-Si) was deposited on 500-nm thermally oxidized Si wafers using low-pressure chemical vapor deposition (LPCVD) system at 550 οC [Fig. 2.1(a)].
Subsequently, the SPC annealing process at 600 οCfor 24 h in N2 ambient was used to crystallize the α-Si film. After the active regions were defined [Fig. 2.1(b)], a 33.6-nm Pr2O3
gate dielectric was deposited by using electron-gun evaporation system, and then annealed at 600 οCfor 30 min in O2 ambient to improve thin-film quality. After the deposition of a 200-nm TiN film, a Cl2 based plasma etching process capable of stopping on the Pr2O3 layer was used to pattern the gate electrode [Fig. 2.1(c)]. A self-aligned phosphorous ion implantation was performed, followed by the dopant activation at 600 οC for 30 min in N2
ambient [Fig. 2.1(d)]. After a 300-nm passivation SiO2 was deposited by plasma-enhanced CVD (PECVD), the definition of contact holes were achieved with the selective wet etching of passivation SiO2 and Pr2O3 by buffered oxide etch (BOE) and H2SO4/H2O2 solutions
[2.14], respectively [Fig. 2.1(e)]. Finally, the fabricated poly-Si Pr2O3 TFTs were sintered at 400 οC after the aluminum pad formation [Fig. 2.1(f)]. Moreover, the poly-Si TFTs with a 35-nm TEOS gate dielectric deposited by PECVD were also fabricated with the same process flow for comparison. Note that all the poly-Si TFTs had no hydrogenation treatment in this work.
2.3 Results and Discussion
2.3.1 Pr2O3 Gate Dielectric Integrity
The cross-sectional transmission electron microscopy (XTEM) image of the proposed poly-Si TFTs is shown in Fig. 2.2, which indicates a physical thickness of Pr2O3 gate dielectric around 33.6 nm with a 1.5-nm interfacial SiO2-like layer. An accumulation capacitance of 532 nF/cm2 is achieved for Pr2O3 gate dielectric from capacitance-voltage (C-V) measurement as shown in Fig. 2.3. Therefore, the equivalent-oxide thickness (EOT) was extracted to be 6.5 nm. The effective dielectric constant (κPr2O3) of Pr2O3 gate dielectric was extracted by using a Pr2O3/interfacial-SiO2 series capacitor model, expressed as Eq. (2.1) [2.15].
2
2 3
2 2 3
interficial-SiO interfacial-SiO Pr O Pr O
EOT =T + (k /k ) × T
………..Eq. (2.1) where κPr2O3 and κinterfacial-SiO2 are the dielectric constants for Pr2O3 and interfacial-SiO2 films, respectively, and TPr2O3 and Tinterfacial-SiO2 are the thicknesses of these films. Based on the relation in Eq. (2.1), the κPr2O3 was evaluated to be 26.2 by assuming the κinterfacial-SiO2 to be 3.9. Moreover, no C-V hysteresis characteristic on Pr2O3 gate dielectric occurs after repeating ±4 V forward and reverse stresses for 100 times.Fig. 2.4 shows the gate current density versus electric field (J-E) characteristic of the Pr2O3 gate dielectric film. The J-E characteristic of the Pr2O3 gate dielectric was measured by applying a gate voltage, with grounding the source and drain of poly-Si TFTs with Pr2O3
gate dielectric. Obviously, the breakdown field of the Pr2O3 gate dielectric is around 6.8 MV/cm, which is larger than that of the PECVD TEOS oxide of 5.4 MV/cm. Therefore, such high gate capacitance density, low charge-trapping phenomenon, and high dielectric breakdown field suggest that the Pr2O3 film is a promising high-κ gate-dielectric candidate for replacing conventional SiO2 film in the poly-Si TFTs.
The chemical composition of the Pr2O3 gate dielectric was determined by x-ray photoelectron spectroscopy (XPS) measurement. In this perspective, the XPS analysis was performed on a 33.6-nm Pr2O3 thin film. The XPS spectra of the Pr3d and O1s core level spectral regions are displayed in Figs. 2.5(a) and 2.5(b), respectively. The Pr3d signals consist of the 3d5/2 and 3d3/2 spin-orbit doublets. The main Pr3d XPS peak is centered at 934 eV, and its spin-orbit component is well separated at 954 eV. The shape, binding-energy values, and spin-orbit splitting associated with present Pr2O3 features are in agreement with previous reported data and indicate the existence of the Pr2O3 phase [2.16]. The shape of O1s XPS feature is quite complicated because of the overlap of different contributions. The visible peak at lower binding energy of 530 eV can be regarded as the Pr-O bonding. At higher binding energy of 533 eV, there is a broad signal due to the overlap of different components associated with SiO2 and hydroxides, that are formed on the film surface.
2.3.2 Device Characteristics
Fig. 2.6 shows the typical transfer characteristics (IDS-VGS) and transconductanes for the proposed poly-Si TFTs with Pr2O3 and TEOS gate dielectric with a dimension of width/length (W/L) = 2 µm/2 µm. The threshold voltage (VTH) is defined as the gate voltage required a normalized drain current of IDS = (W/L)×100 nA at VDS = 0.1 V. The ON/OFF current ratio (ION/IOFF) is defined as that ratio of the maximum on-state current to the minimum off-state current at VDS = 1 V. The poly-Si Pr2O3 TFT exhibits superior electrical performance than poly-Si TEOS TFT, including threshold voltage decreased from 2.28 to
1.27 V, subthreshold swing (S.S.) improved from 1.08 to 0.22 V/dec., field-effect mobility (µFE) enhanced from 23 to 40 cm2/V-s, and ION/IOFF ratio increased from 3.5×106 to 10.6×106. However, undesirable gate-induced drain leakage (GIDL) currents of the poly-Si Pr2O3 TFTs are higher than those of the poly-Si TEOS TFTs, especially under a continuously decreasing gate bias. The inferior GIDL currents may be ascribed to the higher electric field near the drain junction owing to the higher gate capacitance density of the high-κ Pr2O3 gate dielectric. The GIDL current issue could be solved by using lightly doped drain (LDD) structure [2.17].
2.3.3 Output Characteristics
Typical output characteristics (IDS-VDS) of the proposed poly-Si Pr2O3 TFTs and poly-Si TEOS TFTs are illustrated in Fig. 2.7. The device has a drawn channel length (L) and channel width (W) of 2 µm and 2 µm, respectively. As can be seen, the driving current of the poly-Si Pr2O3 TFTs (around 97 µA) is approximately six times larger than that of the poly-Si TEOS TFTs (around 16 µA) at VDS = 4 V and common gate drive of VGS–VTH = 4 V. This driving current enhancement results from the high capacitance density induced higher mobility and smaller threshold voltage for the poly-Si Pr2O3 TFTs compared with the poly-Si TEOS TFTs. Also, These excellent performances of poly-Si TFTs can be approached by SPC technique, without extra plasma treatments [2.6], or other advanced phase crystallization techniques with narrow process window [2.18], [2.19]. Hence, this large driving capability is attractive for high-speed peripheral driving IC’s applications.
2.3.4 Comparison with Other Researches
The measured and extracted device parameters are summarized in Table 2.1, including the other reported data for the SPC poly-Si TFTs with HfO2 [2.10] and LaAlO3 [2.11] gate dielectrics. This work provides the thinnest EOT of 6.5 nm realized on SPC poly-Si TFTs
with high-κ gate dielectrics. Without narrow channel-width effect [2.20], the calculated field-effect mobility of the poly-Si Pr2O3 TFTs is competed with that of the other reported poly-Si high-κ TFTs. By using refractory metal TiN [2.5], [2.6], the self-aligned implantation and dopant activation can be integrated intopoly-Si Pr2O3 TFTs after metal gate formation.
The higher gate capacitance density of high-κ Pr2O3 can quickly fill up the trap states at the grain boundaries in the poly-Si channel. Therefore, the performances of poly-Si Pr2O3 TFTs can be further improved, including moderate threshold voltage, lower subthreshold swing, and higher ON/OFF current ratio.
2.3.5 Threshold-Voltage Rolloff
To investigate the short-channel effects of the poly-Si Pr2O3 TFTs and poly-Si TEOS TFTs, the threshold-voltage rolloff properties are shown in Fig. 2.8. The threshold voltage of the poly-Si TFTs with SiO2 gate dielectric is decreased with continuously scaling down channel length, dominated by the reduction of grain-boundary trap states. In contrast, the poly-Si TFTs with Pr2O3 gate dielectric exhibit a high gate capacitance density to rapidly fill up the grain-boundary trap states and holds superior turn-on characteristics, and thus the threshold-voltage rolloff property could be well controlled.
2.4 Summary
High-performance SPC poly-Si TFTs integrated with Pr2O3 gate dielectric and TiN metal gate have been successfully demonstrated for the first time. This work provides the thinnest EOT of 6.5 nm from the high gate capacitance density of Pr2O3 film. The electrical characteristics of poly-Si Pr2O3 TFTs can be effectively improved compared to those of poly-Si TEOS TFTs, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, and higher driving current capability, even without additional
hydrogenation treatments or advanced phase crystallization techniques. Therefore, the proposed poly-Si Pr2O3 TFT technology is a promising candidate for future high-speed display driving circuit applications.
(a) Thermal oxidation, and α-Si deposition.
(b) Solid-phase crystallization of α-Si, and patterning of active region.
(c) Pr2O3 deposition and densification, TiN deposition, and patterning of gate electrode.
(d) Self-aligned phosphorus ion implantation, and dopant activation.
(e) Passivation oxide deposition, and patterning of contact hole.
(f) Al deposition, patterning of metal pad, and thermal sintering.
Fig. 2.1 Schematic process flows of the poly-Si TFTs with TiN metal gate and Pr2O3 gate dielectric.
Fig. 2.2 XTEM image of the proposed gate structure.
Fig. 2.3 The capacitance-voltage measurement of the Pr2O3 gate dielectric after repeating ± 4 V forward and reverse stresses for 100 times.
Fig. 2.4 Gate-current density versus electric field (J-E) characteristic of the poly-Si TFTs with TiN metal gate and Pr2O3 gate dielectric.
(a) XPS spectra of Pr3d core level.
(a) XPS spectra of O1s core level.
Fig. 2.5 The XPS spectra of Pr3d and O1s for the Pr2O3 gate dielectric.
Fig. 2.6 Typical transfer characteristics of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs with a dimension of W/L = 2 µm/2 µm.
Fig. 2.7 Output characteristics of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs with a dimension of W/L = 2 µm/2 µm.
Table 2.1 Electrical characteristics comparison for SPC poly-Si TFTs with various gate dielectrics, including Pr2O3 as well as TEOS oxide from this work, HfO2, and LaAlO3.
Fig. 2.8 Threshold-voltage rolloff propoerties of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs at VDS = 0.1 V.
Chapter 3
Characterizing Fluorine-Ion Implant and CF
4Plasma Treatment Effects on Polycrystalline Silicon
Thin-Film Transistors with Pr
2O
3Gate Dielectric
3.1 Introduction
Polycrystalline silicon thin film transistors (poly-Si TFTs) have received a considerable attention in fields such as large-area electronic applications including linear image sensors and active-matrix liquid crystal displays (AMLCDs) [3.1], [3.2]. The major application of poly-Si TFTs in AMLCDs lies in integrating the peripheral driving circuits and the pixel switching elements on the same glass substrate to realize system-integration-on-panel (SOP) technology [3.3]. The complicated process can be greatly simplified and then the fabrication cost also can be reduced by realizing SOP technology. Because poly-Si TFTs are usually fabricated on inexpensive glass substrate, low-temperature process is required for the realization of commercial flat-panel displays (FPDs). The solid-phase crystallization (SPC) process with maximum process temperature limiting to 600 °C is widely used to recrystallize amorphous silicon film due to its low production cost and good grain-size uniformity [3.4].
However, it is difficult to develop high-performance and high-reliability poly-Si TFTs that are applicable for both pixel switching elements and peripheral driving circuits. Pixel switching elements require TFTs to operate at high voltages as well as low gate-leakage currents to drive the liquid crystals. In contrast, TFTs with good electrical characteristics including low operation voltages, low subthreshold swings, high driving currents, and low gate-leakage currents are necessary for achieving the peripheral driving circuit applications.
However, the electrical properties of the SPC poly-Si TFTs are not good enough to meet the requirements of driving circuits. The SPC poly-Si TFTs with thinner physical thickness of SiO2 gate dielectric can increase the gate capacitance density to enhance the driving capability, but higher gate-leakage currents could be introduced by the thinner SiO2 gate dielectric, which would unavoidably degrade the device performances [3.5].
In order to address this issue, incorporating high-κ gate dielectrics into poly-Si TFTs can increase the gate capacitance density and then induce more mobile carriers in the channel region. To reach the same value of gate capacitance density, the physical thickness of high-κ gate dielectrics can be thicker than that of SiO2 gate dielectrics. Therefore, poly-Si TFTs with high-κ gate dielectrics can improve the gate controllability for enhancing the driving currents and suppressing the gate-leakage currents. Several high-κ materials including ONO gate stack, Al2O3, and Ta2O5, were proposed to replace conventional SiO2 to serve as the gate dielectrics of poly-Si TFTs [3.6]-[3.8]. However, the performance enhancement of the foregoing poly-Si TFTs is restricted by the lower dielectric constant of ONO gate stack as well as Al2O3 (κ< 9) and the narrow bandgap of Ta2O5. Recently, praseodymium oxide (Pr2O3) becomes a promising high-κ gate-dielectric candidate in MOSFET due to its high dielectric constant value of about 31, low gate-leakage currents, good dielectric properties, and superior thermal stability [3.9], [3.10]. Poly-Si TFTs incorporating Pr2O3 as gate dielectric have been proposed in our previous work [3.11], Chapter 2, which resolved the issues mentioned previously.
However, such high gate capacitance density would contribute to a high electric field at the gate-to-drain overlap area, resulting in rather high field-enhanced emission rates via the grain-boundary trap states. Therefore, poly-Si TFTs with high-κ gate dielectrics would suffer from more undesirable gate-induced drain leakage (GIDL) currents [3.12]. To address this GIDL current issue, various techniques including hydrogen plasma treatments and fluorine ion implantation on poly-Si films have been applied to greatly improve the device
performances by reducing the trap-state densities [3.13]-[3.16]. However, the hydrogenated poly-Si TFTs suffer from a serious instability issue due to the easily broken of weak Si-H bonds under electrical stress [3.14]. Another promising strategy, fluorine ion implantation, has been utilized to improve the device performances by effectively eliminating the trap states at the grain boundaries. In addition, strong Si-F bonds, more stable than Si-H bonds, formed in the poly-Si film and at the poly-Si/gate dielectric interface can significantly improve the device reliability under long-term electrical stress [3.15], [3.16]. However, the fluorine ion implantation method has troublesome problems in large-area electronics and subsequent high-temperature annealing is also required to activate the implanted fluorine ions and cure implant-indcued damages.
In this chapter, two kinds of simple, effective, and process-compatible fluorine-passivation techniques, fluorine ion implantation and low-temperature CF4 plasma treatments, have been utilized to introduce the fluorine ions into the poly-Si films for eliminating the trap states. CF4 plasma-treated process is more uncomplicated than fluorine-implanted process because of the lack of fluorine ion implantation and additional annealing step. We have successfully integrated these two kinds of fluorine-passivation techniques into the poly-Si TFTs with Pr2O3 gate dielectric and characterized their electrical and reliability characteristics.
3.2 Experiments
Fig. 3.1 illustrates the key fabrication steps for the proposed poly-Si Pr2O3 TFTs with fluorine ion implantation and CF4 plasma treatments. First, we describe the fluorine ion implantation process as follows. A 50-nm undoped amorphous silicon (α-Si) layer was deposited on a thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) system at 550 οC [Fig. 3.1(a-1)]. Following, the fluorine
ion implantation was realized with the accelerating energy and dosage at 10 keV and 5×1012 cm-2, respectively [Fig. 3.1(b-1)]. The fluorine ions were implanted into the α-Si layer with
ion implantation was realized with the accelerating energy and dosage at 10 keV and 5×1012 cm-2, respectively [Fig. 3.1(b-1)]. The fluorine ions were implanted into the α-Si layer with