Interface Nucleation v.s. Surface Nucleation

These electrical performance improvements strongly related to the crystallinity of poly-Si film could be qualitatively explained as follows. While using the traditional SPC process with interface-nucleation scheme to crystallize α-Si into poly-Si, the rearrangement of interfacial Si atoms and volume contraction of bulk Si film induce tensile stress at the

α-Si film/underlying SiO2 interface. Hence, a large number of crystalline defects, such as microtwins and dislocations, are generated to relieve the tensile stress. Following, numerous nucleation sites could be produced to result in smaller poly-Si grain size [5.11], [5.14].

Nevertheless, in the case of poly-Si film with a floating-channel structure in this work, the removal of underlying dummy TEOS oxide makes the Si atoms barely bound. As a result, the stress formed during the crystallization process could be easily relieved from the free Si surface pursing for fewer nucleation sites, thereby yielding good-quality poly-Si film with lower trap-state density and larger poly-Si grain size.

5.3.5 Device Reliability

Additionally, hot-carrier stress analysis was applied to investigate the device reliability.

The poly-Si TFT devices were bias-stressed at VDS = 20 V and VGS = 20 V for 10⁴ s to examine the hot-carrier stress immunity. The threshold-voltage shifts over hot-carrier stressing time for the FC and CN poly-Si TFTs are shown in Fig. 5.7. Hot-carrier multiplication occurring on the drain side of poly-Si TFTs causes the degradation of threshold voltage. The poly-Si TFT with a floating-channel structure shows less degradation in threshold voltage. Notably, the threshold-voltage shift of the FC poly-Si TFTs after a stress time of 10⁴ s is found to be 3 V, which is superior to that of the CN poly-Si TFTs (5.4 V). It has been reported that the degradations of threshold voltage caused by hot-carrier stress could be attributed to two reasons: the generation of interface states at the gate dielectric/poly-Si interface and the formation of deep trap states originating from the broken of weak Si-H bonds at the grain boundaries [5.13]. The result indicates that the poly-Si film with floating-channel structure crystallized by SPC process demonstrates a good-quality poly-Si film with larger grain size and fewer grain boundaries, resulting in better hot-carrier endurances.

5.4 Summary

In this study, we have demonstrated that the α-Si film with floating-channel structure crystallized by SPC process exhibits a better crystallinity of poly-Si film with larger grain size and fewer microstructural defects. Poly-Si TFTs with the self-aligned formation of the floating-channel active region is firstly proposed. The electrical characteristics of the FC poly-Si TFTs, including threshold voltage, subthreshold swing, field-effect mobility, ON/OFF current ratio, and hot-carrier immunity are significantly improved. Therefore, the proposed FC poly-Si TFTs are not only compatible with existing manufacturing processes but also possess superior electrical properties for large flat-panel display applications.

(a) Bird’s eye view of the FC poly-Si TFTs

(b) Buffered SiNx, dummy oxide, and α-Si deposition.

(c) Definition of active region, anisotropic dry etching of α-Si, and isotropic wet etching of dummy oxide to form floating-channel α-Si structure.

(d) Solid-phase crystallization of α-Si, and then form floating-channel poly-Si.

(e) Gate oxide and poly-Si gate deposition, and patterning of gate electrode.

(f) Self-aligned phosphorous ion implantation, and dopant activation.

(g) Passivation oxide deposition, patterning of contact hole, and formation of metal pad.

(Cross-sectional view of the FC poly-Si TFTs)

(h) Cross-sectional view of the CN poly-Si TFTs.

Fig. 5.1 Schematic diagram of the fabrication processes of the poly-Si TFTs with floating-channel structure.

Fig. 5.2 Cross-sectional TEM image of the FC poly-Si TFTs.

(a) SEM image of the floating-channel poly-Si film.

(b) SEM image of the conventional poly-Si film.

Fig. 5.3 SEM images of the secco-etched poly-Si films with and without floating-channel structure after SPC process.

Fig. 5.4 Typical transfer characteristics and the extracted field-effect mobility for the FC and CN poly-Si TFTs with a dimension of W/L = 1 µm/10 µm.

Table 5.1 Comparison of device characteristics for the FC and CN poly-Si TFTs with a dimension of W/L = 1 µm/10 µm.

Fig. 5.5 Plot of ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² and the extracted trap-state density (Ntrap) for the FC and CN poly-Si TFTs. IDS was measured at VDS = 0.5 V.

Fig. 5.6 Output characteristics of the FC and CN poly-Si TFTs with a dimension of W/L = 1 µm/10 µm.

Fig. 5.7 Threshold-voltage shift versus hot-carrier stress time for the FC and CN poly-Si TFTs.

Chapter 6

Polycrystalline Silicon Thin-Film Transistors with Nanowire Channel Fabricated by

Sidewall Spacer Technique

6.1 Introduction

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much considerable attention because they could be integrated with peripheral driving circuits and pixel switching elements on a low-cost glass substrate for active-matrix liquid-crystal display (AMLCD) applications [6.1], [6.2]. Also, poly-Si TFTs have the potential to be used in three-dimensional (3-D) circuits, including vertically integrated SRAMs [6.3] and DRAMs [6.4]. To improve the performances of poly-Si TFTs, several advanced crystallization techniques such as excimer-laser crystallization (ELC) [6.5] and metal-induced lateral crystallization (MILC) [6.6]-[6.8] have been developed to produce high-quality poly-Si film with large grain size and low microstructural defect density. However, the most widely used ELC technique still has many issues to be addressed for further developments. MILC technique is a low-cost batch process and also attractive for obtaining needlelike poly-Si grain with grain boundary parallel to the crystallization direction. Though considerable grain length can be obtained by MILC, the grain width achieved is still smaller than the device channel width, which can’t realize poly-Si TFTs with nearly single-grain active channel.

Recently, a lot of efforts have been put forth to enhance the gate controllability over the poly-Si channel by changing the device structures of poly-Si TFTs. Several device structures such as gate-overlapped lightly doped drain (GO-LDD) [6.9], double gate [6.10], and gate all

around [6.11] have been proposed to improve the device performances. However, these proposed device structures involve much more complicated fabrication steps, and are not practicable for poly-Si TFT manufacturing. Moreover, poly-Si TFTs with nano-scale feature sizes have also been proposed to reduce the influence of grain-boundary defects [6.12]-[6.16].

In these studies, the electrical performances of poly-Si TFTs could be remarkably improved by decreasing the channel dimensions to be comparable to, or still smaller than, the poly-Si grain size. However, the poly-Si TFTs with narrow-width channels directly defined using costly electron-beam lithography (EBL) technology could not be practicable in flat-panel displays (FPDs) [6.12]-[6.14]. On the other hand, for the poly-Si TFTs with nanowire (NW) channels and multiple-gate configuration reported in [6.15], [6.16], a undersiable gate-induced drain leakage (GIDL) current resulted from large gate-to-drain overlapping area is found and must be addressed by additional processes. Furthermore, in order to form tri-gate structure with NW channels, the extra top metal gate and bottom Si-substrate gate accompanied with high-temperature thermal oxide and rapid thermal processing are used [6.14], [6.15], which are difficult to process in LCD production line.

In this chapter, we propose a simple sidewall spacer technique to form self-aligned twin poly-Si NW, directly served as the channel regions of poly-Si TFTs, without any expensive photolithograpy process. Poly-Si TFTs with nanowire channels are crystallized by traditional solid-phase crystallization and advanced metal-induced lateral crystallization techniques. All processes are compatible with modern LCD production line, and suitable for system-on-panel (SOP) applications in the future.

6.2 Experiments

The key fabrication steps and the schematic top view of the proposed poly-Si NW TFTs are shown in Figs. 6.1(a)-(g) and (h), respectively. Firstly, a 150-nm SiNX and a 100-nm

tetraethooxysilane (TEOS) SiOX were deposited by plasma-enhanced chemical vapor deposition (PECVD) system to serve as the starting substrate and the dummy oxide layer, respectively [Fig. 6.1(a)]. After patterning and etching to be the dummy oxide stripe, a 100-nm amorphous silicon (α-Si) layer was conformally deposited by low-pressure CVD (LPCVD) at 550 °C [Fig. 6.1(b)], and then anisotropically etched to form square-coil α-Si sidewall spacer in a self-aligned manner [Fig. 6.1(c)]. The feature size of the α-Si spacer could be well controlled by turning dry etching condition and readily shrunk into nanoscale dimension without advanced photolithography technology. The α-Si sidewall spacer was then crystallized by traditional solid-phase crystallization technique at 600 °C for 24 h in N2

ambient to transform amorphous into polycrystalline. At the same time, to investigate the effect of metal-induced lateral crystallization technique on the proposed poly-Si NW TFT, a 200-nm low-temperature oxide (LTO) was deposited and patterned to expose the MILC window [Fig. 6.1(d)]. A 10-nm nickel (Ni) layer was deposited, and lateral crystallization was subsequently carried out at 550 °C for 24 h in N2 ambient. After the MILC process, the remaining Ni and LTO as well as dummy oxide stripe were etched away by hot sulfuric acid and hydrofluoric acid, respectively, and then the square-coil poly-Si NW was reserved [Fig.

6.1(e)]. Then, a 33-nm TEOS gate oxide and a 250-nm n⁺ poly-Si were deposited and patterned to form the gate electrode [Fig. 6.1(f)]. Next, a self-aligned phosphorus ion implantation was performed at 15 keV to a dose of 5×10¹⁵ cm^-2 to dope the source/drain regions, followed by the dopant activation at 600 °C^ for 12 h in N2 ambient. Finally, typical passivation layer deposition, contact hole opening, and metal pad formation completed the device fabrication [Fig. 6.1(g)].

6.3 Results and Discussion

6.3.1 Material Analyses

Fig. 6.2 (a) shows the cross-sectional transmission electron microscopy (XTEM) image of the proposed poly-Si NW TFTs having a couple of NW channels. Here, such test structure with small dimension of 300-nm distance is used to make the illustration more clear. The fractional enlarging plot of poly-Si NW channel is shown in Fig. 6.2(b). Because the poly gate electrode pattern is perpendicularly across the poly-Si NW channels, a couple of active NW channels would be formed after removing the dummy oxide stripe in the proposed poly-Si NW TFTs. From the cross-sectional TEM image, the vertical sidewall thickness (TSi) and horizontal width (WSi) are approximately 50 nm. The aspect ratio TSi/WSi of the active NW channel in the poly-Si NW TFTs (approximately equals to one) is larger than that of large-width channel in the standard planar poly-Si TFTs (much smaller than one). Such high aspect ratio means that the gate electrode forms in a tri-gate-like structure with well electrostatic controllability on channel potential due to sidewall and corner contribution effects [6.17], [6.18].