Summary

High-performance SPC poly-Si TFTs integrated with Pr2O3 gate dielectric and TiN metal gate have been successfully demonstrated for the first time. This work provides the thinnest EOT of 6.5 nm from the high gate capacitance density of Pr2O3 film. The electrical characteristics of poly-Si Pr2O3 TFTs can be effectively improved compared to those of poly-Si TEOS TFTs, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, and higher driving current capability, even without additional

hydrogenation treatments or advanced phase crystallization techniques. Therefore, the proposed poly-Si Pr2O3 TFT technology is a promising candidate for future high-speed display driving circuit applications.

(a) Thermal oxidation, and α-Si deposition.

(b) Solid-phase crystallization of α-Si, and patterning of active region.

(c) Pr2O3 deposition and densification, TiN deposition, and patterning of gate electrode.

(d) Self-aligned phosphorus ion implantation, and dopant activation.

(e) Passivation oxide deposition, and patterning of contact hole.

(f) Al deposition, patterning of metal pad, and thermal sintering.

Fig. 2.1 Schematic process flows of the poly-Si TFTs with TiN metal gate and Pr2O3 gate dielectric.

Fig. 2.2 XTEM image of the proposed gate structure.

Fig. 2.3 The capacitance-voltage measurement of the Pr2O3 gate dielectric after repeating ± 4 V forward and reverse stresses for 100 times.

Fig. 2.4 Gate-current density versus electric field (J-E) characteristic of the poly-Si TFTs with TiN metal gate and Pr2O3 gate dielectric.

(a) XPS spectra of Pr3d core level.

(a) XPS spectra of O1s core level.

Fig. 2.5 The XPS spectra of Pr3d and O1s for the Pr2O3 gate dielectric.

Fig. 2.6 Typical transfer characteristics of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs with a dimension of W/L = 2 µm/2 µm.

Fig. 2.7 Output characteristics of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs with a dimension of W/L = 2 µm/2 µm.

Table 2.1 Electrical characteristics comparison for SPC poly-Si TFTs with various gate dielectrics, including Pr2O3 as well as TEOS oxide from this work, HfO2, and LaAlO3.

Fig. 2.8 Threshold-voltage rolloff propoerties of the proposed poly-Si Pr2O3 TFTs and the poly-Si TEOS TFTs at VDS = 0.1 V.

Chapter 3

Characterizing Fluorine-Ion Implant and CF

₄

Plasma Treatment Effects on Polycrystalline Silicon

Thin-Film Transistors with Pr

₂

O

₃

Gate Dielectric

3.1 Introduction

Polycrystalline silicon thin film transistors (poly-Si TFTs) have received a considerable attention in fields such as large-area electronic applications including linear image sensors and active-matrix liquid crystal displays (AMLCDs) [3.1], [3.2]. The major application of poly-Si TFTs in AMLCDs lies in integrating the peripheral driving circuits and the pixel switching elements on the same glass substrate to realize system-integration-on-panel (SOP) technology [3.3]. The complicated process can be greatly simplified and then the fabrication cost also can be reduced by realizing SOP technology. Because poly-Si TFTs are usually fabricated on inexpensive glass substrate, low-temperature process is required for the realization of commercial flat-panel displays (FPDs). The solid-phase crystallization (SPC) process with maximum process temperature limiting to 600 °C is widely used to recrystallize amorphous silicon film due to its low production cost and good grain-size uniformity [3.4].

However, it is difficult to develop high-performance and high-reliability poly-Si TFTs that are applicable for both pixel switching elements and peripheral driving circuits. Pixel switching elements require TFTs to operate at high voltages as well as low gate-leakage currents to drive the liquid crystals. In contrast, TFTs with good electrical characteristics including low operation voltages, low subthreshold swings, high driving currents, and low gate-leakage currents are necessary for achieving the peripheral driving circuit applications.

However, the electrical properties of the SPC poly-Si TFTs are not good enough to meet the requirements of driving circuits. The SPC poly-Si TFTs with thinner physical thickness of SiO2 gate dielectric can increase the gate capacitance density to enhance the driving capability, but higher gate-leakage currents could be introduced by the thinner SiO2 gate dielectric, which would unavoidably degrade the device performances [3.5].

In order to address this issue, incorporating high-κ gate dielectrics into poly-Si TFTs can increase the gate capacitance density and then induce more mobile carriers in the channel region. To reach the same value of gate capacitance density, the physical thickness of high-κ gate dielectrics can be thicker than that of SiO2 gate dielectrics. Therefore, poly-Si TFTs with high-κ gate dielectrics can improve the gate controllability for enhancing the driving currents and suppressing the gate-leakage currents. Several high-κ materials including ONO gate stack, Al2O3, and Ta2O5, were proposed to replace conventional SiO2 to serve as the gate dielectrics of poly-Si TFTs [3.6]-[3.8]. However, the performance enhancement of the foregoing poly-Si TFTs is restricted by the lower dielectric constant of ONO gate stack as well as Al2O3 (κ< 9) and the narrow bandgap of Ta2O5. Recently, praseodymium oxide (Pr2O3) becomes a promising high-κ gate-dielectric candidate in MOSFET due to its high dielectric constant value of about 31, low gate-leakage currents, good dielectric properties, and superior thermal stability [3.9], [3.10]. Poly-Si TFTs incorporating Pr2O3 as gate dielectric have been proposed in our previous work [3.11], Chapter 2, which resolved the issues mentioned previously.

However, such high gate capacitance density would contribute to a high electric field at the gate-to-drain overlap area, resulting in rather high field-enhanced emission rates via the grain-boundary trap states. Therefore, poly-Si TFTs with high-κ gate dielectrics would suffer from more undesirable gate-induced drain leakage (GIDL) currents [3.12]. To address this GIDL current issue, various techniques including hydrogen plasma treatments and fluorine ion implantation on poly-Si films have been applied to greatly improve the device

performances by reducing the trap-state densities [3.13]-[3.16]. However, the hydrogenated poly-Si TFTs suffer from a serious instability issue due to the easily broken of weak Si-H bonds under electrical stress [3.14]. Another promising strategy, fluorine ion implantation, has been utilized to improve the device performances by effectively eliminating the trap states at the grain boundaries. In addition, strong Si-F bonds, more stable than Si-H bonds, formed in the poly-Si film and at the poly-Si/gate dielectric interface can significantly improve the device reliability under long-term electrical stress [3.15], [3.16]. However, the fluorine ion implantation method has troublesome problems in large-area electronics and subsequent high-temperature annealing is also required to activate the implanted fluorine ions and cure implant-indcued damages.

In this chapter, two kinds of simple, effective, and process-compatible fluorine-passivation techniques, fluorine ion implantation and low-temperature CF4 plasma treatments, have been utilized to introduce the fluorine ions into the poly-Si films for eliminating the trap states. CF4 plasma-treated process is more uncomplicated than fluorine-implanted process because of the lack of fluorine ion implantation and additional annealing step. We have successfully integrated these two kinds of fluorine-passivation techniques into the poly-Si TFTs with Pr2O3 gate dielectric and characterized their electrical and reliability characteristics.

3.2 Experiments

Fig. 3.1 illustrates the key fabrication steps for the proposed poly-Si Pr2O3 TFTs with fluorine ion implantation and CF4 plasma treatments. First, we describe the fluorine ion implantation process as follows. A 50-nm undoped amorphous silicon (α-Si) layer was deposited on a thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) system at 550 ^οC [Fig. 3.1(a-1)]. Following, the fluorine

ion implantation was realized with the accelerating energy and dosage at 10 keV and 5×10¹² cm^-2, respectively [Fig. 3.1(b-1)]. The fluorine ions were implanted into the α-Si layer with the projection range locating at the middle of the α-Si film. Subsequently, a solid-phase crystallization (SPC) process was performed at 600 ^οCfor 24 h in N2 ambient for phase transformation from amorphous to polycrystalline and activation of fluorine-ion dopants.

Individual active regions were patterned and defined [Fig. 3.1(c-1)]. A 40-nm Pr2O3 gate dielectric was deposited by electron-beam evaporation system, and densified at 600 ^οC for 30 min in O2 ambient to improve the gate-dielectric quality. Second, we depict the CF4 plasma treatment technique as follows. A 100-nm α-Si layer was deposited on a thermally oxidized Si wafer [Fig. 3.1(a-2)], and then followed by the realization of SPC process and the definition of individual active region [Fig. 3.1(b-2)]. After RCA clean process, a CF4 plasma treatment process was applied on the recrystallizaed poly-Si film by plasma-enhanced CVD (PECVD) system at 350 ^οC [Fig. 3.1(c-2)]. The chamber pressure and flow rate of CF4

reaction gas were 400 mtorr and 80 sccm, respectively. To investigate the effect of CF4

plasma treatments on the poly-Si Pr2O3 TFTs, various radio frequency (rf) powers of 0 W, 10 W, and 20 W, with a constant treating time of 20 s, were used to perform the CF4 plasma treatments. A 33.6-nm Pr2O3 gate dielectric was deposited by electron-beam evaporation, followed by a realization of thermal annealing treatment at 600 ^οC for 30 min in O2 ambient.

Afterwards, the fluorine-implanted and CF4 plasma-treated poly-Si films were performed with the same following processes. After a 200-nm TiN film was deposited, a Cl2 based dry etching process capable of stopping on the Pr2O3 layer was used to pattern the gate electrode [Fig. 3.1(d-1) and 3.1(d-2)]]. A self-aligned phosphorous ion implantation was performed to dope the source/drain regions and then the dopant was activated by the thermal budget of 600 ^οC for 30 min [Fig. 3.1(e)]. After a 300-nm passivation SiO2 layer was deposited by PECVD system at 300 ^οC, the contact holes were opened by a two-step wet etching process.

The 300-nm passivation SiO2 layer and the Pr2O3 layer were etched away by a buffered

oxide etch (BOE) solution and a H2SO4/H2O2 mixture solution, respectively [Fig. 3.1(f)].

Since the H2SO4/H2O2 mixture solution has rather high etching selectivity of the Pr2O3 film to the passivation SiO2 layer, the Pr2O3 film can be completely etched away by an excess of overetching. Finally, a typical 400-nm Al metallization completed the fabrication process [Fig. 3.1(g)]. For comparison, the control poly-Si Pr2O3 TFTs without the fluorine ion implantation step and the CF4 plasma treatment, rf power of 0 W, were also prepared with the same process flow. In order to study the fluorine-passivation effects on the poly-Si Pr2O3

TFTs, no additional hydrogen plasma treatment and thermal sintering process were performed after the Al electrode formation.

3.3 Results and Discussion

3.3.1 Fluorine-Ion Implant Effect on Pr

₂

O

₃

TFTs

3.3.1.1 Pr2O3 Gate Dielectric Integrity

The cross-sectional transmission electron microscopy (XTEM) image of the integrated Pr2O3 gate dielectric on the fluorine-implanted poly-Si TFTs is depicted in Fig. 3.2. From the XTEM image, the physical thicknesses of the Pr2O3 gate dielectric and the poly-Si channel are around 40 nm and 48 nm, respectively. The higher resolution XTEM image near the Pr2O3/poly-Si interface displayed in the inset of Fig. 3.2 exhibits an around 1.5-nm SiO2-like interfacial layer between the Pr2O3 gate dielectric and poly-Si channel. A metal-oxide-semiconductor (MOS) capacitor with Pr2O3 gate dielectric on single-crystalline Si wafer was also fabricated to obtain the gate capacitance density of Pr2O3 gate dielectric.

Fig. 3.3 shows typical capacitance-voltage (C-V) characteristics of the MOS capacitor at 1 MHz. The MOS capacitor has the same gate-dielectric thickness as the proposed TFT device has. An accumulation gate capacitance density (Cacc) at applied gate voltage of VG = −4 V is 463 nF/cm². Therefore, the equivalent-oxide thickness (EOT) of the Pr2O3 gate dielectric

extracted from the accumulation gate capacitance density is 7.4 nm. The effective dielectric constant of the Pr2O3 gate dielectric was extracted by using a series capacitance of Pr2O3 gate dielectric and SiO2-like interfacial layer according to the series capacitor model [3.17], expressed as Eq. (3.1).

2 3 2 3

interfacial layer interfacial layer Pr O Pr O

EOT = T +( κ / κ ) × T

…………..Eq. (3.1) where κPr2O3 and κinterfacial layer are the dielectric constants of Pr2O3 gate dielectric and SiO2-like interfacial layer, respectively, and TPr2O3 and Tinterfacial layer are the thicknesses of these films. Here, the TPr2O3 and Tinterfacial layer are assumed to be 40 nm and 1.5 nm, respectively, and the κinterfacial layer is assumed to be 3.9 to simplify the calculation. Based on the relation in Eq. (3.1), the effective dielectric constant of the Pr2O3 gate dielectric (κPr2O3) is extracted to be 26. The inset in Fig. 3.3 shows the hysteresis characteristics of the Pr2O3

gate dielectric upon sweeping from accumulation to inversion (−4 V to 4 V) and then sweeping back (4 V to −4 V). The Pr2O3 gate dielectric demonstrates a negligible hysteresis characteristic of 7.2 mV. Therefore, such high gate capacitance density, and low charge-trapping phenomenon suggest that the Pr2O3 film is a promising high-κ gate-dielectric candidate for replacing conventional SiO2 film in the poly-Si TFTs.

3.3.1.2 Evidence of Fluorine Incorporation

Fourier transform infrared spectroscopy (FTIR) and secondary ion mass spectroscopy (SIMS) analyses were utilized to verify the fluorine existing in the poly-Si film. The FTIR spectra of the fluorine-implanted and control poly-Si films after SPC process are shown in Fig. 3.4(a). The main peak of functional group Si-F bonds is clearly observed at around 930 cm^-1 in the fluorine-implanted poly-Si film [3.18]. The stronger peak of Si-O bond is derived from the underlying thermal SiO2 substrate. Therefore, Si-F bonds are formed in the poly-Si film by utilizing fluorine ion implantation. Moreover, Fig. 3.4(b) shows the SIMS profiles of

fluorine and praseodymium atoms for the fluorine-implanted poly-Si film. It was apparently observed that considerable fluorine ions were detected in the poly-Si film and, in particular, two obvious fluorine peaks were piled up at the Pr2O3 gate dielectric/poly-Si channel and the poly-Si channel/underlying thermal SiO2 interfaces. Note that the incorporated and piled-up fluorine ions in the poly-Si film and at the Pr2O3/poly-Si interface would bring about an effective passivation of deep trap states and interface states, resulting in fewer Si dangling bonds and Si strain bonds.

3.3.1.3 Device Characteristics

Fig. 3.5 shows the transfer characteristics (IDS-VGS) of the poly-Si Pr2O3 TFTs with and without fluorine ion implantation. The measurements are performed at two different drain voltages of VDS = 0.1 V and 1 V. The drawn channel width (W) and channel length (L) are 10 µm and 5 µm, respectively. The parameters of the devices, including threshold voltage (Vth), field-effect mobility (µFE), and subthreshold swing (S.S.) are extracted at VDS = 0.1 V, whereas the maximum off-state leakage currents (Ioff, max) and maximum on-state currents (Ion) are defined at VDS = 1 V. The on/off current ratio (Ion/Ioff) is defined as the ratio of the maximum on-state currents to the minimum off-state leakage currents at VDS= 1 V. The threshold voltage is defined as the gate voltage required to achieve a normalized drain current of IDS = (W/L)×100 nA. The detailed device parameters of the fluorine-implanted and control poly-Si Pr2O3 TFTs are summarized in Table 3.1.

Accordingly, the electrical performances of the fluorine-implanted poly-Si Pr2O3 TFT are remarkably improved compared to those of the control poly-Si Pr2O3 TFTs. With the fluorine ion implantation, the poly-Si Pr2O3 TFTs exhibit significant performance improvements in terms of drastically decreased threshold voltage from 1.57 to 0.65 V and reduced subthreshold swing from 320 to 216 mV/dec. It is known that the deep trap states, associated with the Si dangling bonds, accompanied with many energy states near the middle

of Si bandgap, would strongly affect the threshold voltage and subthreshold swing [3.13].

Therefore, introducing fluorine ions into the poly-Si film by fluorine ion implantation can effectively terminate the deep trap states at the grain boundaries. In addition, the maximum on-state currents and on/off current ratio of the fluorine-implanted poly-Si Pr2O3 TFTs are also superior to those of the control poly-Si Pr2O3 TFTs. The corresponding on/off current ratios for the fluorine-implanted and control poly-Si Pr2O3 TFTs are 1.6×10⁷ and 3.4×10⁶, respectively. The on/off current ratio of the fluorine-implanted poly-Si Pr2O3 TFTs is approximately five times larger than that of the control poly-Si Pr2O3 TFTs.

Fig. 3.5 also shows the relation between the field-effect mobility and gate voltage for the fluorine-implanted and control poly-Si Pr2O3 TFTs. The field-effect mobility is extracted from the transconductance value at VDS = 0.1 V. As can be seen, the maximum field-effect mobility of the fluorine-implanted poly-Si Pr2O3 TFTs is higher than that of the control poly-Si Pr2O3 TFTs. With the fluorine ion implantation, the poly-Si Pr2O3 TFT shows approximately 105 % enhancement in the maximum field-effect mobility. Note that the tail states near the Si bandedge resulted from the strain bonds in the poly-Si and at the Pr2O3/poly-Si interface would greatly affect the field-effect mobility [3.13]. This feature implies that the fluorine ion implantation treatment can not only passivate the Si dangling bonds but also relieve the Si strain bonds. The proposed poly-Si TFTs crystallized by SPC technique can demonstrate good electrical performances even without additional hydrogen plasma treatments or other advanced phase crystallization techniques with narrow process window [3.19], [3.20].

However, incorporating high-κ gate dielectric into poly-Si TFT would contribute to a higher electric field at the gate-to-drain overlap area, exhibiting higher field-enhanced emission rates via the grain-boundary trap states. Thus, the control poly-Si Pr2O3 TFTs would suffer from more undesirable gate-induced drain leakage (GIDL) currents, especially under continuously decreasing gate voltage. The GIDL current of the fluorine-implanted

poly-Si Pr2O3 TFTs (2.6×10^-10) is much lower than that of the control poly-Si Pr2O3 TFTs (1.2×10^-8), under applied voltages of VGS = −2 V and VDS = 1 V. This observation suggests that the incorporation of fluorine ions into the poly-Si film can effectively passivate the trap states, thereby resulting in lower GIDL currents under a high electric field.

3.3.1.4 Trap-State Density

In order to verify the effect of fluorine passivation, the grain-boundary trap-state density (Ntrap) was calculated from the square root of the slope of ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² plot according to the grain-boundary trapping model proposed by Proano et al.

[3.21]. Fig. 3.6 exhibits the ln[(IDS/(VGS−VFB)] versus 1/(VGS−VFB)² and the extracted grain-boundary trap-state densities at VDS = 0.1 V and high gate voltage for the fluorine-implanted and control poly-Si Pr2O3 TFTs. It can be found that the fluorine-implanted poly-Si Pr2O3 TFT shows a Ntrap of 4.58×10¹² cm^-2, whereas the control poly-Si Pr2O3 TFT possesses a Ntrap of 1.44×10¹³ cm^-2. This result implies that the fluorine ions can effectively passivate the present grain-boundary trap states in the poly-Si film, thereby exhibiting improved device performances. Combined with the SIMS profiles, we believe that the passivation effect is due to the piled-up and accumulated fluorine ions at the Pr2O3/poly-Si interface and in the poly-Si film.

3.3.1.5 Output Characteristics and Activation Energy

Fig. 3.7 shows the output characteristics (IDS-VDS) of the fluorine-implanted and control poly-Si Pr2O3 TFTs. As can be seen, with the fluorine ion implantation, the poly-Si Pr2O3

TFT exhibits a significant enhancement in the on-state driving current under common gate drive of VGS−VTH = 2, 3, and 4 V. The fluorine passivation of trap states would result in a higher field-effect mobility, thus exhibiting an obvious improvement on the driving capability.

Fig. 3.8 illustrates the activation energy (EA) of drain current as a function of gate voltage at VDS = 1 V for the fluorine-implanted and control poly-Si Pr2O3 TFTs. EA was extracted by the measurements of IDS-VGS characteristics at various temperatures ranging from 25 to 150 ^οC [3.22]. EA represents the carrier transport barrier across the grain boundaries in the poly-Si film. In the turned-off state, the value of EA reflects the required energy for field-enhanced emission of carriers via the trap states, whereas in the turned-on state, the value of EA reflects the carrier transport barrier height caused by the trap states

Fig. 3.8 illustrates the activation energy (EA) of drain current as a function of gate voltage at VDS = 1 V for the fluorine-implanted and control poly-Si Pr2O3 TFTs. EA was extracted by the measurements of IDS-VGS characteristics at various temperatures ranging from 25 to 150 ^οC [3.22]. EA represents the carrier transport barrier across the grain boundaries in the poly-Si film. In the turned-off state, the value of EA reflects the required energy for field-enhanced emission of carriers via the trap states, whereas in the turned-on state, the value of EA reflects the carrier transport barrier height caused by the trap states

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