Chapter 3 Characterizing Fluorine-Ion Implant and CF 4 Plasma Treatment
3.3.2.6 Activation Energy
Fig. 3.19 shows the activation energy (EA) of drain current as a function of gate voltage at VDS = 0.1 V for the poly-Si Pr2O3 TFTs without (0-W), and with 10-W and 20-W CF4
plasma treatments. The extracted EA of the optimal rf power of 10-W CF4 plasma-treated poly-Si Pr2O3 TFT is higher in the turn-off state and lower in the turn-on state, as compared with the 0-W (control) and 20-W samples. Introducing fluorine atoms into the poly-Si film by 10-W CF4 plasma treatment can effectively passivate the trap states, thereby reducing the trap-assisted leakage currents in the turn-off state and improving the carrier transport efficiency in the turn-on state. Besides, in the subthreshold region, a steeper slope is obtained in the 10-W CF4 plasma-treated sample. This verifies that the interface trap states in the 10-W CF4 plasma-treated sample are fewer than those in the 0-W and 20-W CF4
plasma-treated samples. The implication is consistent with the above extracted data of trap-state density.
3.3.2.7 Short-Channel Effect
To investigate the short-channel effect of the poly-Si Pr2O3 TFTs with and without 10-W CF4 plasma treatment, the average and statistical distributions of threshold voltage as a function of channel length with a fixed channel width of 10 µm are shown in Fig. 3.20. The number of sampling devices characterized under each condition is 20. The vertical bars in the figure indicate the minimum and maximum values of threshold voltage and the circle as well as square symbol presents the average values. The threshold voltage of the poly-Si TFTs with conventional SiO2 gate dielectrics is decreased with continuously scaling down channel length. In contrast, the poly-Si TFTs with Pr2O3 gate dielectrics possess high gate capacitance density to rapidly fill up the grain-boundary trap states and then maintain superior turned-on characteristics, demonstrating superior threshold-voltage rolloff properties. In addition, as the channel length scales down, fluctuations of threshold voltage by the variation of the number of grain boundaries in the poly-Si channel become severer for the control poly-Si Pr2O3 TFT. This is reasonable and is related to the inherent grain structure contained in the poly-Si channels. The trap states at the grain boundaries can be greatly
terminated by incorporating the fluorine atoms into the poly-Si film, leading to smaller fluctuations of threshold voltage. Therefore, integrating Pr2O3 gate dielectrics and fluorine-plasma passivation technique into the poly-Si TFTs can not only suppress the threshold-voltage rolloff properties but also reduce the fluctuations of threshold voltage.
3.3.2.8 Device Reliability
Finally, the influence of electrical stress on the poly-Si Pr2O3 TFTs with various rf powers of CF4 plasma treatments is examined. Figs. 3.21 and 3.22 show the threshold-voltage shift and on-current variation as a function of hot-carrier stress time for the poly-Si Pr2O3 TFTs with 0-W, 10-W, and 20-W CF4 plasma treatments. The TFT devices were biased at VGS = 6 V and VDS = 6 V. The CF4 plasma-treated samples show smaller threshold-voltage shift and on-current variation than the control sample. Notably, the threshold-voltage shift and on-current variation of the poly-Si Pr2O3 TFT with 10-W CF4
plasma treatment are found to be 1.84 V and 16.06 % after 1000 s stress, which are superior to those without CF4 plasma treatment (4.72 V and 38.34 %, respectively). Thus, introducing fluorine atoms into the poly-Si film by CF4 plasma treatment would result in the passivation of trap states and the formation of strong Si-F bonds in place of weak Si-H bonds, exhibiting superior endurance against hot-carrier stress.
3.4 Summary
We have incorporated two kinds of fluorination techniques including fluorine ion implantation and CF4 plasma treatments into the poly-Si Pr2O3 TFTs. Pr2O3 gate dielectric can achieve thin equivalent-oxide thickness and high gate capacitance density. Utilizing these fluorination techniques, fluorine atoms can be introduced into the poly-Si films and the Pr2O3 gate dielectric/poly-Si channel interface to passivate the grain-boundary trap states.
Hence, the electrical performances and threshold-voltage rolloff properties of the poly-Si Pr2O3 TFTs can be significantly improved. Besides, these fluorination techniques also enhance the immunity against hot-carrier stress, due to the formation of strong Si-F bonds. It is concluded that the integration of these effective fluorination techniques and Pr2O3 gate dielectric into the poly-Si TFTs could be available for achieving AMLCD applications.
(a-1) Thermal oxidation, and 50-nm α-Si deposition.
(a-2) Thermal oxidation, and 100-nm α-Si deposition.
(b-1) Fluorine ion implants into α-Si film. (b-2) Solid-phase crystallization of α-Si, and patterning of active region.
(c-1) Solid-phase crystallization of α-Si, and patterning of active region.
(c-2) Perform CF4 plasma treatment on poly-Si film.
(d-1) 40-nm Pr2O3 deposition, densification, and TiN gate formation.
(d-2) 33.6-nm Pr2O3 deposition, densification, and TiN gate formation.
(e) Self-aligned phosphorus ion implantation, and dopant activation.
(f) Passivation oxide deposition, and patterning of contact hole.
(g) Al electrode deposition and patterning.
Fig. 3.1 Schematic key fabrication steps for the proposed Pr2O3 gate dielectric TFTs on the fluorine-implanted and the CF4 plasma-treated poly-Si films.
Fig. 3.2 Cross-sectional TEM image of the proposed Pr2O3 gate dielectric TFTs on the fluorine-implanted poly-Si film.
Fig. 3.3 Typical C-V characteristic of the Pr2O3 gate dielectric. The inset shows the hysteresis characteristic of the Pr2O3 gate dielectric.
(a) FTIR spectra of the poly-Si film with and without fluorine ion implantation.
(b) SIMS depth profiles of the fluorine-implanted poly-Si TFTs with Pr2O3 gate dielectric.
Fig. 3.4 FTIR spectra of the poly-Si films with and without fluorine ion implantation and SIMS depth profiles of the fluorine-implanted poly-Si Pr2O3 TFTs.
Fig. 3.5 Transfer characteristics of the poly-Si Pr2O3 TFTs with and without fluorine ion implantation.
Fig. 3.6 Polt of ln[IDS/(VGS−VFB)] versus 1/(VGS−VFB)2 at VDS = 0.1 V and high gate voltage for the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.7 Output characteristics of the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Table 3.1. Electrical characteristics comparison of the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.8 Activation energy versus gate voltage for the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.9 Threshold-voltage rolloff characteristics for the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.10 Threshold-voltage shift over hot-carrier stress time for the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.11 On-current variation over hot-carrier stress time for the fluorine-implanted and control poly-Si Pr2O3 TFTs.
Fig. 3.12 Cross-sectional TEM image of the proposed Pr2O3 gate dielectric TFTs on the CF4 plasma-treated poly-Si film.
Fig. 3.13 Typical C-V characteristic of the Pr2O3 gate-dielectric MOS capacitor. The inset shows the hysteresis characteristic of the Pr2O3 gate dielectric.
Fig. 3.14 Transfer characteristics of the poly-Si Pr2O3 TFTs with various rf powers of CF4
plasma treatments at VDS = 0.1 V.
Fig. 3.15 Transfer characteristics of the poly-Si Pr2O3 TFTs with various rf powers of CF4
plasma treatments at VDS = 1 V.
Table 3.2 Key device parameters for the poly-Si Pr2O3 TFTs with various rf powers of CF4
plasma treatments.
Fig. 3.16 SIMS depth profiles of the fluorine and praseodymium atoms for the poly-Si films with various rf powers of CF4 plasma treatments.
Fig. 3.17 Plot of ln[IDS/(VGS−VFB)] versus 1/(VGS−VFB)2 under strong inversion at VDS = 0.1 V for the poly-Si Pr2O3 TFTs with various rf powers of CF4 plasma treatments.
(a) AFM image of the poly-Si film with rf power of 0-W CF4 plasma treatment (control). The RMS value of the poly-Si surface roughness is 0.25 nm.
.
(b) AFM image of the poly-Si film with rf power of 10-W CF4 plasma treatment. The RMS value of the poly-Si surface roughness is 0.31 nm.
(c) AFM image of the poly-Si film with rf power of 20-W CF4 plasma treatment. The RMS value of the poly-Si surface roughness is 0.47 nm.
Fig. 3.18 AFM images of the poly-Si films with various rf powers of 0-W, 10-W, and 20-W CF4 plasma treatments.
Fig. 3.19 Activation energy (EA) of the poly-Si Pr2O3 TFTs with various rf powers of CF4
plasma treatments.
Fig. 3.20 Threshold-voltage rolloff characteristics of the poly-Si Pr2O3 TFTs with 0-W and 10-W CF4 plasma treatments.
Fig. 3.21 Threshold-voltage shift versus hot-carrier stress time for the poly-Si Pr2O3 TFTs with various rf powers of CF4 plasma treatments.
Fig. 3.22 On-current variation versus hot-carrier stress time for the poly-Si Pr2O3 TFTs with various rf powers of CF4 plasma treatments.
Chapter 4
Effect of Argon-Ion Implant on Solid-Phase Crystallized Polycrystalline Silicon
Thin-Film Transistors
4.1 Introduction
In recent years, polycrystalline silicon thin-film transistors (poly-Si TFT) are widely used for active-matrix liquid crystal displays (AMLCDs) on glass substrates [4.1], [4.2].
However, a difficult technological challenge is to develop high-performance poly-Si TFTs that are useful for both pixel switching elements and peripheral driving circuits [4.3]. To achieve high-performance poly-Si TFTs on inexpensive glass substrate, low-temperature technology is required for realizing flat-panel displays (FPDs) owing to the maximum process temperature of lower than 600 οC. The solid-phase crystallization (SPC) process is widely used for phase transformation from amorphous to polycrystalline due to its low fabrication cost and good grain-size uniformity. However, the electrical characteristics of SPC poly-Si TFTs are strongly dependent on the microstructure of poly-Si film. In particular, the trap states in the poly-Si grains and grain boundaries acted as scattering centers and midgap traps are known to degrade the carrier’s transport properties and increase the off-state leakage current [4.4]-[4.6]. Consequently, reducing these trap states becomes the primary way for achieving high-performance poly-Si TFTs. Hydrogen plasma treatment is a widely used method to passivate the trap states of the poly-Si film and improve the electrical performances of devices in modern TFT manufacturing [4.7], [4.8]. However, the
hydrogenated poly-Si TFTs suffer from a serious reliability issue due to the easily broken of weak Si-H bonds at the grain boundaries. Therefore, the SPC process plays an important role to affect the electrical characteristics of poly-Si TFTs [4.9]-[4.11]. However, the traditional SPC process is an interface-nucleation scheme generating too many nucleation sites at the amorphous silicon/underlying oxide (α-Si/SiO2) interface resulting in a small grain size and a large number of grain-boundary trap states [4.12]-[4.15]. Thus, many efforts have been attempted to increase the grain size and to reduce the trap-state density of the poly-Si film [4.16]-[4.19].
Modified SPC processes with surface-nucleation scheme were proposed to improve the microstructure of poly-Si film by introducing oxygen doping at the α-Si/SiO2 interface [4.16], [4.17]. It has been known that oxygen retards the crystallization process of an oxygen-implanted α-Si film during the solid-phase epitaxial regrowth [4.18]. When the interfacial grain nucleation is effectively suppressed, the grain nucleation process will initiate at another preferable nucleation site on the top free surface of α-Si film [4.16], [4.17].
Because of fewer nucleation sites at the top free surface of α-Si film, the larger grain size of poly-Si could be obtained. However, the oxygen doping during α-Si deposition causes particle contamination issue to possibly affect the electrical characteristics of poly-Si TFTs [4.16], and it also need complicated processes during α-Si deposition [4.17]. Recently, Wu et al. also proposed that retardation of silicon grain nucleation at the α-Si/SiO2 interface could enlarge the grain size of poly-Si [4.19]. The decreased silicon grain nucleation rate could be attributed to that recoiled oxygen atoms from the SiO2 substrate by deep Si implantation will accumulate at the α-Si/SiO2 interface. Among aforesaid processes, an oxygen-rich layer is introduced at the α-Si/SiO2 interface by various methods to verify the grain-size enhancement of poly-Si film, but they have not been successfully adopted for TFT fabrication.
In this chapter, a modified surface-nucleation SPC scheme with the grain-size
enhancement achieved by deep Argon ion implantation is proposed. It is expected that the heavy Argon (atomic weight of 40) ion implantation could induce more recoiled oxygen atoms at the α-Si/SiO2 interface with a lower implantation dosage. Therefore, the crystallinity of SPC poly-Si could be further enhanced, and the performances and reliability of poly-Si TFTs with Argon ion implantation also could be improved.
4.2 Experiments
The schematic diagram of the fabrication processes of the poly-Si TFTs with Argon ion implantation is shown in Fig. 4.1. First, a 100-nm undoped amorphous silicon (α-Si) film was deposited on a 500-nm thermal oxide (SiO2) covered Si wafer by low-pressure chemical vapor deposition (LPCVD) system at 550 οC [Fig. 4.1(a)]. Following, the Argon ions were implanted through the 100-nm α-Si film with the accelerating energy and dosage at 90 keV and 1×1012 cm-2, respectively [Fig. 4.1(b)]. With the 90-keV accelerating energy, the projected range of Argon ions was located beyond the α-Si/thermal SiO2 interface.
Subsequently, the Argon-implanted α-Si layer was recrystallized at 600 οC for 24 h in N2
ambient for phase transformation from amorphous into polycrystalline. After individual active regions were patterned [Fig. 4.1(c)], a 50-nm tetraethylorthosilicate (TEOS) oxide was deposited to serve as the gate dielectric, and a 200-nm poly-Si was deposited and patterned for the gate electrode [Fig. 4.1(d)]. A self-aligned phosphorous ion implantation was preformed to dope the source/drain (S/D) and gate with the dosage and energy of 5× 1015 cm−2 and 40 keV, respectively [Fig. 4.1(e)]. And then, the S/D dopants were activated at 600
οC for 12 h in N2 ambient. Following, a 300-nm passivation SiO2 was deposited by plasma-enhanced CVD (PECVD) system, and then the contact holes were patterned and etched by buffer-oxide etchant (BOE) solution. Aluminum (Al) electrode was deposited and then patterned as metal pads [Fig. 4.1(f)]. Finally, a thermal sintering process was performed
at 350 οC for 30 min. Control poly-Si TFTs without Argon ion implantation were also fabricated for comparison.
4.3 Results and Discussion
4.3.1 Material Analyses
The scanning electron microscopy (SEM) images of solid-phase crystallized (SPC) poly-Si films for the Argon-implanted and control samples after secco etching are shown in Figs. 2.2(a) and 2.2(b), respectively. The SEM images apparently reveal the difference in their grian size between the Argon-implanted and control samples. The average grain sizes of poly-Si for the Argon-implanted and control poly-Si samples are approximately 100 nm and 20 nm, respectively. The enhancement on the silicon grain size is descried as follows.
Because the silicon atoms are bounded to underlying thermal SiO2, the rearrangement and volume contraction of silicon atoms at the beginning of crystallization process would produce a large magnitude of tensile stress at the α-Si/SiO2 interface in the control poly-Si film [4.16]. Many silicon nucleation sites related crystalline defects including microtwins and stacking faults are introduced in order to relieve the tensile stress. Therefore, the grain size of poly-Si obtained from many silicon nucleation sites is rather small. In contrast, in the case of the Argon-implanted poly-Si film, because the interface-nucleation rate is almost suppressed, the stress generated from the surface nucleation is easily relieved from the top free surface. Consequently, the silicon nucleation sites associated with crystalline defects are reduced, resulting in larger silicon grain size and better grain crystallinity in the Argon-implanted poly-Si film.
The x-ray diffraction (XRD) patterns of the Argon-implanted and control poly-Si films after SPC annealing are shown in Fig. 4.3. The SPC poly-Si film has two preferred orientations, the dominant orientation of Si (111) and the other orientation of Si (110),
reported by Aoyama et al. [4.20]. The intensity of the preferred orientation of Si (111) and Si (110) in the Argon-implanted poly-Si film is apparently sharper and higher than that in the control poly-Si film. Therefore, the sharper and higher intensity of XRD peaks proved the crystallinity of poly-Si film in the Argon-implanted sample can be improved compared to that in the control sample. The reason why the Argon-implanted poly-Si film has better crystallinity could be ascribed as following. When heavy Argon ions are implanted through the α-Si film with the projected range located beyond the α-Si/SiO2 interface, many recoiled-oxygen atoms from the SiO2 substrate will accumulate at the α-Si/SiO2 interface.
The presence of recoiled-oxygen atoms is believed to reduce the nucleation sites at the α-Si/SiO2 interface [4.16]- [4.19], which suppresses the interface-nucleation rate of Si atoms, and thereby to result in the nucleation of silicon grain from the top free surface of α-Si layer, called surface-nucleation scheme.
To prove the recoiled-oxygen existing at the α-Si/SiO2 interface, the secondary ion mass spectroscopy (SIMS) analysis is performed. Fig. 4.4 shows the SIMS depth profiles of oxygen atoms for the Argon-implanted and control α-Si films. The SIMS depth profile shows that an oxygen-rich region is observed near at the α-Si/SiO2 interface after the Argon implantation. Consequently, when the interface-nucleation rate is suppressed but the surface-nucleation scheme is dominated, the large silicon grains could be formed after Argon implantation treatment.
4.3.2 Device Characteristics
Typical transfer characteristics of the Argon-implanted and control poly-Si TFTs are shown in Fig. 4.5. The measurements were performed at two drain voltages of VDS = 0.5 V and 5 V, and the drawn channel length (L) and channel width (W) are 10 µm and 10 µm, respectively. The electrical parameters of these devices, including threshold voltage (VTH), field-effect mobility (µFE), and subthreshold swing (S.S.) were extracted at VDS = 0.5 V,
whereas the maximum on current (ION), minimum off current (IOFF), and ON/OFF current ratio (ION/IOFF) were defined at VDS = 5 V. The threshold voltage is defined as the gate voltage required to yield a normalized drain current of IDS = (W/L)×100 nA. The major electrical parameters of these poly-Si TFTs are summarized in Table 4.1. Obvious performance improvements are achieved for the Argon-implanted poly-Si TFTs. The threshold voltage and subthreshold swing of the Argon-implanted poly-Si TFT are 1.73 V and 750 mV/dec, whereas the control poly-Si TFT has the value of 5.75 V and 1290 mV/dec, respectively. The threshold voltage and subthreshold swing of the Argon-implanted poly-Si TFT are found to be superior to those of the control one. Some studies reported that the deep trap states originated from the Si dangling bonds, which have energy states near the middle of the silicon bandgap, would greatly influence the threshold voltage and subthreshold swing [4.21]. The poly-Si film with surface-nucleated scheme can improve the crystallinity of silicon, resulting in decreasing the grain boundaries with decreasing the Si dangling bonds in the poly-Si film. In addition, the leakage current of the Argon-implanted poly-Si TFT was smaller than that of the control one. As is well-known, the traps assisted band-to-band tunneling resulted from the high electric field near the drain junction results in the leakage current [4.22]. The result suggests that fewer grain boundaries exist in the Argon-implanted poly-Si film, and thus the leakage current under a high electric field can be reduced.
Fig. 4.5 also shows the field-effect mobility as a function of gate voltage for the Argon-implanted and control poly-Si TFTs. The field-effect mobility is calculated from the transconductance at VDS = 0.5 V. In Fig. 4.5, the maximum field-effect mobility of the Argon-implanted poly-Si TFT has approximately 74 % improvement compared to that of the control one. Because Argon ion is a noble gas which could not react with Si dangling bonds or contribute any dopant species, the improved performances cannot be ascribed to the Argon passivation effect on the grain-boundary trap states and dopant-induced threshold voltage
Fig. 4.5 also shows the field-effect mobility as a function of gate voltage for the Argon-implanted and control poly-Si TFTs. The field-effect mobility is calculated from the transconductance at VDS = 0.5 V. In Fig. 4.5, the maximum field-effect mobility of the Argon-implanted poly-Si TFT has approximately 74 % improvement compared to that of the control one. Because Argon ion is a noble gas which could not react with Si dangling bonds or contribute any dopant species, the improved performances cannot be ascribed to the Argon passivation effect on the grain-boundary trap states and dopant-induced threshold voltage