In chapter two, two types of analog buffers employing low-temperature polycrystalline silicon thin film transistors are introduced and compared. These are operational amplifier type and source-follower type analog buffers. First, the circuit configuration and operation principle of both the simple structure op-amp buffers and modified op-amp circuits with compensated configuration are described. Next, the conventional source-follower type analog buffer and various compensated source follower circuits are introduced. The advantages and disadvantages of op-amp type and source-follower type analog buffers are compared in the end of this chapter.
In chapter three, the effects of the multi-channel structure on the device uniformity of LTPS TFTs are investigated and discussed. The possible mechanisms of improving uniformity of multi-channel structure are proposed and analyzed according to the experimental results. At last, the multi-channel structure is also introduced to the driving TFT of conventional source-follower type analog buffer to study its influence on circuit performance.
In chapter four, a novel source-follower type analog buffer composed of two n-type thin film transistors, a storage capacitor and four switches is proposed for improving the image quality of displays. An active load is employed to the buffer circuit to suppress the unsaturated phenomenon of output voltage arisen from the significant subthreshold current of driving TFTs. The threshold voltage compensation capability and the elimination of unsaturated output voltage phenomenon of the proposed analog buffer are verified by both the SPICE simulation results and experimental results. The measurement results of offset voltage and output variation of proposed analog buffer are also compared to the
conventional analog buffer circuits. Besides, the effect of bias voltage of active load on the performance of proposed buffer circuits is also discussed in this chapter.
Finally, summary and conclusions is given in chapter five.
Chapter 2
Overview of the Analog Buffer Circuits Using Low-Temperature Polycrystalline Thin Film Transistors
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2.1 Introduction
Researches on “system-on-panel” technology have been attracted much attention at present because it provides a chance to realize a compact, light weight, high reliability, and low cost display system [2.1]-[2.3]. Low-temperature polycrystalline silicon thin film transistor is considered to be the best candidate for carrying out system display due to the low temperature process, high carrier mobility and the compatibility to CMOS technology, which allow the integration of the driver circuit and even more complicated parts such as controller circuits, random access memory (RAM), and central processing unit (CPU) with pixel circuits on a single glass substrate. However, LTPS TFTs suffer from huge device-to-device variation due to the pulse-to-pulse variation of laser energy density and random distribution of grain boundaries, such poor uniformity makes the difficulty to fully integrate driving circuit using LTPS TFTs.
To realize integrating driving circuits using LTPS TFTs, output buffers are indispensable for the data driver to drive the large load capacitance of data lines. However, the poor uniformity of LTPS TFTs leads to the non-uniformity of buffer output voltage
across the panel which results in the wrong image displaying. Therefore, many researches employing LTPS TFTs have been tried to carry out analog buffers with high immunity of the device variations [2.4]-[2.17].
Analog buffer circuits using LTPS TFTs are classified into operational amplifier type (op-amp type) analog buffer and source-follower-type analog buffers according to their circuit architecture. Operational amplifier is most commonly used as the output buffer in single crystal silicon integrated circuits. However, the complicated circuit configuration and the huge output voltage variation of op-amp-type analog buffer using LTPS TFT make it not suitable for system-on-panel application. Source-follower-type analog buffer is considered a better candidate because of its simplicity and higher immunity to the device variations of LTPS TFT.
In this chapter, the circuit configuration, operating sequence, advantages and disadvantages of these two types of LTPS TFT analog buffers circuits are introduced. Those analog buffer circuits are simply classified into various types as shown in Fig. 2.1 based on the compensated methods [2.4]-[2.19]. The compensation principles of different types with configuration will be described in detail in this chapter. Furthermore, the output characteristics of the op-amp type analog buffer circuits and source-follower type analog buffer circuits are also discussed in this chapter.
Fig. 2.1. Classification of compensation method for LTPS TFT analog buffer.
2.1.1 Architecture of AMLCD Driver
The block diagram of AMLCD display panel is shown in Fig. 2.2. The periphery circuits blocks of LCD panel are composed of scan driver, data driver, timing controller, DC/DC converter, gamma reference voltage driver, common voltage driver (Vcom driver).
The timing controller decodes the output waveform to generate control signals at corresponding time, which is responsible for controlling the behavior of scan driver and transmitting the RGB (red, green, and blue) signals to the data driver. A DC-DC converter steps up a single externally supplied voltage to various higher level voltages (ex. VDD to 2VDD, 3VDD positive output voltage, and -2VDD, -3VDD negative output voltage) which provide the power supply voltage to the timing controller, interface circuit, source driver, gate driver, reference voltage driver and common voltage driver [2.20]-[2.21]. The gamma reference voltage driver is used to provide the various gamma reference voltages to the digital-to-analog converter (DAC) circuits. The common voltage driver is used to provide the common electrode voltage for the panel. Besides, the scan driver and data driver will be further discussed in the following.
z Scan Driver
The scan drivers generate the scan pattern and turn on each scan line sequentially. The architecture of source driver is shown in Fig. 2.3. It consists of shifter register, level shifter, and output buffer. The shift register is used to store digital input signal and transit them to the next stage, which generates sequential scan pulse for scan line according to the timing clock. The function of the level shifter is to translate the digital signal to a higher level voltage because the higher voltage is needed to turn on the switch element of the active pixel. Since the scan lines can be modeled as RC (resister and capacitor) ladder, the output
buffer is indispensable to drive the RC loading.
z Data driver
Fig. 2.4 shows the architecture of data driver which mainly contains shifter register, data register, level shifter, digital to analog converter (DAC) and output buffer. The first three stages are categorized as digital part, and the other two stages are belonged to analog part. The shift register generates pulse signal for video signal sampling according to the clock signal and transmit the pulse digital RBG signals to the next stage [2.22]. The data register receives the serial data signal and transmits them in parallel. The function of the level shifter is the same as the one used in the scan driver. It is applied to converter the digital RGB signal to a higher level voltage for data driver [2.23]. Because the data signal is transmitted in the digital interface, the digital to analog converter (DAC) is needed to convert the digital RGB video data into analog data signal for displaying the gray level [2.24]-[2.25]. Finally, the selected video data is transmitted to the data line after changing impedance in the output buffer. The purpose of output buffer is to assure the active pixels can be driven into a desired gray level. When the digital to analog converter is insufficient for driving the large loading of data line, the output buffer is used to enhance its driving capability. As the output buffer is applied, the DAC will charge a smaller loading of output buffer instead of a larger loading of data line. Thus, the desired data signal can be transmitted to the active area accurately. Because the LCD panel usually has large loading, especially in larger panel or higher resolution display, the analog buffer is indispensable to drive the large loading of the data lines.
Fig. 2.2. Block diagram of display panel.
Fig. 2.3. Architecture of the scan driver.
Scan Driver
TFTFig. 2.4. Architecture of the data driver.
2.1.2 Design Considerations for LTPS-TFTs Analog Buffer
To design the output buffer for the data driver of flat pane display, there are several critical issues to be considered. These include output voltage accuracy, driving capability, layout area, and power consumption.
(1) Output voltage accuracy: Analog buffer is applied to the data driver for ensuring that the data signal outputted from DAC can be transmitted exactly to the active pixel. Thus, the high output voltage accuracy of analog buffer circuits is required to display the desired gray level correctly.
(2) Driving capability: The output settling time for the data drivers must be fast enough to quickly transfer the data signals into the pixels within a line time. Therefore, the analog buffers in the end of data driver must quickly charge or discharge the load capacitance of data bus. Especially in the larger panel area and higher resolution display, the line time becomes shorter while the loading of data line is large. High driving capability of the output buffer is needed to achieve fast transition time and to get sufficient capability for driving large loading of data lines.
(3) Layout area: For the LAAT (line at a time) driving architecture, one analog buffer is needed for each column line. Thus, several hundreds of analog buffers are needed in active matrix display. As the resolution is higher and higher in the future, the amount of analog buffers is increasing and larger area will be occupied. Moreover, a data driver should fit in one pixel pitch, and circuit layout area is limited. Therefore, the simple configuration and less transistors are pursued for high-resolution display.
(4) Power consumption: The power consumption of poly-Si TFT integrated circuits tends to be higher than that of single-crystalline silicon ICs because of inferior electrical characteristics of poly-Si TFT such as higher threshold voltage, lower carrier mobility. For the expanding market of mobile and portable production, the demand of power dissipation is increasing. Since several hundreds of analog buffers are needed in the LAAT (line at a time) driving architecture, large static power is dissipated of analog buffers. Therefore, it needs to design an analog buffer with low power consumption.
2.2 Op-amp-type Analog Buffer
2.2.1 Typical Op-amp-type Analog Buffer
Operational amplifier (op-amp) is generally connected as an unit-gain buffer to act as the output buffer in the single crystal silicon LSIs. A typical two-stage operational amplifier (op-amp) is composed of a differential amplifier and an output stage as shown in Fig. 2.5.
Fig. 2.5. Simple two-stage op-amp unit gain buffer.
The output voltage versus input voltage characteristic and output offset voltage of a typical two-stage op-amp unit-gain buffer employing LTPS TFTs are shown in Fig. 2.6, where the offset voltage is defined as the difference between the input voltage and output
voltage, (i.e. Voffset=Vinput -Voutput ). The simulation result shows the good linearity of the op-amp unit-gain buffer. The output offset voltage is average under 30 mV expect when the input voltage is in low level where the offset voltage may exceed 150mV.
Fig. 2.6. Simulation result of the offset and output voltage versus input data voltage for typical two-stage op-amp type analog buffer circuit.
Although the output error of the typical op-amp type analog buffer is small, huge output voltage variation may exist in this circuit because of the inevitable non-uniformity of the poly-Si TFTs electrical characteristics, such as threshold voltage and mobility variations.
In order to study the effect of device non-uniformity on the circuit performance, Monte Carlo simulation with an assumption of normal distribution is introduced where the mean value and deviation of the threshold voltage and the mobility are 1.45V, 0.5V and 65.69 cm2/V-sec, 15 cm2/V-sec, respectively. Each poly-Si TFTs are assumed to vary independently when the Monte Carlo simulation is executed. Fig. 2.7 shows the Monte Carlo simulation results of the two-stage op-amp unit gain buffer. It is obvious that the
output voltage has huge variations, where the variation of output offset voltage may get up to 1450mV. This serious output variation makes it difficult to design a high performance output buffer with the typical op-amp-type analog buffer. Therefore, some compensating methods have been proposed to solve this problem. These compensating methods for op-amp type analog buffer will be discussed in the next section.
Fig. 2.7. Monte Carlo Simulation result of the typical op-amp-type analog buffer with input voltage varying from 1V to 6V.
2.2.2 Op-amp-type Analog Buffer with Compensated Architecture
The compensating methods for device-to-device variation of LTPS-TFTS op-amp-type analog buffer can be mainly classified into two kinds including differential pair compensated method and bias circuit compensated method. The concepts and operating method of these two kinds of compensating circuits will be discussed in detail.
2.2.2.1 Differential Pair Compensated Method
For the differential pair compensated method, an additional capacitor is used to compensate the device mismatch of the differential pair stage. The operating period usually includes two stages. First is the period to calibrate the electrical properties mismatch of the differential pair and the second stage is the signal data voltage programming period. Fig. 2.8 shows an example of this type of compensating method. The op-amp-type unit gain buffer with threshold voltage and mobility deviation-free differential amplifier was reported by Itou [2.4]. Comparing to the typical two-stage op-amp type analog buffer, one capacitor and three switches are added to the differential pair stage. The operating period including two stages: first is the calibration mode, and second is the operation mode.
Fig. 2.8. Circuit configuration and timing diagram of Itou’s differential amplifier compensated op-amp-type unit gain buffer.
In the calibration mode, switches S1 and S2 are on, and S3 is off. At this time, the two input voltages of the differential pair (MP1, MP2) are the same, and the difference of gate to source voltages between the active load pair (MN3, MN4) is stored in the capacitance C1.
The gate voltage of the active load is corresponding with the threshold voltage of the differential pair and the active load. Therefore, the differential pair mismatch and the load pair mismatch are stored in the capacitance C1. When the switches S1 and S2 are off, and S3 is on, the circuit is in the operation mode. In this mode, the input data is transmitted to the output stage. Since the differential pair mismatch and the load pair mismatch have been recorded in the first stage, the input offset resulting from device mismatches can be fully canceled in the operation mode. Thus, the final output voltage will be close to the input data signal in this buffer circuits.
Fig. 2.9. Simulation result of the offset and output voltage versus input data voltage for Itou’s differential pair compensated op-amp-type analog buffer circuit.
The output performance of Itou’s op-amp analog buffer has been studied by simulation results. Fig. 2.9 shows the output voltage-input voltage characteristic and the output offset of the buffer. The output deviation is small except in low input data signal. The Monte Carlo
simulation result is also shown in Fig. 2.10. It is obvious that the output offset variation of this buffer circuits is much smaller than that of the typical two-stage op-amp-type analog buffer. However, the output variation still remains large (~550mV) in low input data level. It is because that when the input data is in low level, the two transistors of the differential pair (MP1, MP2) operate in the linear region. Thus, the transconductance (gm) of two transistors of the differential pair are not kept in constant which result to the differential pair mismatch and the load pair mismatch cannot be recorded accurately in the capacitance C1 and result in the output performance sensitive to the device variation. Besides, the mismatch of the output stage of the analog buffer also contributes to the output variation of the Itou’s op-amp-type analog buffer.
Fig. 2.10. Monte Carlo Simulation result of the Itou’s op-amp-type analog buffer with input voltage varying from1V to 6V.
2.2.2.2 Bias Circuit Compensated Method
In the bias circuit compensated method, a threshold voltage insensitive gate bias
voltage generating circuit is applied to eliminate the influence of threshold voltage variation on the bias current. Fig. 2.11 shows an example of op-amp-type analog buffer using this compensating method [2.7]. This buffer circuit is composed of a typical two-stage op-amp unit gain buffer and the threshold voltage insensitive gate bias generating voltage.
Vg
Fig. 2.11. Circuit configuration and timing diagram of Yiu’s bias circuit compensated op-amp-type unit gain buffer.
The bias current of this op-amp can be expressed as :
2
d o x 5 _ 5 _
I 1 C ( ) (
2 M N g s M N t h M N
W V V 5)
μ L
= − (2.1)
When there is large variation in threshold voltage that will causes bias current variation, thus the variation of gm (transconductance). This in turn causes the non-uniformity of the buffer circuit characteristics across the panel. Therefore, eliminating the effect of threshold voltage variation on bias current may maintain the output characteristics of the op-amp unit-gain buffer. Thus, Yiu propose a gate voltage biasing circuit to provide an insensitive bias gate voltage Vg, (refer to Figure. 2.10) for biasing the transistors. The operation of this
compensating circuit is described in the following. In the first stage, the transistor M1 turns on, and the capacitor will be charged up to Vref. Then transistor M1 turns off and transistor M2 turns on to connect the capacitor to transistor M3. Since transistor M3 is connected like a diode, it will discharge the capacitor until the gate voltage of the transistor M3 is equal to Vbias + Vth. Then this voltage is applied to the gate of MN5, MN6 to provide the bias
The bias current will be independent of the threshold voltage of the transistor if the transistor MN3, MN5 and MN6 are matched. Therefore, the output non-uniformity of the op-amp type analog buffer resulting from the bias current fluctuation can be eliminated in this compensating circuit architecture.
Fig. 2.12 and Fig. 2.13 show the simulation results of the output offset voltage and the output variation versus input data voltage, respectively. It is clear that large output variation still remains in this compensating circuit. It means that the electrical performance variations can not be calibrated out in this compensating architecture. It is because that the compensating method is performed in the bias circuits but not the differential pair. Even if the bias current mismatch has been compensated, the device mismatch of the differential pair and the active load pair which are the mainly causes of output variation for op-amp-type unit gain buffer still remain. Besides, the compensating configuration will
work effectively only when the electrical characteristic MN3, MN5 and MN6 are matched, but it is very difficult to achieve completely device matched between transistors. In addition to large output variation, extra setup time is also required for the application of this buffer circuit to generate the threshold voltage insensitive bias voltage. Furthermore, op-amp-type
work effectively only when the electrical characteristic MN3, MN5 and MN6 are matched, but it is very difficult to achieve completely device matched between transistors. In addition to large output variation, extra setup time is also required for the application of this buffer circuit to generate the threshold voltage insensitive bias voltage. Furthermore, op-amp-type