Output Voltage Unsaturated Phenomenon of Conventional Source-Follower

4.2 Output Voltage Unsaturated and Distribution

Phenomenon of Source-Follower Type Analog Buffer

In order to investigate the output performance of the source-follower type analog buffer, HSPICE circuit simulator was introduced. In this work, the typical model of the poly-Si TFTs for simulation is expressed by the PRI parameters. The device parameters such as threshold voltage and mobility are 1.45V and 65.69cm²/V-sec for n-type TFTs, and -0.99V and 61.51cm²/V-sec for p-type TFTs. The load capacitance of data line is assumed 20pF which corresponds to a 2-inch QVGA LCD.

4.2.1 Output Voltage Unsaturated Phenomenon of

Conventional Source-Follower Type Analog Buffer

A conventional source follower and its output waveform are shown in Fig. 4.1 and Fig.

4.2, respectively. In theory, the output voltage of a source follower will reach to input voltage minus the threshold voltage of the transistor (Vout=Vin-Vth) according to the turn-on characteristic of transistors. However, from the output waveform shown in Fig 4.2, it is clear that the final output voltage of the source follower is not kept constant, but exceeds the target voltage of Vin-Vth with time. This is mainly caused by the large subthreshold current of poly- Si TFTs. As model used in this work, the sub-threshold swing of LTPS TFTs is about 0.3V/dec that is much larger than MOSFETs’ (0.06V/dec). When the output voltage approach the target voltage, the source follower will operate in the subthreshold region and large subthreshold current will keep charging the load capacitance. Consequently, the output voltage will be sensitive to the charging time. This problem makes the difficulty in buffer circuits designing for various product specifications with a source follower structure.

In order to eliminate this output unsaturated phenomenon, an active load is added to the source follower. The source follower with an active load and its output waveform simulating result are shown in Fig. 4.3. It is obvious that the unsaturated phenomenon of the output voltage is suppressed and the final output voltage nearly kept constant. In this circuit, the active load plays the role of a constant current source which provides a leaking path for subthreshold current of the driving TFT. Therefore, the output voltage will not be charged up by the subthreshold current and then keeps constant with charging time. The offset voltage (i.e.

offset voltage=Vin-Vout) versus input voltage (Vin) of conventional source follower and source follower with active load with different charging time are shown in Fig. 4.4. It is clear that the offset voltage of the conventional source follower varies with different charging time.

On the contrary, the offset voltage of the source follower with an active load is almost the same in different charging time. It means that adding the active load can solve the unsaturated phenomenon of the output voltage successfully. Although the output offset voltage of source follower with active load is larger than that of conventional source follower, it can be

eliminated by gamma correction [4.19]. According to the results, the structure of source follower with active load has high charging time variation-tolerant and is suitable for LTPS-TFTs buffer circuit design with source-follower-type configuration.

Fig. 4.1. Conventional source-follower type analog buffer.

Fig. 4.2. Simulating output waveform of conventional source-follower type analog buffer.

Fig. 4.3. Schematic of conventional source follower with an active load and its output waveform simulating results.

Fig. 4.4. Offset voltage comparison of conventional source follower and source follower with an active load in various charging time.

4.2.2 Output Voltage Distributed Phenomenon of Source-Follower Type Analog Buffer

In additional to the output unsaturated phenomenon of conventional source follower, the large output voltage variation resulting from the electrical characteristic variations of LTPS-TFTs such as threshold voltage variation, carrier mobility variation, and subthreshold swing variations is another serious problem needed to be solved in LTPS-TFTs analog buffer circuits. Fig. 4.5 shows the cumulative distributions of the device parameters from 30 n-channel LTPS TFTs fabricated on the same glass substrate. It is obvious that there is a large variation in the electrical characteristics of LTPS TFTs between transistors over the substrate glass. Such huge device-to-device variation will cause the output voltage distributed phenomenon of the source follower and lead to the wrong gray scale.

To study the effect of the device variation on the circuit performance, Monte Carlo simulation with an assumption of normal distribution as shown in Fig. 4.6 is executed, where the mean value and the deviation of the threshold voltage and mobility are 1.45V, 0.5V and 65.69cm²/V-sec, 15cm2/v.s, respectively. Fig. 4.7 shows the twenty times Monte Carlo simulation results of the conventional source follower with active load when input voltage are 2V, 3V, and 4V. It can be seen obviously that huge output voltage variations resulting from the LTPS TFTs device variation still exist in this circuit. Therefore, an effective compensating configuration is required to develop an analog buffer with high immunity to the device variation in TFTs.

Fig. 4.5. Cumulative distributions of the device parameters from 30 n-channel LTPS TFTS fabricated on the same glass substrate.

Fig. 4.6. The diagram of the assumption for Monte Carlo Simulation.

Fig. 4.7. Twenty times of Monte Carlo simulation results of the conventional source follower with an active load when input voltage 2V to 4V

4.3 Proposed Source-follower Type Analog Buffer

Since the conventional source-follower-type analog buffer suffers from large output voltage variation due to the inevitable non-uniformity of the poly-Si TFTs electrical characteristics as discussed previously. A new source-follower-type analog buffer is proposed in this article for compensating the device variations in LTPS TFTs.

Table 4.1 shows the schematic of the proposed analog buffer which is composed of two n-type thin film transistors, one storage capacitor and four switches. The design parameters of the proposed analog buffer are also shown in Fig. 4.9. The roles of these two NTFT are the driving TFT and the active load, respectively. The driving TFT is to provide the data voltage to charging the data line loading. Thus the large W/L ratio is designed for high driving capability consideration. The active load is used to as a constant current source to eliminate

the output unsaturated phenomenon of source follower and thus large channel length is chosen to minimize the kink effect. The gate terminal of the active load is bias with a constant voltage Vbias. The capacitor is supplied to compensate the device variation of driving TFT through the concept of self-compensation method which has been described in chapter 2. And in this work, the load capacitance of data line is assumed to be 20pF which corresponds to a 2-inch QVGA LCD.

The operation scheme and compensation principle of the compensating buffer circuit are described as follows.

(1) Compensation period:

During the first operating period, SW1 and SW2 are closed, and SW3 and SW4 are opened. Thus, the compensation is executed from the constant voltage source Vdd, and a voltage drop ΔV corresponding to the threshold voltage of driving TFT, the threshold voltage of the active load, and the bias voltage is stored in the capacitance Cvt.

(2) Data input period:

After the compensation period was executed, SW1 and SW2 are opened, and SW3 and SW4 are closed. The input data is then applied to one terminal of the storage capacitor to enter the data input period. Because of the gate to source voltage (VGS) of the driving TFT is hold in the value of ΔV, the gate voltage of the driving TFT becomes the input voltage added to ΔV. Thereby, the output voltage will be equal to input data voltage, Vout=Vin+ΔV-ΔV=Vin.

Consequently, the output voltage will be independent of the threshold voltage and the carrier mobility of the driving TFT and the device variation can be compensated through the capacitor and the operating sequence.

Fig.4.8. Schematic and the timing diagram of the proposed source-follower-type analog buffer.

Tab 4.1. Design parameters of the proposed source-follower-type analog buffer.

4.4 Simulation and Measurement Results of the Proposed

Analog Buffer

In this section, the output performance of the proposed analog buffer is studied and verified through both the circuit simulation and experiment. In the circuit simulation, HSPICE circuit simulator was performed. The typical model of the poly-Si TFTs for simulation is expressed by the PRI parameters. The device parameters such as threshold voltage and mobility are 1.45V and 65.69cm²/V-sec for n-type TFTs, and -0.99V and 61.51cm²/V-sec for p-type TFTs. The load capacitance of data line is assumed 20pF which corresponds to a 2-inch QVGA LCD.

4.4.1 Simulation Results and Discussion

In this work, Monte Carlo simulation is executed to study the effect of the device variation on the proposed circuit design, where the simulation condition is the same as that used in section 4.2.2. Fig. 4.9 shows the twenty times Monte Carlo simulation result of the output waveform of the proposed analog buffer when input voltage is 2V, 3V, and 4V.

Compared to the simulating result of the source follower with active load shown in Fig. 4.7, it is clear that the output variation decrease drastically. The output voltage variation of the conventional source follower with active load is larger than 500mV, while that of the proposed analog buffer is commonly smaller than 25mV regardless of the large variation of LTPS-TFTs characteristics. It verifies that the device variation of LTPS TFTs can be compensated successfully by the proposed analog buffer.

Fig.4.9. Monte Carlo Simulation output waveform of the proposed analog buffer when input voltage is 2V, 3V, 4V.

4.4.2 Fabrication Process and Measurement Result of the Proposed Analog Buffer

In addition to circuit simulation, the proposed analog buffer is also fabricated and measured to study its output performance after buffer circuit design finished. The testing buffer circuits were fabricated using a LTPS CMOS process. The fabrication process is described as follows. A buffer oxide and 500Å-thick a-Si was first deposited on the glass substrate sequentially. Then the amorphous silicon thin film was crystallized to poly-crystalline silicon film by KrF excimer laser annealing at room temperature. After the active region was defined, the channel doping was carried out for adjusting the threshold voltage of n-type TFT. Then, high dose ion implantation was executed to source/drain regions of n-type TFT. Next, 1000 Å-thick gate oxide was deposited by plasma enhanced chemical

vapor deposition (PECVD). A 3000Å-thick Cr film was deposited next. Then, the gate oxide and the Cr film were etched to form the gate electrode. Next, a high dose self-aligned ion implantation was executed to form source/drain regions of p-type TFT. Then a 4000Å-thick SiNx was deposited by PECVD as interlayer. Finally, the test circuits for the proposed analog buffer were accomplished after the contact holes formation and the 4000Å-thick Cr metallization. The image of optical micrograph of the proposed analog buffer circuit is shown in Fig. 4.10.

The measurement system for these testing buffer circuits is shown in Fig. 4.11. It includes four units: (1) Agilent 4156C including probe station and parameter analyzer, (2) HP 41501A pulse generator for providing control signal pulse, (3) Keithley 617 programmable electrometer for supplying one DC signal voltage through an additional probe, (4) Agilent MSO6034A mixed signal oscilloscope to display the output signal through the coaxial cable and BNC connection.

Fig. 4.10. Optical micrograph of the proposed analog buffer circuit.

Fig. 4.11. Measurement system for the testing buffer circuits.

After measurement system is ready for measuring, several testing buffer circuits of the proposed analog buffer and conventional source follower were measured. Fig.4.12 shows the measurement result of the offset voltage compared between the proposed analog buffer and the conventional analog buffer with input voltage varying from 1V to 6V. It is observed that output voltage of the proposed analog buffer is very closely to the actual input voltage. The maximum offset voltage of the proposed buffer is about 160mV which is much less than the large offset voltage (>1V) of the conventional analog buffer. In order to study the variation toleration of the proposed buffer, eight set of the buffer circuits are measured to gather statistics. The measured result shows that the conventional analog buffer suffers from large output offset variation as shown in Fig.4.13. On the other hand, the output offset variation of the proposed analog buffer is much smaller than that of the conventional analog buffer. It is evident that the proposed analog buffer can compensate the device-to-device variations of LTPS TFTs successfully.

Fig.4.12. Measurement result of the offset voltage compared between the proposed analog buffer and the conventional analog buffer.

Fig.4.13. Offset voltage variation of 8 set of the analog buffer circuits are compared between the proposed analog buffer and the conventional analog buffer.

4.5 Bias Voltage Effect Discussion

The bias voltage of the active load is considered to be a factor that may affect the performance of the proposed analog buffer. The value of the bias voltage will determine the operation region of the active load, and the operation mode of the driving TFT and the active load in two operating period will affect the output characteristic due to the different output resistance of transistor in these two operation mode. Thus, in this section we will discuss the bias effect of the proposed analog buffer in detail.

First, the circuit simulation is executed to investigate how the bias voltage affects the output performance. Fig.4.14. shows the simulation result of the offset voltage and the power dissipation for the proposed analog buffer with bias voltage varying from 1.5V to 9.5V when input data voltage is 3V. It shows that the offset voltage defined as Vin minis Vout turns from positive to negative value as bias voltage increasing, and a minimum value of the offset voltage exists as the bias voltage is in the range between 2V to 2.5V. The tendency can be understood by the detailed discussion on the operation of driving TFT and the active load.

During the first compensation period, the driving TFT is in the saturation region because of the diode connected configuration and the active load is also operated in the saturation region.

However, during the data input period, the active load may operate in the saturation or the linear region depending on the bias voltage while the driving TFT still work in the saturation region.

Fig.4.14. Simulation result of the output offset voltage and the power dissipation for the proposed analog buffer with different bias voltage.

These can be divided into two conditions for discussing. In the following, we will discuss these two conditions in detail by the mathematical analysis. Here the driving TFT is assumed to TFT1 and active load is TFT2 for convenience.

A. Driving TFT in saturation region, active load in saturation region at the data input period

2 From equation (4.6), it is observed that the threshold voltage and carrier mobility variations of driving TFT and the active load both can be stored in the capacitor for the compensation during the compensation period. Therefore, the output voltage will be in theoretically equal to the input voltage independent of the threshold voltage and the carrier mobility of the driving TFT and active load as shows in equation (4.10).

B. Driving TFT in saturation region, active load in linear region at the data input period (1)Compensation period:

During the first operation period, the driving TFT and the active load will always work in the saturation region as the bias voltage is smaller than Vdd. Therefore, the situation in this condition during the compensation period is the same as described previously. In which the voltage stored in the capacitor is corresponding to the threshold voltage of driving TFT and active load, bias voltage and the K1/K2 ratio.

(2)Data input period:

2 2

(A) term can be simplified to:

2 2

2 2 2 2 2 2

Therefore, the output voltage can be simplified as

2 2 Equation (4.21) indicates that the output voltage will larger than the input voltage because that the bias voltage must be higher than the threshold voltage of the active load to turn on the active load. Therefore, we know that if the active load works in the linear region at the data input period, the output voltage will exceed the input data and thus a negative offset voltage is obtained. This situation will happen when the bias voltage is higher than the input voltage. Corresponding to the simulation result shown in Fig.4.14, it is obvious that the output offset voltage is the negative value as the bias voltage larger than the input voltage because the active load is in the linear region. Nevertheless, as the bias voltage is lower than the input voltage, the active load will operate in the saturation region and the output voltage is very closely to the input data voltage as expressed in equation (4.10).

In addition, an important information can be obtained from equation (4.21). It tells us that the output voltage can be almost equal to the input voltage when the Vbias is chosen to a lower value but just slightly above V_TH2 and the large factor “a” is designed. The factor “a” is

related to the mobility and the W/L ratio of the driving TFT and the active load as represented in equation (4.3). Because of the mobility of the driving TFT and the active load are almost the same. Larger W/L ratio of the driving TFT and smaller W/L ratio of the active load were designed to possess large “a” factor which coincides with previously design in section 4.3.

The output voltage is accurate as the factor “a” is larger. However, the optimum value in designing is required to meet the specifications of display.

Furthermore, from the mathematical analysis of bias voltage effect, we can see that the proposed analog buffer circuit can compensate not only the variations of the driving TFT but also the variations of the active load. In additional to the electrical characteristic variations, the issue of TFTs reliability is also taken into consideration in this discussion. In comparison with a-Si TFTs, LTPS TFTs have better long term reliability. For example, after 1000sec DC stress with Vg=7V and Vd=14V, the threshold voltage variation is about 0.5V and the degradation of carrier mobility is about 4% [4.20]. Moreover, the gate voltage of the active load is designed to be 2V in our proposed analog buffer which is in the very low voltage level.

Therefore, it is almost no degradation of the active load in this bias condition and no apparent influence on the output performance will be seen in the proposed analog buffer circuit.

In additional to simulation result, the analog buffer circuits were also measured to study the bias effect. The measurement result is compared to the simulation result when input voltage 3V as shown in Fig.4.15. It is clear that the relationship between the offset voltage and the bias voltage of measurement result shows the same tendency with the simulation result. The simulation and measured result when input voltage 2V is also shown in Fig.4.16, and the same trend exhibited. According to the simulation and measured results, an optimum value of the bias voltage can be chosen to get the minimum output offset voltage. Furthermore, the power dissipation related to the bias voltage shown in Fig.4.14 exhibit that the power

In additional to simulation result, the analog buffer circuits were also measured to study the bias effect. The measurement result is compared to the simulation result when input voltage 3V as shown in Fig.4.15. It is clear that the relationship between the offset voltage and the bias voltage of measurement result shows the same tendency with the simulation result. The simulation and measured result when input voltage 2V is also shown in Fig.4.16, and the same trend exhibited. According to the simulation and measured results, an optimum value of the bias voltage can be chosen to get the minimum output offset voltage. Furthermore, the power dissipation related to the bias voltage shown in Fig.4.14 exhibit that the power