Current Type

Fig. 2.28 shows the circuit configuration and the timing diagram of one example of current type compensating buffer circuit, which is proposed by C. Yoo in 2005 [2.17]. It consists of a pair of nMOS and pMOS TFTs, four control switches and a storing capacitor.

The operating concept of this buffer circuit is as follows. During the input signal sampling period, the switches S1 and S3 are turned on while the others are open. Since the drain

currents of M1 and M2 are equal. The gate to source voltage of M2 is established and stored on the capacitor as the gate voltage of M1 is equal to Vin. The switches S1 and S3 are then open, and switches S2 and S4 are turned on to enter the driving period. The drain current of M1 and M2 are the same during this period. Because the gate to source voltage of M2 is determined and stored in the storage capacitor at the input signal sampling period, the drain current of M2 during the driving period is the same as that during the input signal sampling period and so dose the drain currents of M1. It means that the gate to source voltage of M1 should also be equal during both periods. Therefore, the output voltage is the same as the input voltage regardless of the threshold voltage and mobility of the N-type and P-type TFTs.

Fig. 2.28. Circuit configuration and timing diagrams of Yoo’s current type analog buffer.

Fig. 2.29. Simulation result of the output voltage and output offset voltage versus input voltage of Yoo’s analog buffer.

Fig. 2.30. Monte Carlo simulation result of the output offset voltage of Jung’s analog buffer.

Fig. 2.29 and Fig. 2.30 show the output characteristics including the output offset voltage and the output variations of this analog buffer circuit. It shows the output offset

voltage still large in this compensating circuit. The main source of the error in the output voltage is the small output resistance of the transistors. The output resistance in the saturation region of the poly-Si TFT is much smaller than that of the single-crystalline Si MOSFETs. Owing to the small output resistance of poly-Si TFTs, the current levels during the sampling and driving periods may be different which results in the invalidity of this compensating method.

2.4 Comparisons of Several Op-amp-type and Source-follower Type Analog Buffer Circuits

In this section, the comparisons between several op-amp-type analog buffers and source-follower type analog buffers including the output performance, circuit configuration, and power dissipation are discussed. These data are shown in Table 2.1.

z From the aspect of output performance

Table 2.1 shows the output offset deviation and output offset variation of three op-amp type analog buffers and three source-follower type analog buffers. The output offset deviation is defined as the difference between the average value and the extreme value of output offset voltage with input signal varying from 1V to 5V. The output offset variation is referred to the maximum value minus the minimum value of the offset voltage in a given input voltage. The simulation results show that op-amp-type analog buffers have better linearity of input-output characteristics while suffering from serious output variations due to device-to-device variations of LTPS TFTs. Effective compensation can be achieved by the differential-pair compensated method while compensation in bias circuit seems less

efficiency. This is because that the differential-pair mismatch is the primary source of output variations in op-amp-type analog buffers. On the contrary, source-follower type analog buffers show higher immunity to the device variation. The output variation can be reduced effectively with self-compensation method through the storage capacitor. However, large variations still exist in the compensating circuit with the concept of matching TFTs. Because the assumption that device characteristic of one transistor matches another completely on the same glass substrate is very difficult to achieve. Therefore, it is considered that self-compensation method by a storage capacitor is the best compensating method for source-follower-type analog buffers.

z From the aspect of circuit configuration

Form Table 2.1, it is clear that op-amp-type analog buffer needs many transistors which will occupy large area. On the contrary, because of the simple configuration, source-follower-type analog buffers need fewer transistors than op-amp-type analog buffers.

The advantage of simple configuration makes source-follower type analog buffer more suitable for high resolution display application.

z From the aspect of power dissipation

It is obvious that the power dissipation of source-follower type analog buffers is much smaller than that of op-amp type analog buffers. Depending on the simulation results, the power dissipation of op-amp-type analog buffer is ten times or even larger than that of source-follower-type analog buffer when input voltage is 4V. Since several hundreds of analog buffers are needed in the LAAT (line-at a-time) driving architecture, vast power will be dissipated by analog buffers employing op-amp. Therefore, source-follower type analog

buffer is the better choice for SOP application in consideration of low power consumption.

Table 2.1 Comparison of several op-amp-type and source-follower type analog buffers.

2.5 Summary and Conclusion

Several kinds of analog buffer circuits using LTPS TFTs are introduced with the circuit configuration and the compensation concepts. These analog buffer circuits are classified into operational amplifier type (op-amp-type) analog buffer and source-follower type analog buffers according to their circuit architecture and divided into six major compensating methods. These compensating architectures of analog buffer circuits are necessary owing to the electrical characteristic variation of the transistors resulting from the pulse-to-pulse variations of laser energy density and random distribution of grain boundaries. Each kind of circuit compensating method has its own advantages and disadvantages as discussed in section 2.4. In conclusion, the source-follower type analog buffer with simple configuration,

better immunity to the LTPS TFTs device variation, and lower power dissipation is considered to be the best candidate for system-on-panel applications.

Chapter 3

The Effect of Multi-channel Structure on Low-Temperature Polycrystalline Silicon Thin Film Transistors

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3.1 Introduction

Recently, fast growing market of system-on-panel (SOP) for flat-panel display has pressed the development of Low-temperature poly-Si TFT to higher performance, higher uniformity, and higher reliability. It is well known that the key to obtain high performance poly-Si TFT is the crystallization of a-Si thin films. Large grain size and less grain boundaries and trap states of the poly-Si film are the main requirement in the poly-Si crystallization process. Among the many researches of the crystalline methods, the excimer laser crystallization (ELC) is considered to be the most promising approach to get high performance of the transistors at present [3.1]-[3.2]. However, due to the narrow process window of the laser energy density for producing large grain of poly-Si thin film in SLG regime, the laser energy density must be precisely controlled. Unfortunately, laser energy density varies randomly in space, and differs from pulse to pulse, which will cause the non-uniform grain size distribution and thus the non-uniform trap states across the substrate.

Thus, when the devices were fabricated on the substrate, large difference of trap states densities may exist between transistors. Trap states of the poly-Si thin film exert a profound

influence on device characteristics. It is well understood that the threshold voltage and subthreshold swing are strongly influenced by the density of dangling-bond midgap states which are thought to originate mainly from dangling bonds in grain boundaries, while the field-effect mobility and leakage current are related to the strain-bond tail states which may mainly come from the intragranular defects [3.3]-[3.5]. Hence, there are large device characteristics variations of LTPS TFTs between transistors. It is very undesirable for device applications.

To achieve the goal of system-on-panel, the improvements are required to solve this problem of device-to-device variations. This can be achieved from three aspects: materials and process technology, device structure, and circuit design. From the aspect of materials and process technology, the key point is the poly-Si crystallization technology. Highly uniform poly-Si thin film is required to achieve good uniformity of LTPS TFTs. The best resolution is to obtain the single grain crystallization. However, it is difficult to carry out at present. From the aspect of device architecture, novel or modified device architectures for better device quality and better tolerance of device variation is needed. But it must fit in with the requirement of low cost. Therefore, without extra process step is must taken into consideration as well. In additional to the improvements from process technology and device structure, the compensation from the circuit design offers another path to solve the output variation of LTPS-TFTs analog circuits resulting from the large device-to-device variation of poly-Si TFTs. It can be achieved by optimizing circuit design with the effective compensating configuration and appropriate driving scheme.

In this thesis, we purpose to compensate the device non-uniformity of LTPS-TFTs by means of modified device architecture and circuit design. For the part of device architecture we want to improve the non-uniformity of LTPS TFTs by simply modifying the device architecture while without the use of additional masks and no need to modify the normal process of TFT fabricating. The multi-channel structure with slicing layout method is used in

this work. Recently, several researches on multi-channel structure revel that high performance and high reliability poly-Si thin film transistors can be achieved with multi-cahnnel structure resulting from the reduction of grain boundary defects and the superior gate control ability [3.6]-[3.10]. However, the improvement of poly-Si TFTs uniformity by multi-channel structure is rare discussed. The multi-channel structure of LTPS-TFT was supposed to possess better uniformity compared with conventional structure. In this chapter, the uniformity of LTPS TFTs with multi-channel structure are investigated and discussed. The mechanism of improving uniformity of multi-channel structure will be detailed expounded.

3.2 Experimental Procedure

Fig.3.1 shows the top view of the layout images of conventional single channel TFTs and the TFTs with multi-channel structure. In the multi-channel TFTs, the channel was divided into five stripes and ten stripes respectively for study the effect of stripe numbers on the device uniformity. The conventional single channel TFTs and multi-channel TFTs were fabricated on the same oxidized silicon wafers by the identical process technology. A schematic graph of key processes is illustrated in Fig.3.2. First, 500Å-thick a-Si thin films were deposited on oxidized silicon wafers by low-pressure chemical vapor deposition (LPCVD) at 550°C using SiH4 as gaseous source. Then, the a-Si thin films were crystallized by KrF excimer laser annealing in a vacuum ambient, in which the substrate temperature was controlled at room temperature. After defining the device active layer, 500/1000Å-thick tetraethyl orthosilicate (TEOS) gate oxides were deposited by low-pressure chemical vapor deposition (LPCVD). A 2000Å-thick a-Si thin film was then deposited by LPCVD for forming gate electrode. Then, the a-Si thin film was etched by transformer-coupled plasma reactive ion etching (TCP-RIE) to form gate electrodes. After removing the gate oxides,

self-aligned implantations of phosphorous with dose of 5×10¹⁵ cm^-2 were carried out to form the source and drain regions of n-channel TFTs. Then a 3000Å-thick passivation TEOS oxides were deposited by low-pressure chemical vapor deposition (LPCVD), following by dopant activation for the source/drain and gate regions by annealing at 300°C in the horizontal furnace. The process was completed after conventional contact opening and 5000 Å-thick Al metallization. After that, a 20-min sintering process was executed at 400°C for reducing the contact series resistance of the source/drain electrodes.

Fig.3.1 Layout image of conventional single channel TFTs and TFTs with multi-channel structure.

Fig.3.2 The process procedure of fabricating ELC LTPS TFTs.

3.3 Results and Discussion

3.3.1 Electrical Characteristics of Conventional

Single-channel and Multi-Channel LTPS TFTs

Fig.3.3(a)~3.3(c) show the typical transfer characteristics I-V curves of thirty n-channel LTPS TFTs (W/L=10μm/5μm) of single channel structure, multi-channel structure with five stripe numbers, and multi-channel structure with ten stripe numbers, respectively. It is clear that the performance of the thirty transistors in the subthreshold region becomes more uniform as channel stripe numbers increasing. It revels that the variation of electrical characteristics include threshold voltage and subthreshold swing are reduced by channel slicing. However, the leakage current of thirty transistors still has large distribution regardless of channel stripe numbers. Besides, it can be seen that the scale and variations of on current of single channel and multi-channel structure are almost the same from our measured results. In order to study the multi-channel effect on the on current performance more detailed, the output characteristics are also measured. The Id-Vd curves of these thirty transistors of single channel structure, multi-channel structure with five stripe numbers, and multi-channel structure with ten stripe numbers are shown in Fig.3.4(a)~3.4(c), respectively. It can be seen that the on current of multi-channel devices are slightly larger than single channel devices and the highest on current is existed in the devices with ten channel stripes, while the variations of on current between thirty transistors are still very large in the multi-channel devices. It tells that the non-uniformity of on current can not be improved in our multi-channel devices.

In additional to the Id-Vg and Id-Vd curve, the cumulative probability of twenty-five devices are shown in Fig.3.5 and Fig.3.6 to more clearly find out the device characteristics distribution of single-channel devices and multi-channel devices. Fig.3.5(a)~3.5(c) show the

cumulative distributions of critical characteristic of single channel structure and multi-channel structure including threshold voltage (Vth), subthreshold swing (SS), and transconductace (gm), respectively. The W/L of these devices is 10μm/5μm. It is obvious that large variations exist in the conventional single-channel devices. However, the variations of the threshold voltage and subthreshold swing are much smaller in the multi-channel devices and decreasing with the channel stripe numbers increasing. Nevertheless, there are still large variations of the transconductance even the multi-channel structure is employed to the devices.

Fig.3.6(a)~3.6(c) also show the cumulative distributions of the third critical characteristics in the devices with large W/L ratio (W/L=200μm/5μm ). Similar to the results seen in the devices with smaller W/L ratio (W/L=10μm/5μm), it is observed that the device characteristic variation of Vth and SS are reduced as channel stripes increasing. However, the non-uniformity of transconductance remains poor in multi-channel devices. In addition, it is noticed that the device variations of the transistors with large channel width is commonly smaller then that ones with smaller channel width. The devices with 200μm channel width and ten channel stripes suffer from the smallest device-to-device variations in our experiment.

(a)

(b)

(c)

Fig.3.3. Transfer characteristics of thirty LTPS TFTs at Vds = 0.1 V of (a) single channel devices, (b) multi-channel device with stripe number =5, and (c) multi-channel device with

stripe number =10.

(a)

(b)

(c)

Fig.3.4. Output characteristics of thirty LTPS TFTs at Vg=10V of (a) single channel devices.

(b) multi-channel device with stripe number =5, and (c) multi-channel device with stripe number =10.

(a)

(b)

(c)

Fig.3.5. Cumulative distributions of (a) threshold voltage, (b) subthreshold swing, and (c) transconductace the device parameters from 25 n-channel LTPS TFTS (W/L=10μm/5μm) of

single channel structure and multi-channel structure.

(a)

(b)

(c)

Fig.3.6. Cumulative distributions of (a) threshold voltage, (b) subthreshold swing, and (c) transconductace the device parameters from 25 n-channel LTPS TFTS (W/L=200μm/5μm) of

single channel structure and multi-channel structure.

3.3.2 Mechanisms of the Effect of Multi-channel Structure

From the experimental results discussed in the previous section, it seems that multi-channel structure can only improve the uniformity of Vth and SS, but on effect on improving the uniformity of transconductance. In this section, we will propose the mechanisms of the multi-channel effect on device uniformity of LTPS TFTs according to our measurement results.

At first, we suppose that there are three possible mechanisms of improving uniformity of LTPS TFTs by multi-channel structure. They are side-wall effect, passivation effect, and probability effect. These three effects are discussed and analyzed in the following to make out the most important factor in improving uniformity of our multi-channel devices.

z Side-wall effect

The multi-channel structure with nano-scale channels has been verified to effectively enhance the electrical performance and reliability of poly-Si TFTs [3.8]-[3.9]. It is referred to induce side-wall channels on both sides of each channel due to the tri-gate structure. It results in the increasing of effective channel width and excellent gate control. As a result, LTPS TFTs with the multiple nano-scale channels structure can obtain higher electrical performance. Therefore, the standard deviation of the device characteristics is reduced due to the increasing of the average value. However, the smallest channel width of each stripe in the multi-channel devices we fabricated is 1μm, which is impossible to form the tri-gate structure. Moreover, the50nm-thick poly-Si thin film and 50/100nm-thick gate oxide were used in our devices. The side-wall gate control capability is very weak in these devices because of the thick gate oxide. Consequently, the effect of side-wall channel can be almost neglected in our multi-channel devices. The side-wall effect is considered not to be the factor

in improving uniformity of our multi-channel devices.

.

z Passivation effect

The passivation of defects in the channel region has been proved to be the effective method for reducing grain boundary traps [3.11]-[3.16]. Trap states in the poly-Si active region have pronounced influence on device characteristics. The threshold voltage and subthreshold swing are strongly influenced by the density of dangling-bond deep states which are thought to mainly originate from dangling bonds in grain boundaries, while the field-effect mobility and leakage current are related to the strain-bond tail states which may mainly come from the intra-grain defects. The multi-channel structure has been reported to get high performance devices due to increase the efficiency of passivation resulting from the expanded passivation path [3.17]-[3.20]. Moreover, it has been verified that the passivation treatment can improves the uniformity of TFT characteristics significantly due to the reduction of localized defect density in the poly-Si film [3.21]. Therefore, it can be sure that the transistors with multi-channel structure which enhance the passivation efficiency can greatly reduce the device variation. Nevertheless, there is no passivation treatment in our devices fabricating process. As a result, the passivation effect is not the cause of improving uniformity in our multi-channel devices.

z Probability effect

For the LTPS TFTs using excimer laser crystallization, due to the non-uniform beam profile and pulse-to-pulse variation of laser energy density, a very non-uniform grain size distribution is always obtained across the whole substrate. The random grain distributions will result to huge variations of electrical characteristic between transistors. As shown in

Fig.3.7(a), when the transistors were fabricated on the substrates, it may located in the small

Fig.3.7(a), when the transistors were fabricated on the substrates, it may located in the small