Differential Pair Compensated Method

For the differential pair compensated method, an additional capacitor is used to compensate the device mismatch of the differential pair stage. The operating period usually includes two stages. First is the period to calibrate the electrical properties mismatch of the differential pair and the second stage is the signal data voltage programming period. Fig. 2.8 shows an example of this type of compensating method. The op-amp-type unit gain buffer with threshold voltage and mobility deviation-free differential amplifier was reported by Itou [2.4]. Comparing to the typical two-stage op-amp type analog buffer, one capacitor and three switches are added to the differential pair stage. The operating period including two stages: first is the calibration mode, and second is the operation mode.

Fig. 2.8. Circuit configuration and timing diagram of Itou’s differential amplifier compensated op-amp-type unit gain buffer.

In the calibration mode, switches S1 and S2 are on, and S3 is off. At this time, the two input voltages of the differential pair (MP1, MP2) are the same, and the difference of gate to source voltages between the active load pair (MN3, MN4) is stored in the capacitance C1.

The gate voltage of the active load is corresponding with the threshold voltage of the differential pair and the active load. Therefore, the differential pair mismatch and the load pair mismatch are stored in the capacitance C1. When the switches S1 and S2 are off, and S3 is on, the circuit is in the operation mode. In this mode, the input data is transmitted to the output stage. Since the differential pair mismatch and the load pair mismatch have been recorded in the first stage, the input offset resulting from device mismatches can be fully canceled in the operation mode. Thus, the final output voltage will be close to the input data signal in this buffer circuits.

Fig. 2.9. Simulation result of the offset and output voltage versus input data voltage for Itou’s differential pair compensated op-amp-type analog buffer circuit.

The output performance of Itou’s op-amp analog buffer has been studied by simulation results. Fig. 2.9 shows the output voltage-input voltage characteristic and the output offset of the buffer. The output deviation is small except in low input data signal. The Monte Carlo

simulation result is also shown in Fig. 2.10. It is obvious that the output offset variation of this buffer circuits is much smaller than that of the typical two-stage op-amp-type analog buffer. However, the output variation still remains large (~550mV) in low input data level. It is because that when the input data is in low level, the two transistors of the differential pair (MP1, MP2) operate in the linear region. Thus, the transconductance (gm) of two transistors of the differential pair are not kept in constant which result to the differential pair mismatch and the load pair mismatch cannot be recorded accurately in the capacitance C1 and result in the output performance sensitive to the device variation. Besides, the mismatch of the output stage of the analog buffer also contributes to the output variation of the Itou’s op-amp-type analog buffer.

Fig. 2.10. Monte Carlo Simulation result of the Itou’s op-amp-type analog buffer with input voltage varying from1V to 6V.

2.2.2.2 Bias Circuit Compensated Method

In the bias circuit compensated method, a threshold voltage insensitive gate bias

voltage generating circuit is applied to eliminate the influence of threshold voltage variation on the bias current. Fig. 2.11 shows an example of op-amp-type analog buffer using this compensating method [2.7]. This buffer circuit is composed of a typical two-stage op-amp unit gain buffer and the threshold voltage insensitive gate bias generating voltage.

Vg

Fig. 2.11. Circuit configuration and timing diagram of Yiu’s bias circuit compensated op-amp-type unit gain buffer.

The bias current of this op-amp can be expressed as :

2

d o x 5 _ 5 _

I 1 C ( ) (

2 ^{M N g s M N t h M N}

W V V ₅)

μ L

= − (2.1)

When there is large variation in threshold voltage that will causes bias current variation, thus the variation of gm (transconductance). This in turn causes the non-uniformity of the buffer circuit characteristics across the panel. Therefore, eliminating the effect of threshold voltage variation on bias current may maintain the output characteristics of the op-amp unit-gain buffer. Thus, Yiu propose a gate voltage biasing circuit to provide an insensitive bias gate voltage Vg, (refer to Figure. 2.10) for biasing the transistors. The operation of this

compensating circuit is described in the following. In the first stage, the transistor M1 turns on, and the capacitor will be charged up to Vref. Then transistor M1 turns off and transistor M2 turns on to connect the capacitor to transistor M3. Since transistor M3 is connected like a diode, it will discharge the capacitor until the gate voltage of the transistor M3 is equal to Vbias + Vth. Then this voltage is applied to the gate of MN5, MN6 to provide the bias

The bias current will be independent of the threshold voltage of the transistor if the transistor MN3, MN5 and MN6 are matched. Therefore, the output non-uniformity of the op-amp type analog buffer resulting from the bias current fluctuation can be eliminated in this compensating circuit architecture.

Fig. 2.12 and Fig. 2.13 show the simulation results of the output offset voltage and the output variation versus input data voltage, respectively. It is clear that large output variation still remains in this compensating circuit. It means that the electrical performance variations can not be calibrated out in this compensating architecture. It is because that the compensating method is performed in the bias circuits but not the differential pair. Even if the bias current mismatch has been compensated, the device mismatch of the differential pair and the active load pair which are the mainly causes of output variation for op-amp-type unit gain buffer still remain. Besides, the compensating configuration will

work effectively only when the electrical characteristic MN3, MN5 and MN6 are matched, but it is very difficult to achieve completely device matched between transistors. In addition to large output variation, extra setup time is also required for the application of this buffer circuit to generate the threshold voltage insensitive bias voltage. Furthermore, op-amp-type analog buffer needs many transistors which not only occupy large area but cause high power dissipation. Therefore, the op-amp-type analog buffer is not suitable for the driver integration applications.

Fig. 2.12. Simulation result of the offset and output voltage versus input data voltage for Yiu’s bias circuit compensated op-amp-type analog buffer circuit.

Fig. 2.13. Monte Carlo simulation result of theYiu’s op-amp-type analog buffer with input voltage varying from1V to 6V.

2.3 Source-Follower Type Analog Buffer

2.3.1 Conventional Source-Follower Type Analog Buffer

Fig. 2.14. Conventional source-follower type analog buffer.

Conventional source-follower type analog buffer is a very simple configuration as shown in Fig. 2.14. In order to realize the output characteristic of this circuit, HSPICE simulator is used. The simulation result of the output offset versus input voltage is shown in Fig. 2.15. Due to the intrinsic turn on characteristic of the transistor, an offset voltage about the same value to the threshold voltage will exist in the conventional source-follower type analog buffer. As shown in Fig. 2.15, the offset voltage is about 1400mV that is close to the threshold voltage of the LTPS TFTs model we used in this work. Twenty times Monte Carlo simulation is also executed to understand the effect of device variation on the output performance of the conventional source-follower type analog buffer. As shown in Fig.2.16, it is clear that the output offset variation of the conventional source-follower type analog buffer is smaller than that of the typical two-stage op-amp type analog buffer, but huge output variations still exist since the LTPS TFTs device variations. Therefore, the compensating circuit is required to eliminate the device variations for achieving high accurate output performance of source-follower type analog buffer circuits.

Fig. 2.15. Simulation result of the output voltage and output offset voltage versus input voltage of conventional source-follower type analog buffer.

Fig. 2.16. Monte Carlo simulation result of the output offset voltage of conventional source-follower type analog buffer.

2.3.2 Source-Follower Type Analog Buffer with Compensation Architecture

2.3.2.1 Self-Compensation Method

The so-called self-compensation method is to compensate the own threshold voltage variation of the driving TFT. It is usually carried out by an additional capacitance. There are usually two main operating stages in this compensating method. First is the so-called calibration period. The threshold voltage of the driving TFT is stored in the additional capacitance in this stage. Then comes the data input period to transmit the data signal, and the threshold voltage of the driving TFT that has been recorded in the first stage will be canceled out in the second operating stage. Thus, the threshold voltage insensitive source-follower type analog buffer can be obtained with this compensating method. Here

are tow examples of this kind of compensating method, one is the “Push-Pull” analog buffer reported by Chung in 2001 [2.9] and the other is the “Double Offset Canceling” analog buffer proposed by Kida in 2002 [2.10].

z Chung’s Push-Pull Analog Buffer

The circuit configuration and the timing diagram of Chung’s push-pull analog buffer are shown in Fig. 2.17. It is composed of a complementary source follower output stage, three switches, and a capacitance. The NTFT pushes up current to the output load and the PTFT pulls down current from the load; thus, it is called “push-pull” analogue buffer. The operation sequence and the compensating concept of this analog buffer will be described in the following.

Fig. 2.17. Circuit configuration and timing diagrams of Chung’s push-pull analog buffer.

There are two operating stages for this buffer circuit: first is the compensation period, and second is the data input period. During the first compensation period, switches SW1 and SW2 are turned on and SW3 is turned off. An analog signal (Vin) is applied to the gate of the driving transistors. Then the buffer output voltage will reaches Vin-VTN. Thus,the threshold voltage of NTFT will be stored in the additional capacitance Cvt. Then switches SW3 is turned on, and SW1 and SW2 are turned off. The buffer circuit is in the data input period at this time. The gate voltage will become the input voltage added to V_TN, Vgate = Vin + VTN, because the threshold voltage of the NTFT has been stored in first compensation period. Thus, the output voltage of this circuit will reach to Vin, Vout = Vgate – V_TN = Vin – VTN = Vin. In a similar way, the negative analog voltage signal is buffered by the P-type driving transistor after compensating the threshold voltage of the PTFT. In this way, the output voltage will be independent of the threshold voltage of the driving TFT. Therefore, wide threshold voltage variations of poly-Si TFTs can be compensated by this method.

Fig. 2.18. Simulation result of the output voltage and output offset voltage versus input voltage of Chung’s push-pull analog buffer.

Fig. 2.19. Monte Carlo simulation result of the output offset voltage of Chung’s push-pull analog buffer.

Fig. 2.18 and Fig. 2.19 show the simulation results of the output offset voltage versus input voltage and the output variation versus input voltage, respectively. It is obvious that the offset voltage and the output variation are much smaller than that of conventional source-follower type analog buffer due to threshold voltage variation compensated through capacitor Cvt. However, the output error and output variation of this circuit are still large for real product applications. That can be attributed to several causes. The first is the charge loss of the threshold holding capacitor (Cvt); the second is the poor subthreshold characteristic of LTPS TFTs that causes an exact threshold voltage of driving TFT cannot to be stored in the capacitor Cvt. The last cause is that the driving TFT may not be biased at the same gate-to-source voltage during two operating stage. The offset voltage stored in the capacitor Cvt during the first stage is not equal to the actual offset of this circuit. Thus the offset can not be fully canceled by this compensating method. Therefore, Kida et al. of Sony Cop.

proposed a modified compensating method named “Double offset canceling” in 2002 which

will be introduced in the following.

z Sony’s Double-Offset-Canceling Analog Buffer

The compensating concept of the Sony’s double-offset-canceling analog buffer is the same with the Chung’s push-pull analog buffer. It uses the capacitors to compensate the own threshold voltage variation of the driving TFT. The only difference between these two analog buffers is that the offset calibrating is executed two times in Sony’s double-offset-canceling analog buffer. Fig. 2.20 shows the circuit configuration and the timing diagram of double-offset-canceling analog buffer. The analog buffer is the source follower circuit which is composed of one N-type TFT, seven switches, two capacitors, and a constant current source.

Fig. 2.20. Circuit configuration and timing diagrams of Sony’s double-offset-canceling analog buffer.

The operation of this analog buffer is as follows. When Ncont is active, this buffer circuit goes active. The switch SW6 turns on first to discharge the C_L voltage level. Then the switches SW1 and SW4 turn on to supply analog data level from DAC to stored the first offset voltage of the source follower in the capacitor ccn1. Next, SW1 turns off, and SW2 turns on. The gate of the driving TFT becomes Vg=Vin+Vgs(1) at the time. Thus the second offset voltage is produced and stored in the capacitor ccn2. Then both SW2 and SW4 turn off, and SW3 and SW5 turns on to sampling the data to the output terminate. When the first offset cancellation is executed, the operating point reaches nearly to the output signal level that makes the stored voltage in the ccn2 come very close to the actual offset voltage.

Therefore, highly accurate output voltage can be achieved by precisely canceling the offset voltage of the source follower.

Fig. 2.21 and Fig. 2.22 show the simulating results of the output offset voltage and the output variation of this buffer circuit. It is obvious that the output offset voltage is very small by twice calibrating the offset of the buffer circuit. Besides, the output voltage of this buffer is almost independent to the threshold voltage variations of the driving TFT because the output voltage is nearly irrelative to the threshold voltage of the driving TFT by applying the double-offset-canceling method. Although highly precise offset canceling can be achieved in this compensating circuit, it requires many transistors, many control signals, two capacitors, and a stable current source. Consequently, it must occupy large area and need complicated operation. Furthermore, the variations of the constant current source employed by the LTPS TFTs will influence the output performance of the circuit that cannot be ignored.

Fig. 2.21. Simulation result of the output voltage and output offset voltage versus input voltage of Sony’s double-offset-canceling analog buffer.

Fig. 2.22. Monte Carlo simulation result of the output offset voltage of Sony’s double-offset-canceling analog buffer.

2.3.2.2 Matching TFTs

For the analog buffer employed the concept of matching TFTs, the function of driving TFT is to output the analog voltage, an additional diode connected transistor is used to provided a threshold voltage of the transistor for canceling out the influence of threshold voltage on the circuit output characteristics.

Jung’s analog buffer as show in Fig. 2.23 is an example of the compensating circuit with the concept of matching TFTs [2.13]. The operating sequence is described as follows.

First, reset signal is high to reset the previous data voltage in the load capacitor. Then the data signal is applied. As the voltage of node A is higher than that of node B, N1 turns on and N2 turns off. The gate of the driving TFT N3 becomes about Vin-Vth_N1 by diode connected of N1 and N3 turns on. Then N4 is turned on when “active” signal is high. Since the gate node of N3 is floating, the gate of N3 will be charged up by the bootstrapping effect through power supplied line until Vdata+Vth__N2 is reached and then the transistor N2 is turned on while N1 is turned off. The gate of N3 is no longer floating as this time, so the action of bootstrapping is stopped. Finally, the output voltage will reach to Vdata+Vth_N2-Vth_N3. If the transistors N2 and N3 are matched, the output voltage will be equal to Vdata, and the offset voltage of source follower can be eliminated. However, the device characteristic of one transistor is impossible to match another completely in reality.

Fig. 2.24 and Fig. 2.25 show the simulating results of this analog buffer, in which the mismatch of driving TFT (N3) and the compensating TFT (N2) is taken into consideration.

It is obvious that the output offset voltage and the output variations due to threshold voltage variations of driving TFT are still large. It means that the threshold voltage variations of the driving TFT cannot be compensated efficiently using matching-TFTs compensating method.

A B

Fig. 2.23. Circuit configuration and timing diagrams of Jung’s analog buffer.

Fig. 2.24. Simulation result of the output voltage and output offset voltage versus input voltage of Jung’s analog buffer.

Fig. 2.25. Monte Carlo simulation result of the output offset voltage of Jung’s analog buffer.

2.3.2.3 Inverter Type

The purpose of this compensating method is to calibrate out the influence of parasitic capacitances of driving transistor. In the self-compensation method, a compensating capacitor is used to store the threshold voltage of driving TFT in first operating period. Thus in the data input stage, the gate voltage of the driving TFT becomes Vin+Vth. However, the capacitance coupling by parasitic capacitances of Cgd and Cgs in the driving TFT will make the gate voltage of driving TFT not equal to this target voltage. As shown in Fig. 2.26, the real gate voltage of the driving TFT can be represented as equation (2.4).

C O M P E N S A T I O N

G A T E I N P U T T H

C O M P E N S A T I O N P A R A S I T I C

V V C V

C C

= + ×

+ (2.4)

Fig. 2.26. Structure of source follower with compensating capacitance.

In order to solve this problem, Yong-Su Yoo has proposed an inverter type compensating circuit in 2004 [2.16]. The circuit configuration and timing diagrams of Yoo’s inverter type analog buffer is shown in Fig. 2.27. It consists of one p-type driving TFT two inverters, four capacitors and eight switches. The operating principle of this buffer circuit is very complicated. In brief, the output voltage will final keep in the value of input voltage times aγfactor and plus a DC voltage level VCOM_LOW by the operation of these two inverters, and the coupling of four additional capacitors and the parasitic capacitances. In which, the γfactor is related to the capacitors C1, C2, C3, C4 and Cparasitic. Thus, the

In order to solve this problem, Yong-Su Yoo has proposed an inverter type compensating circuit in 2004 [2.16]. The circuit configuration and timing diagrams of Yoo’s inverter type analog buffer is shown in Fig. 2.27. It consists of one p-type driving TFT two inverters, four capacitors and eight switches. The operating principle of this buffer circuit is very complicated. In brief, the output voltage will final keep in the value of input voltage times aγfactor and plus a DC voltage level VCOM_LOW by the operation of these two inverters, and the coupling of four additional capacitors and the parasitic capacitances. In which, the γfactor is related to the capacitors C1, C2, C3, C4 and Cparasitic. Thus, the