Chapter 2 Overview of the Analog Buffer Circuits Using
4.5 Bias Voltage Effect Discussion…
The bias voltage of the active load is considered to be a factor that may affect the performance of the proposed analog buffer. The value of the bias voltage will determine the operation region of the active load, and the operation mode of the driving TFT and the active load in two operating period will affect the output characteristic due to the different output resistance of transistor in these two operation mode. Thus, in this section we will discuss the bias effect of the proposed analog buffer in detail.
First, the circuit simulation is executed to investigate how the bias voltage affects the output performance. Fig.4.14. shows the simulation result of the offset voltage and the power dissipation for the proposed analog buffer with bias voltage varying from 1.5V to 9.5V when input data voltage is 3V. It shows that the offset voltage defined as Vin minis Vout turns from positive to negative value as bias voltage increasing, and a minimum value of the offset voltage exists as the bias voltage is in the range between 2V to 2.5V. The tendency can be understood by the detailed discussion on the operation of driving TFT and the active load.
During the first compensation period, the driving TFT is in the saturation region because of the diode connected configuration and the active load is also operated in the saturation region.
However, during the data input period, the active load may operate in the saturation or the linear region depending on the bias voltage while the driving TFT still work in the saturation region.
Fig.4.14. Simulation result of the output offset voltage and the power dissipation for the proposed analog buffer with different bias voltage.
These can be divided into two conditions for discussing. In the following, we will discuss these two conditions in detail by the mathematical analysis. Here the driving TFT is assumed to TFT1 and active load is TFT2 for convenience.
A. Driving TFT in saturation region, active load in saturation region at the data input period
2 From equation (4.6), it is observed that the threshold voltage and carrier mobility variations of driving TFT and the active load both can be stored in the capacitor for the compensation during the compensation period. Therefore, the output voltage will be in theoretically equal to the input voltage independent of the threshold voltage and the carrier mobility of the driving TFT and active load as shows in equation (4.10).
B. Driving TFT in saturation region, active load in linear region at the data input period (1)Compensation period:
During the first operation period, the driving TFT and the active load will always work in the saturation region as the bias voltage is smaller than Vdd. Therefore, the situation in this condition during the compensation period is the same as described previously. In which the voltage stored in the capacitor is corresponding to the threshold voltage of driving TFT and active load, bias voltage and the K1/K2 ratio.
(2)Data input period:
2 2
(A) term can be simplified to:
2 2
2 2 2 2 2 2
Therefore, the output voltage can be simplified as
2 2 Equation (4.21) indicates that the output voltage will larger than the input voltage because that the bias voltage must be higher than the threshold voltage of the active load to turn on the active load. Therefore, we know that if the active load works in the linear region at the data input period, the output voltage will exceed the input data and thus a negative offset voltage is obtained. This situation will happen when the bias voltage is higher than the input voltage. Corresponding to the simulation result shown in Fig.4.14, it is obvious that the output offset voltage is the negative value as the bias voltage larger than the input voltage because the active load is in the linear region. Nevertheless, as the bias voltage is lower than the input voltage, the active load will operate in the saturation region and the output voltage is very closely to the input data voltage as expressed in equation (4.10).
In addition, an important information can be obtained from equation (4.21). It tells us that the output voltage can be almost equal to the input voltage when the Vbias is chosen to a lower value but just slightly above VTH2 and the large factor “a” is designed. The factor “a” is
related to the mobility and the W/L ratio of the driving TFT and the active load as represented in equation (4.3). Because of the mobility of the driving TFT and the active load are almost the same. Larger W/L ratio of the driving TFT and smaller W/L ratio of the active load were designed to possess large “a” factor which coincides with previously design in section 4.3.
The output voltage is accurate as the factor “a” is larger. However, the optimum value in designing is required to meet the specifications of display.
Furthermore, from the mathematical analysis of bias voltage effect, we can see that the proposed analog buffer circuit can compensate not only the variations of the driving TFT but also the variations of the active load. In additional to the electrical characteristic variations, the issue of TFTs reliability is also taken into consideration in this discussion. In comparison with a-Si TFTs, LTPS TFTs have better long term reliability. For example, after 1000sec DC stress with Vg=7V and Vd=14V, the threshold voltage variation is about 0.5V and the degradation of carrier mobility is about 4% [4.20]. Moreover, the gate voltage of the active load is designed to be 2V in our proposed analog buffer which is in the very low voltage level.
Therefore, it is almost no degradation of the active load in this bias condition and no apparent influence on the output performance will be seen in the proposed analog buffer circuit.
In additional to simulation result, the analog buffer circuits were also measured to study the bias effect. The measurement result is compared to the simulation result when input voltage 3V as shown in Fig.4.15. It is clear that the relationship between the offset voltage and the bias voltage of measurement result shows the same tendency with the simulation result. The simulation and measured result when input voltage 2V is also shown in Fig.4.16, and the same trend exhibited. According to the simulation and measured results, an optimum value of the bias voltage can be chosen to get the minimum output offset voltage. Furthermore, the power dissipation related to the bias voltage shown in Fig.4.14 exhibit that the power dissipation is small when the bias voltage is in the range corresponding to the minimum output offset voltage. It is clouded that an appropriate design of the bias voltage is required to
achieve high output performance and keep low power dissipation.
Fig.4.15. Output offset voltage versus bias voltage of the measurement result in comparison with the simulation result at input voltage Vin=3V.
Fig.4.16. Output offset voltage versus bias voltage of the measurement result in comparison with the simulation result at input voltage Vin=2V.
4.6 Comparisons between the Proposed Analog Buffer Circuit and Others Analog Buffer Circuits
The comparisons of the proposed analog buffer and others analog buffer including op-amp type analog buffers and source-follower type analog buffers are given in the output performance, circuit configuration, and power consumption in this section. As shown in Taable 4.2, the output offset voltage deviation and the output offset voltage variations are both smaller than that of others buffer circuits expect sony’s double-offset-canceling buffer. The output performance is superior to the Chung’s push-pull analog buffer due to the compensation from the power supply line (Vdd) instead of the input signal line in Chung’s buffer. Although the output performance of the sony’s double-offset-canceling analog buffer is greater, the requirements of many transistors and extra applied signals which occupies large area and cause much higher power consumption in comparison with our proposed analog buffer. The circuits configuration and power dissipation of the proposed analog buffer are also superior to others buffer circuits.
Table 4.2 Comparison of the proposed analog buffer and others buffer circuits.
4.7 Summary
A novel source follower type analog buffer using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) for the integrated data driver circuits of active matrix liquid crystal displays (AMLCD) and active matrix light emitting diodes (AMOLED) has been proposed. It is composed of two n-type thin film transistors, one storage capacitor and four switches. Besides the data line and DC power supply lines, two additional control signals were used. However, the sign of these two control signal are completely inverse, and thus only one control signal line is needed by adding an inverter. Therefore, an analog buffer with simple circuit configuration is achieved.
The proposed buffer circuit compensates the device variation of transistors by a
capacitor and the simple operation scheme. Both the simulation and measurement results exhibit that the output variation resulting from the variation of poly-Si TFT characteristics is successfully compensated in the proposed analog buffer. The output offset voltage is also eliminated through the compensation operation. Furthermore, the unsaturated of output voltage arisen from the significant subthreshold current is solved by adding an active load.
The effect of the bias voltage applied to the active load is also discussed in this study. An optimum parameter of the bias voltage can be designed to achieve high output performance and keep low power dissipation of the proposed analog buffer. Consequently, the proposed analog buffer has high immunity to device variation, simple configuration, and low power consumption which is suitable for integrated system application.
Chapter 5
Summary and Conclusions
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The uniformity issues of low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) in devices and analog buffer circuits were investigated in this thesis. The multi-channel structure is employed to improve the uniformity of LTPS TFTs and the mechanism of improving device uniformity is proposed. In addition, the design of LTPS TFTs analog buffers has been studied. A new simple source-follower type analog buffer with compensating configuration has been proposed. The improvement of output variation is achieved by compensating the device variations through a capacitor and the appropriate operation schemes.
In chapter two, several kinds of analog buffer circuits using LTPS TFTs are introduced and discussed. These analog buffer circuits are classified into operational amplifier type (op-amp-type) analog buffer and source-follower type analog buffers according to their circuit architecture and divided into six major compensating methods. These compensating architectures of analog buffer circuits are necessary owing to the electrical characteristic variation of the transistors resulting from the random distribution of grain boundaries. The advantages and disadvantages of each kind of circuit compensating method have also been discussed and compared. In conclusion, the source-follower type analog buffer with simple configuration, better immunity to the LTPS TFTs device variation, and lower power dissipation is considered to be the best candidate for system-on-panel applications.
In chapter three, the effects of multi-channel structure on the device uniformity of LTPS
TFTs and the output performance of source follower analog buffer are investigated. It is clear that variations of the threshold voltage and subthreshold swing are reduced as channel stripes increasing, while no such tendency can be seen in the transconductance and leakage current.
The mechanism of the improving uniformity of multi-channel structure is discussed and it is considered that probability effect is the most possible cause. According to the probability distribution, better uniformity of threshold voltage and the subthreshold swing of poly-Si TFTs can be obtained with channel slicing due to the more uniform grain boundaries densities between transistors. While the variations of the mobility and leakage current can not be reduced due to the remained tail states variations of multi-channel devices. At last, the conventional source follower with multi-channel structure is also studied. It is clear that the output offset voltage variations of source follower with multi-channel structure in the driving TFT are reduced to about half of that in conventional source follower. It confirms that the variations of poly-Si TFTs indeed can be reduced by the multi-channel structure.
In chapter four, a novel simple source follower type analog buffer using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) for the integrated data driver circuits of AMLCD and AMOLED has been proposed. It consists of two n-type thin film transistors, one storage capacitor and four switches. Both the simulation and measurement results exhibit that the output variation resulting from the variation of poly-Si TFT characteristics is successfully compensated in the proposed analog buffer. The output offset voltage is also eliminated through the compensation operation. Furthermore, the unsaturated of output voltage arisen from the significant subthreshold current is solved by adding an active load.
The effect of the bias voltage applied to the active load is also discussed in this study. An optimum parameter of the bias voltage can be designed to achieve high output performance and keep low power dissipation of the proposed analog buffer. Consequently, the proposed analog buffer has high immunity to device variation, simple configuration, and low power consumption which is suitable for integrated system application.
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