Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)
In this section, we will compare the difference between the a-Si TFT and LTPS TFT from two aspects. First is the manufacturing aspect in terms of process steps, commercial cost, and yield and second is the electrical performance including the driving capability and stability.
z Manufacturing aspect
z Process Steps and Commercial Cost
Less process steps, usually four to five mask processes are necessary for the fabrication of a-Si TFT which is usually employed by bottom gate structure. These mask processes include gate electrode, a-Si active layer, source/drain electrode, passivation layer, and ITO.
Compared to a-Si TFT, top gate structure is usually adopted for LTPS TFTs, and more process steps, nine to ten mask process are needed. They are poly-Si active layer, channel and source/drain implant (N+, N-, P+), gate electrode, inter layer dielectric, source/drain electrode, passivation layer, and ITO.
In addition to more process steps, extra equipment is required to fabricate the LTPS TFTs. These include excimer laser annealing for poly-Si film crystallization, ion implanter or ion shower for implantation to form the source/drain, rapid thermal annealing or excimer laser annealing for doping activation. Consequently, higher equipment cost than a-Si TFT is required to fabricate LTPS TFT. More process steps and higher equipment investment make LTPS TFT more costly than a-Si TFT [1.28]
z Electrical Performance
z Driving Capability
Due to the smaller grain sizes and higher gate/source and gate/drain overlap capacitances of hydrogenated amorphous silicon TFT, the mobility of a-Si TFTs is generally below 1.0 cm2/V-s, and such low carrier mobility limits the driving capability of a-Si TFT.
In order to meet sufficient driving capability, large W/L ratio must be designed in the a-Si TFT based circuits which limit the resolution of display. Besides, with the intrinsic properties of a-Si, only n-type TFT is available when a-Si is employed which greatly
reduces the flexibility of TFT applications and causes some difficulties in designing. On the other hand, the carrier mobility of LTPS TFT is one or two orders higher than that of a-Si TFT. The higher driving ability makes it a good candidate for high resolution displays, even provides the possibility of integrating driver circuits for AMLCDs and AMOLEDs to realize completely system on panel (SOP). Besides, both n-type and p-type LTPS are available, therefore CMOS drivers can be integrated on the substrate.
z Stability
A-Si TFT suffers from large threshold voltage shift and conductance current lowering after long term operation. These device performance degradations are commonly explained by two mechanisms which include the dangling-bond states creation in the amorphous silicon layer and charge trapping in the gate insulator [1.29]-[1.30]. On the other hand, LTPS TFT is quite stable relatively after a prolonged period of biasing time.
Although low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) require higher manufacturing cost than that of a-Si TFT, the higher driving capability and better long term reliability of the LTPS TFT are more suitable for the flat panel display applications. At present, LTPS TFT has attract much attention for integrating driver circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) [1.31]-[1.32]. However, there are still some issues of LTPS TFTs for system-on-panel (SOP) application. The more detailed concepts and issues of system-on-panel (SOP) are discussed in the next section.
1.3 The Concepts and Issues of System-On-Panel (SOP)
At present, application of thin film transistors (TFTs) for active matrix display is mainly in the pixel element, the driving circuits and other controlling circuits of active matrix display are employed with single crystalline VLS IC design on printed circuit board (PCB). It requires large numbers of interconnections between the panel and the peripheral circuits. Since off-panel connections have considered to be the most frequent cause of LCD failure, the system-on-panel (SOP) technology which omitting the usage of ICs and interconnections promise the LTPS-based products to be more reliable. Moreover, reducing the number of external components and the connections to display enable to lower the cost of panel and a compact, light weight system can be achieved for better economic benefits.
Thus, several researches have been proceeded to integrate the analogue and digital display driver circuits , controller circuits, random access memory (RAM), and more complicated part such as central processing unit (CPU) or digital signal processing (DSP) on the active matrix substrate [1.33]-[1.34]. In 2004, the first full-functional system panel was proposed by Sharp Corporation and Semiconductor Energy Laboratory Co., where a CPU, a graphic controller, an audio circuit, a program ROM, an audio ROM, various types of RAMs, a voltage generator, a clock generator, and the large-scale logic circuits comprising approximately 120,000 TFTs are monolithically formed on a glass substrate forming an LCD by using CG-Silicon technology [1.35].
Although the system display has been successfully demonstrated, the technology is not matured for mass production. In additional, the advantages of lower system cost and lower power consumption are not apparent nowadays. The properties of poly-Si TFTs are considered to be the key factors for the goal of system-on-panel, thus the disadvantages of electrical properties and the fabrication techniques of poly-Si TFTs must be improved to
satisfy the requests for system on panel. Here, several critical issues and the research opportunities for developing system on panel are discussed in the following sections.
z Issues of System-On-Panel
z Electrical Properties
At present, the performance of poly-Si TFTs is still much poor in comparison with conventional single-crystal MOSFETs such as lower carrier mobility, higher threshold voltage, larger subthreshold current and larger leakage current, etc. In order to achieve high speed and high driving capability of poly-Si TFTs, significant advances in carrier mobility are needed. As the carrier mobility is improved, the scale of the transistors can be reduced without sacrificing the driving current, thus high integrated density of transistors can be obtained for high resolution and more functions integrated display system. For the demand of low power consumption, low and centered (between n-tpe TFT and p-type TFT) threshold voltage of poly-Si TFTs is needed. The high threshold voltage will result in relatively high voltage supply required to drive the circuits and dissipate high power.
The kink effect and hot carrier effect of poly-Si TFTs are also the critical problems in system display progressing. Kink effect of poly-Si TFTs causes the high value of output conductance and a strong dependence on bias condition [1.36] that will raise the difficulty in circuit design. For example, in analogue applications that will lead to a considerable reduction of the maximum attainable gain and reduces the common mode rejection ratio (CMRR), and result in increasing of power dissipation and slightly degrades the switching characteristics in digital circuits. Besides, the unsaturated I-V curve causes the problem in saturation voltage defined. The standard definition of saturation voltage is not applicable because a well-defined saturation does not exist. Hot carrier effect will cause the shift of
threshold voltage, subthreshold swing, and mobility of poly-Si TFTs due to the carrier trapped in the Si/SiO2 interface or carrier injection to the gate oxide. This will degrade the reliability of poly-Si TFTs. Moreover, in order to reduce the kink effect and hot carrier effect, device with drain-engineering architecture or some circuit configurations (e.g.
cascode, normally used to reduce the consequences of the kink on circuits) must be introduced. Thus the added steps of device process and excessive number of stacked devices are required which result in an increase in fabricated cost and power dissipation.
The device electrical properties play a key role in the performance of display, therefore, electrical characteristics of poly-Si TFTs must be further improved for meet the requirements of next system-on-panel (SOP) generation.
z Uniformity
Over the past ten years, laser-based crystallization has been intensely studied and developed for poly-Si TFTs [1.37]-[1.40], and have been verified to be the excellent technology with the ability to produce high quality poly-Si films [1.41]. Excimer laser crystallization (ELC) is the most commonly used method for mass production of LTPS TFTs. However, the narrow process window of laser energy density for producing poly-Si thin film is a critical issue for ELC LTPS TFTs. In order to crystallize large-grain poly-Si, the laser energy density must be controlled in the super lateral growth (SLG) region.
Nevertheless, the pulse-to-pulse variation of excimer laser energy density and non-uniform laser beam profile cause the laser energy density not to be uniformly controlled in the SLG region across the large area. That result in random grain boundaries distributed in the channel region of LTPS TFTs between devices. As the channel dimensions continue to shrink, the uniformity behavior becomes more severe. The larger device-to-device variation will lead to many problems in real product applications.
z Design Rule Consideration
The performance of poly-Si TFTs is inferior to that of conventional single crystallization Si MOSFETs at present. In order to keep compatible with large-area processing, relatively coarse design rules must been used in designing the poly-Si TFTs based circuits [1.41]. There are three reasons for this phenomenon. First of all, the restriction of photolithographic and processing for fabricating TFTs on the large-area substrate is severe. It is more challenging to scale down the device into the submicron dimension because of limitations in the resolution of lithography equipment. Second, the short-channel effects are relatively severe in poly-Si TFTs. As the dimension scaled down, the short-channel effects will intensely affect the device performance and make more difficulty in designing. Third, an AMLCD pixel typically requires a total voltage swing of about 10 V to encompass both the positive and negative driving polarities, and about 15 V supply voltage is needed by using poly-Si TFTs drivers. Therefore, the broader line width is required.
In order to enhance the device performance, the dimension of poly-Si TFTs must be scaled down. For the development of more advanced panels systems, the dimension of channel must be shrunk to submicron dimension (<0.8um) to achieve high performance TFTs [1.42]. However, there are many challenges to scale down the device into the submicron dimension domain by current mass production technologies. Thus it requires the development and introduction of new technologies of process and device.
z Power Consumption
Because of the higher threshold voltage, lower mobility, and loose design rule of
poly-Si TFTs compared to single crystal Si MOSEFTs. It require higher supply voltage for sufficient driving capability of poly-Si TFTs, thus the power consumption of integrated driver circuits tends to be higher than that of single crystal silicon ICs. This tendency will increase as circuit-integration progresses. For example, in the case of QVGA (Quarter Video Graphics Array) LCDs, the power consumption of conventional TFT-LCD with external driver ICs ranges from 10 to 13 mW, while that of typical SOP-LCDs with integrated driver circuits ranges from 20 mW upwards, which is more than twice of the power consumption of conventional TFT-LCDs [1.43].
Therefore, power reduction is one of the major challenges in further advanced SOP-LCDs application. From the viewpoint of device electrical characteristics, low and centered (between nMOS and pMOS device types) threshold voltage with extremely small distribution is needed for meeting the requirement of low power consumption. Designing the driver circuits with simple configuration and less control signals is also a solution from the designing aspect. Furthermore, modified driver architecture and lowered the line resistance and parasitic capacitance are also the efficient methods to reduce the power consumption.
z Yield
At present, the fabrication cost of low-temperature poly-Si TFTs is higher than that of amorphous silicon TFTs because of more process steps and more expensive equipments.
The reduction of external component cost has been offset by the higher fabrication cost in many commercial applications, resulting in higher display prices. Besides, the narrow process window of laser crystallization technology, and additional steps or more complex texture employed to achieve high performance poly-Si TFTs (ex. drain engineering for reducing the kink effect and hot carrier effect, additional steps or equipments for
crystallization to get high carrier mobility) will also reduce the production yield rate.
Therefore, how to get high manufacturing yield is really important for real production applications.
z Research Opportunities for Realizing System-On-Panel
To achieve the goal of system-on-panel, the improvements at various levels are required to solve several issues as discussed above. This can be achieved from three aspects:
materials and process technology, device structure, and circuit design.
z Materials and Process Technology
New elemental process technology is needed for the formation of high quality critical
layers, such as the active and the gate-insulator layers of poly-Si TFTs.
In the area of active layer, high quality poly-Si microstructure is needed to increase device performance. The crystallization process is a very critical step of the fabrication process for TFTs, because it needs to satisfy the requirements on trade-off considerations including material quality, fabrication cost and thermal-budget constraints imposed by the display substrate. The key points for further improved poly-Si crystallization technology are high electrical performance and good uniformity which can be achieved through enlarging grain size, reducing the defect densities, getting good grain orientation and location control.
Several advanced crystallization technology has been proposed to achieve large grain size or location controlled poy-Si film such as the “Continuous Grain Silicon (CG Silicon)”
technology by Shrap Corporation [1.44]-[1.45], “Selectively enlarging laser crystallization (SELAX)” technology by Hitachi, Ltd. [1.46]-[1.47], or “comb-shaped excimer laser annealing” technology by NEC Corporation [1.48]-[1.50].
In terms of gate insulator layer, there are requirements in thickness and film quality - i.e. fixed and interface trap density, reliability against electrical stress. GI thickness reduction is necessary to get a TFT gate length in the submicron range. As GI thickness decreases, issues of step coverage become increasingly more severe. Current gate insulator technology is based on PECVD TEOS-SiO2, but this technology seems incapable of overcoming the challenge with the gate insulator thickness gradually decreasing to 50 nm and beyond. In order to maintain high quality for increasingly thinner gate insulator layer, new technology must be introduced.
z Device Architecture
Modified device architectures must complement and customize device performance according to required function. Improvements in the device architecture are vital in two aspects: (1) enable the fabrication of submicron channel dimensions with technology compatible with LCD manufacturing and (2) provide an additional way to complement material quality and compensate the variation of material properties in the critical layer for supplying additional controls for system optimization. But it must conform to the requirement of low cost, thus without extra process step (ex. additional steps for drain engineering or integration of low-voltage and high-voltage TFTs) is also taken into consideration.
z Circuit Design
In additional to improved process technology and device structure, improvements from the circuits design concept offer another solution to realize the goal of system-on-panel. For example, analog buffer which is indispensable to driving large load capacitance of the panel
will suffer from large offset voltage and huge output variation due to the high threshold voltage and large device-to-device variation of poly-Si TFTs. Precise circuit design is employed to deal with the output offset voltage and eliminate the output variation of the buffer circuits through the appropriate circuit architecture and driving scheme. To ensure designing accurately of circuits, suitable device model and exact device parameters are required. It is important to develop accurate models of poly-Si TFTs for circuit simulation and design.
1.4 Motivation
The “system-on-panel (SOP)” technology by low-temperature poly-Si thin-film transistors (LTPS TFTs) is considered to be the most promising solution for realizing the compact, highly reliable, fully functionally, and low system cost display because of the higher carrier mobility of LTPS TFTs which allow the integration of the driver circuit with pixel circuits on a single glass substrate. However, the severe device-to-device variation of LTPS TFTs due to the inevitable process such as pulse-to-pulse variation of laser energy density and random distribution of grain boundaries greatly restrict the progress of system-on-panel (SOP) technology. Thus, in this thesis, the electrical non-uniformity of LTPS TFTs is studied from two viewpoints: device structure and circuit design.
z The Effect of Multi-channel Structure on the Uniformity of LTPS TFTs
In this part, we purpose to improve the device non-uniformity of LTPS-TFTs from the aspect of device architecture by means of simply modifying the device architecture while without the use of additional masks and no need to modify the normal process of TFT
fabricating. The multi-channel structure with slicing layout method is used in this work. The electrical characteristics and uniformity of multi-channel devices are studied and compared to conventional single-channel devices. The mechanisms of improving uniformity by the multi-channel structure are found out according to the experimental results.
z Electrical Uniformity Compensation by Circuit Design
For the development of integrated data driver employing LTPS TFTs, output buffers are indispensable to drive the large load capacitance of data lines. However, the LTPS TFTs suffer from huge device-to-device variations that cause the bad uniformity of output voltage of analog buffers across the panel. Therefore, many researches on LTPS TFTs analog buffer have been tried to realize a buffer with high immunity to the device variations, and source-follower type analog buffer shows the superiority among these efforts. In additional to the large variations of electrical properties, LTPS TFTs have much larger subthreshold current compared with single crystal Si transistors, and this poor electrical characteristic will results to large output offset and cause the output voltage not to be constant with time. Thus in this thesis, we intend to design a new source-follower type analog buffer which can not only eliminate the output variations but suppress the output unsaturated phenomenon of conventional source-follower type analog buffer. The proposed analog buffer is composed of two n-type thin film transistors, one storage capacitor and four switches. The output voltage variation decreases greatly by the storage capacitor and compensated operation of the proposed buffer. Furthermore, the unsaturated phenomenon of output voltage arisen from the significant subthreshold current of driving TFTs is also eliminated by adding an active load. According to the simulated and measured results, it is obvious that the output voltage is very closely to the real input voltage and the output variations are successfully compensated in the proposed analog buffer.
1.5 Thesis Organization
In chapter two, two types of analog buffers employing low-temperature polycrystalline
In chapter two, two types of analog buffers employing low-temperature polycrystalline