Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS

Discrete Dopant Fluctuations in

20-nm/15-nm-Gate Planar CMOS

Yiming Li, Member, IEEE, Shao-Ming Yu, Jiunn-Ren Hwang, and Fu-Liang Yang

Abstract—We experimentally quantified, for the first time, the

random dopant distribution (RDD)-induced threshold voltage

(V

) standard deviation up to 40 mV for 20-nm-gate planar

complementary metal–oxide–semiconductor (CMOS) field-effect

transistors. Discrete dopants have been statistically positioned in

the 3-D channel region to examine the associated carrier

trans-portation characteristics, concurrently capturing “dopant

con-centration variation” and “dopant position fluctuation.” As the

gate length further scales down to 15 nm, the newly developed

discrete dopant scheme features an effective solution to suppress

the 3-sigma-edge single-digit dopant-induced V

variation by the

gate work function modulation. The results of this paper may

postpone the scaling limit projected for planar CMOS.

Index

Terms—Complementary

metal–oxide–semiconductor

(CMOS) device, dopant concentration variation, dopant position

fluctuation, random dopant distribution (RDD), threshold voltage

fluctuation, 3-D modeling and simulation.

I. I

I

T IS KNOWN that gate length scaling is still the most

effective way to continue Moore’s law for transistor density

increase and chip performance enhancement [1]–[3].

How-ever, as the planar complementary metal–oxide–semiconductor

(CMOS) field-effect transistor advances to sub-20-nm gates,

double-digit channel dopants make transistor behaviors more

complicated to be characterized with conventional “continuum

modeling” because every “discrete” dopant has its

signifi-cant weight impacting the resulting transistor performance.

The random nature of discrete dopant distribution results

in significantly random fluctuations, such as the deviation

of threshold voltage (V

), drive current mismatch, and so

on [3]–[14]. The fluctuation budget has to be controlled

even tighter due to the doubly increased transistor number

along with technology node moving ahead. Unfortunately, the

Manuscript received August 27, 2007; revised January 23, 2008. This work was supported in part by the National Science Council of Taiwan under tract NSC-96-2221-E-009-210, Contract NSC-95-2221-E-009-336, and Con-tract NSC-95-2752-E-009-003-PAE, in part by the MoE ATU Program under a 2006–2007 Grant, and in part by the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C., under a 2006–2008 Grant. The review of this paper was arranged by Editor H. S. Momose.

Y. Li is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: ymli@faculty. nctu.edu.tw).

S.-M. Yu is with the Department of Computer Science, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.

J.-R. Hwang and F.-L. Yang are with the Taiwan Semiconductor Manufac-turing Company, Hsinchu 300, Taiwan, R.O.C.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.921991

fluctuation is intrinsically increased with the scaling of

tran-sistor feature size, not even considering the worsened short

channel control [3].

Without loss of generality, the fluctuation can be decomposed

into three components: one is resulting from the random dopant

distribution (RDD) [3]–[8], [10]–[14]; and the others are due

to the mean gate length deviation (GLD) and the line edge

roughness (LER) [3], [4], [6], [8], [9]. The mean GLD and

the LER mainly resulted from issues associated with resolution

and granularity of lithography. The RDD-induced fluctuation is

due to the random nature of ion implantation. Various random

dopant effects have been recently studied in both experimental

and theoretical approaches [4]–[8], [10]–[14]. These studies

have shown that the fluctuation of electrical characteristics is

not purely a result of a variation in average doping density

as-sociated with a fluctuation in the number of dopants but also the

particular random distribution of dopants in the channel region.

In this paper, we are absorbed in the random dopant effect and

herein developed a systematic method to experimentally extract

the RDD-induced V

fluctuation. We have, for the first time,

experimentally quantified the RDD-induced threshold voltage

standard deviation up to 40 mV for 20-nm-gate planar CMOS.

Discrete dopants have been statistically positioned in the 3-D

channel region to examine the associated carrier

transporta-tion characteristics, concurrently capturing “dopant

concentra-tion variaconcentra-tion” and “dopant posiconcentra-tion fluctuaconcentra-tion.” Therefore, a

3-D “atomistic” device simulation, in good agreement with the

experimental data, has been carried out to realize statistical

analysis and to feature solutions for reducing the RDD-induced

V

variation upon gate length (L

) scaling. As the gate length

of CMOS devices further scales down to 15 nm, the developed

approach also suggests a solution to suppress the 3-sigma-edge

single-digit dopant-induced V

variation by gate work function

modulation. We believe that the study may postpone the scaling

limit projected for nanoscale CMOS devices.

This paper is organized as follows. In Section II, we state

the experiment and simulation. In Section III, we show the

results and discuss comparison between the measurement and

simulation. Finally, we draw conclusions.

II. E

S

T

Threshold voltage is one of the key device parameters in the

characteristics of nanoscale metal–oxide–semiconductor

field-effect transistors (MOSFETs). As the mean GLD, LER [3], [4],

[6], [8], [9], and RDD [3]–[8], [10]–[14] are the major variation

sources of threshold voltage, we can thus extract the

RDD-induced standard V

deviation σV

from the following

1450 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008

approximated equation as σV

and σV

can be

directly measured from the experimental data [3]:

(σV

)

≈ (σV

)

+ (σV

)

(1)

where σV

is the total standard V

deviation, and

σV

is the V

fluctuation contributed from the

mean GLD and LER. Using the V

rolloff relation [15]

σV

= (dV

/dL

)

× σL

, σV

can be

ex-tracted with the experimental data of V

rolloff and standard

GLD σL

. Thus, from the experimentally measured σV

and extracted σV

, we can calculate σV

ac-cording to (1). We notice that for data with large σV

, the

I

distribution is scattering. However, it can still be

analyzed and well fitted by (1). σL

is obtained from scanning

electron microscope critical dimension measurements.

In this paper, an excellent short-channel-effect control down

to 20-nm gate has been experimentally realized with advanced

shallow junction technology. We achieve a junction depth of

around one-half of the gate length to maintain the subthreshold

leakage at 100 nA/µm with channel doping

≈ 5E18 cm

and gate dielectric of 12 A

equivalent oxide thickness (EOT).

Furthermore, to have the insights of RDD effects, quantum

mechanical transport simulation is performed and compared

with experimental data by solving a set of calibrated 3-D

density–gradient equation coupling with Poisson equation

as well as electron–hole current continuity equations [11],

[15]–[17]. The 3-D device simulation was calibrated against

the nonequilibrium Green’s function simulation for planar

MOSFETs [17]–[19]. All the statistically generated discrete

dopants, as shown in Fig. 1 (details in the next paragraph), are

advanced and incorporated into the 3-D device simulation under

our parallel computing system [16]. Such large-scale

simula-tion approach allows us to explore the electrical characteristic

fluctuations concurrently induced by the randomness of dopant

number and the position in the channel region. The mobility

model used in the device simulation, according to Mathiessen’s

rule [20], [21], can be expressed as

1

µ

=

D

µ

+

D

µ

+

1

µ

(2)

where D = exp(x/l

), x is the distance from the interface,

and l

is a fitting parameter. The mobility consists of three

parts. 1) The surface contribution due to acoustic phonon

scat-tering is µ

= (B/E) + [C(N

/N

)

/E

(T /T

)

],

where N

= N

+ N

(N

is the acceptor impurity density,

and N

is the donor impurity density), T0

= 300 K, E is the

transverse electric field normal to the interface of

semicon-ductor and insulator, B and C are parameters based on the

physically derived quantities, N0

and τ are fitting

parame-ters, T is the lattice temperature, and K is the temperature

dependence of the probability of surface phonon scattering.

2) The contribution attributed to surface roughness scattering

is µsurf_rs

= [((E/Eref)

/δ) + (E

/η)]

, where Ξ = A +

[(α

· (n + p)N

ref

)/(N

+ N

)

], E

= 1 V/cm is a reference

electric field to ensure a unitless numerator in µsurf_rs, Nref

=

1 cm

is a reference doping concentration to cancel the unit

of the term raised to the power v in the denominator of Ξ,

Fig. 1. (a) Discrete dopants randomly distributed in (100 nm)3cube with an average concentration of 5E18 cm−3. There will be 5000 dopants within the (100 nm)3_{cube, but the dopants vary from 24 to 56 (the average number is 40,}

and the standard deviation is 6.3) within its 125 subcubes of (20 nm)3_{[(b), (c),}

and (e)]. These 125 subcubes are then equivalently mapped into the channel region for dopant-position- and dopant-number-sensitive simulation, as shown in (d).

δ is a constant that depends on the details of the technology

(such as oxide growth conditions), N1

= 1 cm

, and A, α,

and η are fitting parameters. 3) The bulk mobility is µbulk

=

µ

(T /T0)

, where µ

is the mobility due to bulk phonon

scattering, and ξ is a fitting parameter. The mobility model is

quantified with our device measurements for the best accuracy.

First, the doping profile is analytically approximated to the

device measured. We then apply the method to be described

below, shown in Fig. 1, to generate discrete dopants in the

channel region. Fig. 1 briefly illustrates how to generate a

discrete dopant channel for the aforementioned simulation,

concurrently capturing the randomness of dopant number and

dopant position. Fig. 1(a) shows the discrete dopants randomly

distributed in the cube of volume (100 nm)

_{with an average}

concentration of 5E18 cm

, which is the same as the fabricated

device. There will be 5000 dopants within the (100 nm)

cube,

but dopants vary from 24 to 56 (the average number is 40,

and the standard deviation is 6.3) within its 125 subcubes of

(20 nm)

_{, as shown in Fig. 1(b), (c), and (e), respectively. These}

125 subcubes are then equivalently mapped into the channel

region for the discrete dopant simulation, as shown in Fig. 1(d).

In principle, 3-D device simulation with 125 channel structures

Fig. 2. Experimental saturation threshold voltage Vtsof N-MOSFETs with

Lgdown to 20 nm for (a) width = 200 nm and (b) width = 20 nm at Vd=

1.0 V. The saturation threshold voltage is defined as a gate voltage for the saturation drain current of 100 nA.

Fig. 3. Experimental Ion–Ioffcharacteristics of N-MOSFETs with Lgdown

to 20 nm for (a) width = 200 nm and (b) width = 20 nm at Vd= 1.0 V. Ion

was normalized against theON-state current of the nominal Lgcase, i.e., the

20-nm Lgcase.

Fig. 4. (a) Experimentally extracted σVt, RDDand discrete dopant simulation

(∗, Lg= W = 20 nm, EOT = 12 A◦) for various devices with nominal Lg

from 55 nm down to 20 nm. The width is fixed and the length is varying to give the range of values of (W L)−0.5. The sample size for each data point of

σVtis around 100 points. (b) Extracted σVt, GLD&LERfor c and d conditions.

The value was normalized against σVt, GLD&LERof the nominal Lgcase in

d condition.

TABLE I

CORRESPONDINGPARAMETERS FORALLCASES INFig. 4. ITPRESENTS THETREND OFσVtFORTECHNOLOGYSCALING. THENOMINALLg

CASES IN THETABLEARE THENOMINALGATELENGTHS FOREACH TECHNOLOGYNODE, RESPECTIVELY

almost covers

±3σ cases, as shown in Fig. 1(e), and thus will be

fairly meaningful to reflect the statistical randomness of dopant

number and dopand position in the channel region.

III. R

D

Figs. 2 and 3 show the experimental V

fluctuation and

the

- and

-state current (Ion–Ioff

) characteristics of the

n-typed MOSFETs (N-MOSFETs) down to 20-nm gates. The

L

values in Fig. 2 are estimated from the gate capacitances

in analysis data, and we presume that the widths of all

sam-ples are 200 and 20 nm for Fig. 2(a) and (b), respectively.

As expected, the V

rolloff characteristics of 20-nm-wide

vices are much more scattered than that of 200-nm-wide

de-vices. The RDD-induced V

’s standard deviation σV

has

then been experimentally extracted, as shown in Fig. 4(a).

The discrete dopant simulation for L

= width (W ) = 20 nm

1452 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008

Fig. 5. (a) Extracted nonstrain mobility versus doping concentration at 0.3 and 1 MV/cm vertical field. (b) Scaling of the average channel dopant numbers versus channel size.

[data represented with the symbol

, as shown in Fig. 4(a)] is

in good agreement with the experimental data, which confirms

that the channel doping is randomly distributed as statistically

modeled. As shown in Fig. 1, more than 100 cases are

re-quired for a set of L

and width. We notice that each 3-D

simulation case may take about three to seven days for the

final convergent result. Without loss of generality, due to the

heavy computing resource, we select the most critical case (i.e.,

length = width = 20 nm) for comparison between simulation

and measurement. Fig. 4(b) shows the extracted σV

of c and d conditions. The σV

contains the

contri-bution from the mean GLD and the LER. In our experimental

data, the σV

increases as (W L)

increased, and

it has a similar trend compared with σV

. Table I

sum-marizes the corresponding parameters for all cases in Fig. 4.

Fig. 5(a) shows the extracted mobility versus the doping

con-centration from samples of the cases (a) and (b), as shown in

Fig. 4(a). The used mobility model can generate mobility that

is in good agreement with the extracted mobility, as shown

in Fig. 5(a). The low-field electron mobility at 0.3 MV/cm is

greatly reduced with increasing doping concentration. That is

why we limit our channel doping concentration at 5E18 cm

,

which corresponds to an average of 40 dopants in (20 nm)

cubes and 17 dopants in (15 nm)

cubes, as shown in Figs. 1

and 8, respectively. Less channel doping concentration may

reduce σV

, but the channel dopants will quickly approach

a single-digit number, as shown in Fig. 5(b). Fig. 6(a)–(c) shows

Fig. 6. Distributions of (a) Ion, (b) Ioff, and (c) Vts versus the

chan-nel dopants for the 125 discrete-dopant 20-nm-gate transistors (Lg= W =

20 nm) shown in Fig. 5(e).

the I

, I

, and V

distributions versus the channel dopants

of these 125 cases. From the random-dopant-number point of

view, the equivalent channel doping concentration increases

when the dopant number increases. This substantially alters

the threshold voltage and the

- and

-state currents, as

shown in Fig. 6(a)–(c), respectively. The random dopant

po-sition induced a different fluctuation of characteristics in spite

of the same number of dopants. Furthermore, the magnitude

of the spread characteristics increases as the number of dopants

increases. Fig. 7(a) shows the Ion–Ioff

characteristics of the 125

cases from Fig. 1. Fig. 7(b)–(d) discloses three different discrete

dopant channels that have similar values of Ion

or Ioff

but

with various dopant distributions. Their corresponding

cross-sectional

-state electrostatic potential and

-state current

Fig. 7. (a) Ion–Ioff characteristics of the 125 discrete-dopant 20-nm-gate

transistors (Lg= W = 20 nm). (b) and (d) Two cases of channel doping with

similar Ionbut different Ioff. (c) and (d) Two cases of channel doping with

similar Ioffbut different Ion. The correspondingOFF-state (Vd= 1.0 V, Vg=

0.0 V) potential contours and ON-state (Vd= 1.0 V, Vg= 1.0 V) current

density of (b)–(d) are shown in (b’)–(d’) and (b”)–(d”), respectively. All cross-sectional figures ofOFF-state potential contours andON-state current density distributions are extracted at 1 nm below 12 A◦EOT gate oxide.

shown in Fig. 7(b’)–(d’) and (b”)–(d”), which clearly shows

that the distributions of the electrostatic potential and current

density are closely related to the dopant arrangements within

the cross-sectional area beside the source side, as shown in

Fig. 7(b)–(d).

Based on experimental data and the discrete modeling of

20-nm gate with 12 A

EOT, 8 A

EOT seems an effective way

for 15-nm-gate CMOS to mitigate the increase of the

RDD-induced V

variation. With the same approach (shown in Fig. 1)

for generating discrete dopant channels, Fig. 8(a) shows 343

subcubes of (15 nm)

derived from (105 nm)

cubes with

5E18 cm

doping. Fig. 9 shows the Ion–Ioff

characteristics

and the V

distribution of these cases with 12 A

and 8 A

EOT.

The case of 8 A

EOT shows a tighter V

scattering.

Further-Fig. 8. (a) 5E18 cm−3 doped (105 nm)3 _{cube with 343 subcubes of}

(15 nm)3_{. Dopants inside the subcubes range from (c) 7 to (b) 27, with}

(d) the average number of 17 and one standard deviation of 4.

more, as the channel dopants could only be seven at the 3σ

edge, as shown in Fig. 8(c), we herein propose using a higher

work function gate to increase its intrinsic electrostatic potential

barrier height, as shown in Fig. 10(c), to prevent

source-to-drain punch-through at the

-state, as shown in Fig. 10(b).

Thus, σV

can be maintained while L

scales down to

15 nm from 20 nm, as summarized in Table II. It has been

known that σV

is proportional to the oxide thickness [5],

[15]; that is, σV

= (qtox/ε

)

N

W

/4LW , where ε

is

the permittivity of the gate oxide, and W

is the width of

the depletion layer under the gate. In the examination for the

15-nm-gate CMOS, when the EOT changed from 12 A

to 8 A

(1.5 times smaller), the σV

was reduced from 54 mV to

41 mV (1.32 times smaller), which conformed to the expression

of σV

. Although the advanced devices, such as double-gate or

surrounding-gate structures [3], [10], or the epitaxial channels

[13], [14] can reduce the fluctuation, these approaches are much

more complicated and still require the EOT’s improvement to

some degree for the good suppression of σV

.

IV. C

The RDD-induced σV

for 20-nm-gate planar CMOS

de-vices has been experimentally extracted and in good agreement

with the newly developed 3-D discrete dopant

characteriza-tion. An average of 40 dopants randomly distributed in the

channel region give rise to σV

of 40 mV. The

devel-oped scheme outlooks that seven dopants under 15-nm gate

at the 3σ edge will occur, and 8 A

EOT, in addition to the

work-function-modulated metal gate, can suppress the increase

1454 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008

Fig. 9. (a) Ion–Ioffcharacteristics and (b) Vtsversus channel dopants of the

discrete doped 15-nm gates with EOT = 12 A◦(solid triangle) and 8 A◦(open circle). The gate work function is 4.22 eV in the simulation.

Fig. 10. Cross-sectional OFF-state electrostatic potential contours of two extreme cases in 15-nm channels (W = 15 nm and EOT = 8 A◦) with (a) 27 dopants and ΦN= 4.05 eV, (b) seven dopants and ΦN= 4.05 eV, and

(c) seven dopants and ΦN= 4.22 eV, all at 1 nm below the gate oxide.

TABLE II

SUMMARY OF THEDISCRETEDOPANTFLUCTUATED20-nm-AND 15-nm-GATEPLANARCMOS TRANSISTORS

of the σV

for realizing manufacture with such gate length

scaling.

A

The authors would like to thank the managerial and

in-strumental supervision to deploy the development work at

Taiwan Semiconductor Manufacturing Company, Hsinchu,

Taiwan, R.O.C.

R

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Yiming Li (M’02) received the B.S. degree in ap-plied mathematics and electronics engineering, the M.S. degree in applied mathematics, and the Ph.D. degree in electronics from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1996, 1998, and 2001, respectively.

In 2001, he was an Associate Researcher with the National Nano Device Laboratories (NDL), Taiwan, and an Assistant Professor with the Microelectronics and Information Systems Research Center (MISRC), NCTU, where he was engaged in the field of com-putational science and engineering, particularly in the modeling, simulation, and optimization of nanoelectronics and very large scale integration (VLSI) circuits. In 2002, he was a Visiting Assistant Professor with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst. From 2003 to 2004, he was a Research Consultant with the System on a Chip (SOC) Technology Center, Industrial Technology Research Institute, Hsinchu. From 2003 to 2005, he was the Director of the Departments of Nanodevice and Computational Nanoelectronics, NDL. In 2004, he was an Associate Professor with the MISRC, NCTU. He is currently an Associate Professor with the Department of Communication Engineering, NCTU, and an Adjunct Professor with the Institute of Management of Technology, NCTU. He is the Deputy Director of the Modeling and Simulation Center of NCTU and conducts the Parallel and Scientific Computing Laboratory, NCTU. He has authored or coauthored over 120 research papers appearing in international book chapters, journals, and conference proceedings. His current research areas include com-putational electronics and physics, physics of semiconductor nanostructures, device modeling, parameter extraction, VLSI circuit simulation, development of technology computer-aided design (TCAD) and electronic CAD (ECAD) tools and SOC applications, bioinformatics and computational biology, ad-vanced numerical methods, parallel and scientific computing, optimization techniques, and computational intelligence.

Dr. Li is a member of Phi Tau Phi, Sigma Xi, the American Physical Society, the American Chemical Society, the Association for Computing Machinery, the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Society for Industrial and Applied Mathematics. He is included in Who’s Who in the World. He has served as a Reviewer, Guest Associate Editor, and Guest Editor for many international journals. He has organized and served on several international conferences and was an Editor for the Proceedings of International Conferences. He has served as a Reviewer for the IEEE TRANSACTIONS ON NANOTECHNOLOGY, the IEEE TRANSACTIONS ONMICROWAVETHEORY ANDTECHNIQUES, the IEEE TRANSACTIONS ON EVOLUTIONARYCOMPUTATION, the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, the IEEE ELECTRONDEVICELETTERS, and the IEEE TRANSACTIONS ONELECTRON DEVICES. He was the recipient of the 2002 Research Fellowship Award presented by the Pan Wen-Yuan Foundation, Taiwan, and the 2006 Outstanding Young Electrical Engineer Award from the Chinese Institute of Electrical Engineering, Taiwan.

Shao-Ming Yu received the B.S. and M.S. degrees in computer and information science in 2002 and 2004, respectively, from the National Chiao Tung University (NCTU), Taiwan, R.O.C., where he is currently working toward the Ph.D. degree in the Department of Computer Science.

His research interests focus on the modeling and simulation of semiconductor nanodevices, parallel and scientific computation, evolutionary algorithms, and design optimization.

Jiunn-Ren Hwang received the B.S. degree in elec-trophysics from the National Chiao Tung Univer-sity, Hsinchu, Taiwan, R.O.C., in 1986, the M.S. degree in applied physics from the National Tsing Hua University, Hsinchu, in 1988, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in 1996.

He is currently a Manager with the Exploratory Research Division, Department of Research and De-velopment, Taiwan Semiconductor Manufacturing Company, Hsinchu. His current interest is on the development of FinFET devices for the applications of N22 SRAM and logic devices. He has authored or coauthored several papers in IEDM, VLSI technol-ogy, and IRPS conferences. He has been awarded over 20 U.S. patents in the fields of semiconductor devices and manufacturing process. His recent research works also involve strain silicon technology, advanced metal gate/high-K devices, bulk-FinFET SONOS Flash, and CMOS variability in the 65-nm regime and beyond.

Fu-Liang Yang received the B.S. degree in materials science and engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1989, and the Ph.D. degree in materials science and engineering from Cambridge University, Cambridge, U.K., in 1994.

From 1994 to 2000, he was with Vanguard, where he worked on DRAM process and device develop-ment. From 2000 to 2006, he managed a department in Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, with research focuses on novel transistor architecture and process technologies for sub-32-nm node logic and nonvolatile memory. Since January 2007, he has conducted a phase-change memory program forNAND/NORFlash replacement in TSMC. He has authored or coauthored over ten publications in IEDM, Symposium on VLSI Technology, and IEEE journals. He is the holder of more than 100 US patents in advanced CMOS devices and dynamic/static/nonvolatile memory technologies.

Dr. Yang received the Outstanding Young Engineer Award from the Chinese Institute of Engineering in 2004. He was the recipient of TSMC’s 2003 Best Invention Disclosures Award and the 2004 Innovation Award. He is entitled TSMC Academician of TSMC Academy since 2004.