Temperature Coefficient of Poly-Silicon TFT and Its
Application on Voltage Reference Circuit With
Temperature Compensation in LTPS Process
Ting-Chou Lu, Student Member, IEEE, Hsiao-Wen Zan, Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
Abstract—The temperature coefficient (TC) of n-type
polycrys-talline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage ref-erence circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/◦C, between 25 ◦C and 125◦C. The proposed voltage reference circuit with temperature compensation can be applied to design precise ana-log circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels.
Index Terms—System on glass, system on panel, temperature
coefficient (TC), thin-film transistor (TFT), voltage reference circuit.
I. INTRODUCTION
P
OLYCRYSTALLINE silicon thin-film transistors (poly-Si TFTs) with the increased carrier mobility have been widely used in active-matrix liquid crystal displays (AMLCDs), which integrated the corresponding peripheral driving circuitry on panel [1], [2]. The CPU, memory, timing controller, digital-to-analog converter, and driving buffer had been implemented on glass substrate with the low-temperature poly-Si (LTPS) TFT process. LTPS AMLCDs integrated with driver andcon-Manuscript received March 13, 2008; revised July 1, 2008. Current version published September 24, 2008. This work was supported in part by the National Science Council, Taiwan, R.O.C., under Project NSC96-2221-E-009-127-MY2, by the AU Optronics Corporation, Taiwan, and by the Ministry of Economic Affairs, Taiwan, under Project MOEA-96-EC-17A-O7-S1-046. The review of this paper was arranged by Editor H.-S. Tae.
T.-C. Lu is with the Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
H.-W. Zan is with the Display Institute, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
M.-D. Ker was with the Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. He is now with Depart-ment of Electronics Engineering, I-Shou University, Kaohsiung 804, Taiwan, R.O.C. (e-mail: mdker@ieee.org).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2008.2003087
trol circuits on glass substrate have been practically applied in portable systems, such as mobile phone, digital camera, notebook, etc. [3], [4]. However, even with the advanced crys-tallization technologies such as the excimer laser annealing (ELA) or the sequential laser solidification process, it is still observed that the carrier transport in poly-Si TFTs is dominated by the thermionic emission effect [5], [6]. The energy barriers at grain boundaries confine the carrier movement, reduce the field-effect mobility, and make the device characteristics strongly dependent on temperature. As a result, to reduce the impact of temperature variation on the performance of analog circuits in the LTPS process is a very important design challenge.
The voltage reference circuit with temperature compensation is the key design in analog circuits to provide a stable voltage reference with low sensitivity to temperature and supply voltage [7]–[10]. The voltage reference circuit with temperature com-pensation has been widely used in analog and digital circuits, such as DRAM, Flash memory, analog-to-digital converter, and so on. Although the voltage reference circuit with temperature compensation is important to provide a stable output voltage, the LTPS voltage reference circuit with temperature compen-sation on glass substrate was never reported in the past. The conventional CMOS voltage reference circuit with temperature compensation incorporated with BJTs or p-n junction diodes is a great challenge for LTPS process, since the characteristics of the poly-Si BJTs or the poly-Si p-n junction diodes are still unknown or lack of investigation. On the contrary, the characteristics of LTPS TFT devices are strongly dependent on temperature even if the devices are operated in saturation region [5], [6]. Therefore, the LTPS voltage reference circuit with temperature compensation can be realized by using only the LTPS TFT devices on glass substrate.
In this paper, the temperature coefficient (TC) of LTPS TFT devices is first analyzed. The relationship between the activa-tion energy and the TC is investigated. Then, the influences from the laser energy density of the ELA process on the TC of TFT devices are discussed. Followed by the investigation on the channel width effect to the TC, a combination of a narrow-width device and a wide-width device is proposed to generate a positive TC by an appropriate circuit arrangement. The positive TC can be used to compensate the negative TC of TFT devices to achieve the design of a stable output voltage with low sensitivity to the temperature. Finally, this concept has been demonstrated with the first on-glass voltage refer-ence circuit with temperature compensation in LTPS process. 0018-9383/$25.00 © 2008 IEEE
Fig. 1. Traditional voltage reference circuit with temperature compensation in CMOS technology.
Without additional laser trimming after fabrication, the new proposed bandgap voltage reference circuit has been verified on the glass substrate with the output voltage of 6.87 V at room temperature. The TC of voltage reference circuit with temperature compensation output voltage is 195 ppm/◦C under VDD power supply of 10 V when the temperature varies from 25◦C to 125◦C.
II. TRADITIONALVOLTAGEREFERENCECIRCUITWITH TEMPERATURECOMPENSATION INCMOS TECHNOLOGY
A traditional implementation of voltage reference circuit with temperature compensation in CMOS technology is shown in Fig. 1 [11]. In this circuit, the output voltage (VREF) is
the sum of a base–emitter voltage (VEB) of BJT Q3 and the
voltage drop across the upper resistor R2. The BJTs (Q1, Q2, and Q3) are typically implemented by the diode-connected vertical parasitic p-n-p bipolar junction transistors in CMOS process with the current proportional to exp(VEB/VT), where VT(= kT /q) is the thermal voltage. Under constant current
bias, VEBis strongly dependent on VT as well as temperature.
The current mirror is designed to bias Q1, Q2, and Q3 with
identical current. Then, the voltage drop on the resistor R1can
be expressed by VR1= VTln A1 A2 (1)
where A1and A2are the emitter areas of Q1and Q2. It is noted
that VR1 exhibits a positive TC when A1 is larger than A2.
Moreover, since the current that flows through R1is equal to the
current that flows through R2, the voltage drop on the resistor
R2can be expressed by VR2= R2 R1 VTln A1 A2 . (2)
(R2/R1) and summing with VEB, the voltage reference circuit
with temperature compensation would result in a very low sensitivity to temperature. Consequently, if a proper ratio of resistors is kept, the output voltage (VREF) with a very low
sensitivity to temperature can be obtained.
From the analysis on traditional voltage reference circuit with temperature compensation, it is known that the realization of voltage reference circuit with temperature compensation in CMOS process strongly depends on the TC of BJTs (Q1, Q2,
and Q3). In other words, the exponential term exp(VEB/VT) in
the I–V relationship of BJTs makes it possible to obtain a PTAT voltage from the voltage difference of a large-area BJT and a small-area BJT. The voltage across MOSFETs was not sensitive to temperature; thus, MOSFETs were seldom used in volt-age reference circuit with temperature compensation directly. A pure MOSFET voltage reference circuit with temperature compensation was realized only when the MOSFETs are biased in subthreshold region [9]. Unlike the MOSFETs, the charac-teristics of LTPS TFTs are strongly dependent on temperature even when the devices are operated in above threshold region [5], [6]. Therefore, it is expected that the voltage reference circuit with temperature compensation can be realized by using only the LTPS TFT devices on glass substrate.
III. TFT FABRICATION
For device analysis, the typical top-gate coplanar self-aligned n-type poly-Si TFTs with 1.25-μm-length LDD structure in a 3-μm LTPS process were used in this paper. First, the buffer layer was deposited on the glass substrate. Then, the undoped 50-nm-thick a-Si layer was deposited and crystallized by XeCl excimer laser with a laser energy density varied from 340 to 420 mJ/cm2. The recrystallized poly-Si films were patterned into the active islands. Afterward, the 60-nm-thick oxide layer was deposited as the gate insulator. Then, the 200-nm-thick molybdenum was deposited and patterned as the gate electrode. The n− doping was performed self-aligned to the gate electrode. The n+ source/drain region was defined
by an additional mask. The dopants were activated by ther-mal process. After the deposition of nitride passivation and the formation of contact holes, the 550-nm-thick titanium/ aluminum/titanium trilayer metal was deposited and patterned as the metal pads. The channel lengths of TFT devices are all kept as 6 μm while the channel widths are designed from 30 to 6 μm in the on-glass voltage reference circuit with temperature compensation.
Fig. 2. Activation energy as a function of VGSfor diode-connected NTFTs
with W/L of 6 μm/6 μm, 12 μm/6 μm, and 30 μm/6 μm.
IV. MEASUREDRESULTS ANDTEMPERATUREMODEL Since the temperature response of the LTPS devices is mostly influenced by the thermionic emission effect with an activation energy associated with the grain boundary barrier height, the relationship between the activation energy and the TC is first investigated in this paper. As shown in Fig. 2, the activation energy (Ea) extracted from the Arrhenius plot of
the drain current is depicted as a function of the gate bias (VGS). The drain bias (VDS) is equal to VGS for the
diode-connected TFT devices. Devices with three different channel widths are measured in Fig. 2. Devices are fabricated in the same run with identical crystallization laser energy density. It is found that, similar to the three-terminal LTPS devices, Ea
of the diode-connected devices is strongly dependent on VGS.
Under small gate bias, Ea is high. When VGS is increased,
Ea decreases drastically. It is well known that, for the
three-terminal LTPS TFTs, the measured activation energy represents the grain boundary energy barrier of the poly-Si film which is sensitive to the poly-Si thin-film properties [5], [6]. Channel width has no influence on the thin-film properties; thus, devices with different channel widths exhibit similar Eacharacteristics
as those measured in Fig. 2.
Then, to extract the TC, the setup to measure VGS of the
fabricated devices under the bias of three different current levels (1, 10, and 50 μA) is shown in Fig. 3(a). The measured VGS
of the fabricated device with a channel width of 30 μm is shown as a function of temperature in Fig. 3(b). As shown in Fig. 3(b), VGSis decreased while the temperature increases. An
almost linear relationship between VGSand temperature can be
observed in Fig. 3(b), where the slope represents the TC. For the diode-connected NTFT with a channel width of 30 μm under different current levels, the TC is negative. Additionally, the magnitude of TC decreases when the bias current is increased. When the bias current increases from 1, 10, to 50 μA, the TC varies from−6.04, −5.04, to −2.96 mV/◦C. It is noted that for one identical diode-connected device, the increase of bias current gives rise to the increase of operation voltage. As a result, the larger bias current makes the devices operated under larger VGS with smaller Ea and smaller magnitude of TC.
This result clearly demonstrates the relationship between the activation energy and the TC. Furthermore, the aforementioned discussion can be expressed by the following derivation.
Fig. 3. (a) Setup to measure VGSunder the bias of IDS. (b) Relationship
between VGS and temperature under three different current levels (1, 10,
and 50 μA).
For LTPS TFTs, the drain current IDSof devices operated in
saturation region can be expressed as [12], [13] IDS= W 2Lμ0Cox(VGS− VTH) 2exp −VB VT (4) where μ0 is the carrier mobility within the grain, L denotes
the effective channel length, W is the effective channel width, Cox is the gate oxide capacitance per unit area, VTH is the
threshold voltage of TFT device, and VGSis the gate-to-source
voltage of TFT device. VB is the potential barrier at grain
boundaries which is associated with the crystallization quality of the poly-Si film. When the activation energy is extracted from the Arrhenius plot of the drain current, Eais equal to qVB.
Under small VGS, VB is large. When the VGS increases, VB
decreases rapidly. When the device in circuit is operated under small VGS, the drain current IDSof device is dominated by the
exponential term and can be simplified by IDS= W α exp −VB VT (5) where α is only weakly dependent on VGSbut is insensitive to
temperature. Then, the equation of VBcan be derived as
VB= VTln W α IDS =kT q ln W α IDS . (6)
Fig. 4. Dependence between potential barrier of grain boundary VBand
gate-to-source voltage VGSof diode-connected NTFT.
When there is a variation of temperature ΔT , the corresponding variation on VBis ΔVB = kΔT q ln W α IDS . (7)
Fig. 4 shows the measured dependence between potential barrier of grain boundary VB and gate-to-source voltage VGS
of diode-connected NTFT with device dimension W/L of 30 μm/6 μm, whereas the laser energy density is kept at 340 mJ/cm2. As shown in Fig. 4, the variation of VBis related to
the variation of VGS. Assume that the variation of VGS(ΔVGS)
is very small, and a negative linear approximation can be given between ΔVBand ΔVGSas ΔVGS=− 1 mΔVB=− kΔT mq ln W α IDS (8) where m is the absolute slope of the linear approximation between ΔVB and ΔVGS in Fig. 4. Finally, the TC can be
found as TC = ΔVGS ΔT =− k mqln W α IDS =−ΔVB mΔT. (9) Even though the increase of VB accompanies with the increase
of m, the variation of VBcan be more significant than that of m
under a proper design.
The activation energy, as well as the grain boundary barrier, should be related to the grain structure and the grain boundary property. It is therefore presumed that the laser energy density of the ELA process influences the grain structure and affects the TC of the devices. Fig. 5(a) shows the activation energy of the diode-connected devices with the poly-Si film crystallized under different laser energies (340, 400, and 420 mJ/cm2). The channel width of the TFT device studied in Fig. 5(a) is 30 μm. The activation energy is found to be reduced with increasing laser energy density. As a result, the TC of the devices with higher laser energy density is also smaller than those with lower laser energy density, as shown in Fig. 5(b). However, the influence of laser energy density on the TC is not significant. When the laser energy density changes±10%, the TC changes only about±2.75%. The reason can be explained by identifying
Fig. 5. (a) Activation energy as a function of VGS for diode-connected
NTFTs with poly-Si film crystallized by laser energy density as 340, 400, and 420 mJ/cm2. (b) Relationship between V
GSand temperature under identical IDSof 10-μA. Devices W/L are 30 μm/6 μm.
the biasing points of three devices in Fig. 5(a). The operation voltages of three devices under the bias of 10-μA IDS are
indicated by the arrow symbols in Fig. 5(a). It is found that the activation energies of the three biasing points are similar. This makes the TC insensitive to the deviation of the laser energy density in the ELA process. Similar results can be also observed for the devices with small channel width of 6 μm in Fig. 6(a) and (b), where the laser energies for poly-Si film crystallized are also 340, 400, and 420 mJ/cm2.
The influence of the channel width on the TC, however, is found to be significant. When the diode-connected devices are biased under a constant current of 10 μA, VGSof TFT devices
with channel widths of 6 and 30 μm is shown as a function of temperature in Fig. 7, whereas the laser energy density is kept at 400 mJ/cm2. Obviously, the wide-channel-width device ex-hibits more negative TC than the narrow-channel-width device. From Fig. 2, it has been observed that the channel width has only little influence on the device activation energy. However, when all the devices are biased by identical current source, the wide-channel-width devices are operated under small VGS, and
the narrow-channel-width devices are operated under large VGS. When VGSis reduced, the activation energy is drastically
Fig. 6. Activation energy as a function of VGSfor diode-connected NTFTs
with poly-Si film crystallized by laser energy density as 340, 400, and 420 mJ/cm2. (b) Relationship between V
GSand temperature under identical IDSas 10 μA. Devices W/L are 6 μm/6 μm.
Fig. 7. Relationship between VGSand temperature of devices with different
channel widths under identical IDSof 10 μA.
of the TC is significantly enlarged by increasing the channel width. Such a phenomenon can be also explained by (9).
Finally, the TC of the diode-connected NTFT devices biased under a 10-μA current is shown in Fig. 8. The influences of channel width and crystallization laser energy on the TC of the diode-connected NTFT devices are compared. It can be concluded that the influence of ELA laser energy density or
Fig. 8. TC of the diode-connected NTFT devices biased under a 10-μA current source to investigate the influences of channel width and crystallization laser energy on the TC of the diode-connected NTFT devices.
Fig. 9. Implementation of the new proposed voltage reference circuit with temperature compensation in a 3-μm LTPS process.
the poly-Si thin-film property on the TC is relatively small. This makes the voltage reference circuit with temperature com-pensation not sensitive to the deviation of the laser annealing process in the LTPS technology. On the contrary, changing the device channel width can effectively change the TC of the diode-connected device. This enables the designer to modulate the TC of the diode-connected devices easily.
V. APPLICATION ONVOLTAGEREFERENCECIRCUITWITH TEMPERATURECOMPENSATION INLTPS TECHNOLOGY The difference of TCs between the wichannel-width de-vice and the narrow-channel-width dede-vice is very useful if a positive TC can be extracted from the VGSof the
wide-channel-width device to the VGS of the narrow-channel-width device.
This positive TC can be used to compensate the negative TC in the VGSof TFT devices.
A. Implementation
The new proposed voltage reference circuit with temperature compensation designed and fabricated by a 3-μm LTPS tech-nology is shown in Fig. 9. In this circuit, the TFTs M1, M2,
ΔVR1= kΔT mq ln W6 W7 =kΔT mq ln N. (10)
Obviously, ΔVR1is proportional to the absolute temperature
(PTAT). Hence, a PTAT loop is formed by M6, M7, and R1.
The PTAT current variation ΔI1can be written as
ΔI1=
kΔT mqR1
ln N (11)
where N (= W6/W7) is the channel width ratio of M6and M7.
The current mirror, which is composed of M1, M2, and M3,
imposes equal currents in these three branches I1, I2, and I3
of the circuit. The output voltage (VREF) is the sum of a
gate–source voltage of TFT M8 (VGS8) and the voltage drop
across the upper resistor (VR2). Therefore, the output voltage
variation (ΔVREF) of the new proposed voltage reference
circuit with temperature compensation can be expressed as ΔVREF= ΔI3R2+ ΔVGS8=
R2
R1
kΔT
mq ln N + ΔVGS8 (12) where R1and R2are the resistances shown in Fig. 9. The first
item in (12) with positive TC is proportional to the absolute temperature (PTAT), which is used to compensate the negative TC of ΔVGS8. After multiplying the PTAT voltage with an
appropriate factor (proper ratio of resistors) and summing with ΔVGS8, the output voltage of voltage reference circuit with
temperature compensation would result in a very low sensitivity to temperature.
The proposed voltage reference circuit with temperature compensation has been fabricated in a 3-μm LTPS technology. Fig. 10 shows the chip photo of the new proposed voltage reference circuit with temperature compensation fabricated on glass substrate. The chip size of the proposed voltage reference circuit with temperature compensation is 400× 380 μm2. The
resistances R1and R2 implemented by the poly resistance are
also included into the layout. B. Measurement Results
The threshold voltage of TFT devices in a 3-μm LTPS technology is Vthn≈ Vthp≈ 1.25 V at 25◦C. The total gate
area of M6 is 480 μm2, and that of M7 is 80 μm2 in this
fabrication. The resistors in this chip, formed by poly resistors, have minimum process variation to improve the accuracy of resistance ratio. The power supply voltage VDD is set to 10 V,
Fig. 10. On-glass circuit photograph of the new proposed voltage reference circuit with temperature compensation fabricated in a 3-μm LTPS process.
Fig. 11. Measured output voltage VREFof the fabricated voltage reference
circuit with temperature compensation under different resistance of R2without
laser trimming after fabrication.
and the total operating current is 8.97 μA. The measured results of the output voltage VREF from 25 ◦C to 125◦C are shown
in Fig. 11, where the R2 is drawn with different values in
the test chips. As R2 is equal to 500 kΩ, the measured TC
of the fabricated voltage reference circuit with temperature compensation on glass substrate is around 195 ppm/◦C without laser trimming after fabrication, whereas the output voltage (VREF) is kept at 6.87 V.
VI. CONCLUSION
The TC of TFT devices in LTPS technology is strongly de-pendent on the activation energy of the devices. With a suitable control, higher activation energy gives rise to higher absolute value of the TC. The influence of the laser energy density in ELA process on the TC of the devices is not significant. On the other hand, the bias current level and the channel width have a strong impact on the device TC. As a result, the TC of devices can be controlled by regulating the channel width of the devices. With an appropriate circuit design, a positive TC can be generated by using the voltage drop between devices
that have different TCs (different channel widths). Then, the positive TC can be used to compensate the negative TC from the devices. The first voltage reference circuit with temperature compensation has been successfully verified in a 3-μm LTPS process. The measured reference output voltage is 6.87 V with a TC of 195 ppm/◦C. The proposed voltage reference circuit with temperature compensation consumes an operating current of only 8.97 μA under the supply voltage of 10 V on glass substrate. This new voltage reference circuit with temperature compensation can be used to realize precise analog circuits in LTPS process for system-on-glass applications.
ACKNOWLEDGMENT
The authors would like to thank C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, W.-M. Huang, K.-C. Lin, C.-C. Shih, C.-C. Chiu, and Dr. C.-Y. Liu for their valuable technical suggestions and the AU Optronics Corporation, Taiwan, R.O.C., for the fabrica-tion support of on-glass devices and circuits.
REFERENCES
[1] H. G. Yang, S. Fluxman, C. Reita, and P. Migliorato, “Design, mea-surement and analysis of CMOS polysilicon TFT operational am-plifiers,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 727–732, Jun. 1994.
[2] T. Matsuo and T. Muramatsu, “CG silicon technology and development of system on panel,” in Proc. SID Tech. Dig., 2004, pp. 856–859.
[3] Y. Nakajima, Y. Kida, M. Murase, Y. Toyoshima, and Y. Maki, “Latest development of ‘System-on-Glass’ display with low tempera-ture poly-Si TFT,” in Proc. SID, Dig. Tech. Papers, 2004, vol. 21, pp. 864–886.
[4] Y. Nakajima, “Ultra-low-power LTPS TFT-LCD technology using a multi-bit pixel memory circuit,” in Proc. SID Tech. Dig., 2006, pp. 1185–1188.
[5] M. Jacunski, M. Shur, A. Owusu, T. Ytterdal, M. Hack, and B. Iniguez, “A short-channel DC spice model for polysilicon thin-film transistors including temperature effects,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1146–1158, Jun. 1999.
[6] A. Hatzopoulos, D. Tassis, N. Hastas, C. Dimitriadis, and G. Kamarinos, “On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain bound-aries,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1727–1733, Aug. 2005.
[7] K.-N. Leung and K.-T. Mok, “A sub-1-V 15-ppm/◦C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE
J. Solid-State Circuits, vol. 37, no. 4, pp. 526–530, Apr. 2002.
[8] K.-N. Leung, K.-T. Mok, and C.-Y. Leung, “A 2-V 23-μA 5.3-ppm/◦C curvature-compensated CMOS bandgap voltage reference,” IEEE J.
Solid-State Circuits, vol. 38, no. 3, pp. 561–564, Mar. 2003.
[9] G. Vita and G. Iannaccone, “A sub-1-V, 10-ppm/◦C, nanopower volt-age reference generator,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1536–1542, Jul. 2007.
[10] M.-D. Ker and J.-S. Chen, “New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 667–671, Aug. 2006.
[11] G. Rinconmora, Voltage Reference From Diodes to Precision High-Order
Bandgap Circuits. Hoboken, NJ: Wiley, 2002, pp. 23–28.
[12] K. Mourgues, A. Rahal, T. Mohammed-Brahim, M. Sarret, J. P. Kleider, C. Longeaud, A. Bachrouri, and A. Romano-Rodriguez, “Density of states in the channel material of low temperature polycrystalline silicon thin film transistors,” J. Non-Cryst. Solids, vol. 266–269, pp. 1279–1283, May 2000.
[13] Y. Kuo, Thin Film Transistors: Materials and Processes, vol. 2. Norwell, MA: Kluwer, 2004, pp. 35–38.
Ting-Chou Lu (S’08) received the B.S. degree
from the National Chung-Cheng University, Chiayi, Taiwan, R.O.C., in 2005 and the M.S. degree in the National Chiao Tung University, Hsinchu, Taiwan, in 2008, where he is currently working toward the Ph.D. degree in the Nanoelectronics and Gigascale Systems Laboratory.
His main research interest is the design of analog circuits on glass substrate for thin-film transistor panel applications.
Hsiao-Wen Zan (M’05) received the B.S. degree in
electrical engineering from the National Taiwan Uni-versity, Taipei, Taiwan, R.O.C., in 1997 and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 1999 and 2003, respectively.
She then joined as an Assistant Professor with the Department of Photonics, National Chiao Tung University, where she is currently with the Dis-play Institute. Her current research interests include Si-based thin-film transistor devices and circuits, organic polymer thin-film devices, bio/chemical sensors, and silicon thin-film solar cells.
Ming-Dou Ker (S’92–M’94–SM’97–F’08) received
the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1993.
He was the Department Manager with the VLSI Design Division, Computer and Communication Research Laboratories, Industrial Technology Re-search Institute, Hsinchu. Since 2004, he has been a Full Professor with the Nanoelectronics and Giga-scale Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University. From 2006 to 2008, he served as the Director of Master Degree Program with the College of Electrical Engineering and Computer Science, National Chiao Tung University, as well as the Associate Executive Director of the National Science and Technology Program on System-on-Chip (NSoC Office), Taiwan. In 2008, he served as the Chair Professor and the Vice President of I-Shou University, Kaohsiung, Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 300 technical papers in international journals and conferences. He has proposed many inventions to improve the reliability and quality of integrated circuits, which have been granted with 134 U.S. patents and 141 R.O.C. (Taiwan) patents. He had been invited to teach and/or to consult the reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis.
Prof. Ker has served as a member of the Technical Program Committee and the Session Chair of numerous international conferences. He served as the Associate Editor for the IEEE TRANSACTIONS ONVLSI SYSTEMS. He has been selected as the Distinguished Lecturer in the IEEE Circuits and Systems Society (for year 2006–2007) and in the IEEE Electron Devices Society (since 2008). He was the President of Foundation in the Taiwan ESD Association. In 2005, one of his patents on ESD protection design has been awarded with the National Invention Award in Taiwan. In 2008, he has been elevated as an IEEE Fellow “for his contributions to the electrostatic protection in integrated circuits and the performance optimization of VLSI microsystems.”
