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Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate
High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit
View the table of contents for this issue, or go to the journal homepage for more 2012 Jpn. J. Appl. Phys. 51 04DC08
(http://iopscience.iop.org/1347-4065/51/4S/04DC08)
Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate
High-
/Metal Gate Complementary Metal–Oxide–Semiconductor
Device and Inverter Circuit
Yiming Liand Hui-Wen ChengParallel and Scientific Computing Laboratory, Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan Received September 26, 2011; accepted December 28, 2011; published online April 20, 2012
This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-/metal gate (HKMG) metal–oxide–semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO2/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device’s inversion layer cannot effectively screen potential’s variation; thus, devices still have noticeable fluctuation of gate capacitance (CG) under high gate bias. The cutoff frequency decreases as
increasing the number of ITs owing to the decreasing transconductance and increasingCG. Decreasing on-state current and increasingCGfurther
result in increasing intrinsic gate delay time () when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal–oxide–semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs’ fluctuations are increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices. # 2012 The Japan Society of Applied Physics
1. Introduction
Silicon-based devices are scaled down continuously accord-ing to Moore’s law.1)More and more challenges have to be overcome for advanced device technologies; one of them is the management of process variation and random fluctua-tion.2) With device scaling, various randomness effects resulting from the random nature of manufacturing process, such as ion implantation, diffusion, and thermal annealing, have induced significant characteristic fluctuations in nanometer scale complementary metal–oxide–semiconduc-tor (nano-CMOS);3–7) in particular, threshold voltage (Vth)
fluctuation is crucial for design window, noise margin, yield, stability, and reliability of nano-CMOS integrated circuits. High-/metal gate (HKMG) technology for maintaining device characteristics and suppressing device’s intrinsic parameter fluctuation is introduced.8–19)However, emerging fluctuation source, the random interface traps (ITs) at high-/silicon interface degrades device characteristic.20–31) Recently, one-dimensional (1D) and 2D random ITs at high-/silicon interface were proposed for DC characteristic fluctuation simulation of sub-45-nm CMOS devices.9,16,21) But much less attention has been paid to device’s AC and transfer-characteristic fluctuations of a nano-CMOS inverter circuit caused by random ITs. In addition, randomness of IT’s positions in devices makes the fluctuation of gate capacitance of a device nonlinear.
In this work, DC/AC and transfer-characteristic fluctua-tions, induced by random ITs at HfO2/Si interface, of 16-nm-gate HKMG metal–oxide–semiconductor field effect transistor (MOSFET) device and inverter circuit are studied by using an experimentally calibrated 3D device simulation. Because random ITs exhibit a spike of local energy barrier and trap majority carriers, for the N-MOSFETs, electrons are trapped by acceptor-like traps and result in high Vth.
Therefore, all fluctuated drain current–gate voltage (ID–VG)
curves are shifted right; similarly, the fluctuated ID–VG
curves are shifted left for the P-MOSFETs. The fluctuation of drain current is pronounced resulting from random ITs at sub-threshold regions; however, it is reduced as VGincreases
due to inversion charges filling the interface states and minimizing their impact. Nevertheless, the existing random ITs at the HfO2/Si interface weakens the screening effect, in contrast to random dopant fluctuation (RDF).5)For the same number of ITs, simulated device samples with similar Ionbut
different Ioffmay disclose the effect of random ITs’ position
on the off-state potential; in particular, ITs near source end alter potential barrier significantly. Large number of random ITs not only implies high density of ITs at HfO2/Si interface but also scatters high-field transport of inversion-layer carriers; consequently, it raises Vth and impacts the on-state
conducting current path, in spite of maintaining similar off-state current. In addition, drain-induced barrier lowering (DIBL), transconductance (gm), output resistance (ro), and
gate capacitance (CG)1) are governed by random ITs; the
cutoff frequency decreases owing to the decreasing gm and
increasing CG. The intrinsic gate delay time () increases
because of decreasing the on-state current and increasing CG, as the number of ITs increases. The noise margin
fluctuation (NM) of a CMOS inverter circuit is thus analyzed and compared with the results of RDF. Even for cases with the same number of random ITs, NMs are still quite different due to the different distribution of random ITs. Both NM high (NMH) and NM low (NML) increase as
the number of random ITs increases. Because NM is directly proportional to Vth, NM is also increased due to
the more sources of fluctuation at HfO2/Si interface of HKMG devices. Compared with the results of RDF, the random ITs-induced NML fluctuation, NML,ITs, is about
20.3 mV which is less than the RDs-induced NML
fluctua-tion, NML,RDs of 35.0 mV. Similarly, RDs-induced NMH
fluctuation, NMH,RDs, is 20.1 mV which is also less than
NMH,RDs of 30.0 mV. Furthermore, the findings of
combined RDs and random ITs (denoted as RDs+ITs) simulation indicate RDF is a major part of NM of 16-nm-gate HKMG CMOS inverter circuit.
E-mail address: [email protected]
This paper is organized as follows. In x2, we brief the random ITs fluctuation (ITF) simulation procedure. In x3, we discuss DC/AC and transfer-characteristic fluctuations of the studied device and circuit. Finally, we draw conclusion and suggest future work.
2. ITF Simulation Procedure
The devices we studied are the 16-nm-gate MOSFETs (width: 16 nm) with amorphous-based titanium nitride/ hafnium oxide (TiN/HfO2) gate stacks and an effective oxide thickness (EOT) of 0.8 nm, as shown in Fig. 1(a). We first calibrate the nominal DC characteristic of the studied HKMG devices according to ITRS roadmap for low operating power, which was experimentally quantified in our recent study.32)Note that all adopted material properties,
device settings, and characteristics follow our recent study,8) where the threshold voltage of the 16-nm-gate N-MOSFETs is equal to 250 mV (250 mV for P-MOSFETs). For ITF simulation, we first randomly generate 753 ITs in a large 2D plane, where the size of plane is (224 nm)2, as shown in Fig. 1(b); thus, the concentration in the entire plane is about 1:5 1012cm2 and the equivalent total number of
generated traps follows the Poisson distribution. The entire plane is then partitioned into many sub-planes (the size of
each sub-plane is 16 16 nm2), where the number of random traps in all sub-planes (area: 16 16 nm2) may vary from 0 to 8 and the average number is 4. To perform 3D device simulation with 2D ITF for each randomly generated device sample, we assume each IT has same area of (2 nm)2, as shown in Fig. 1(a), and assign each individual IT’s density within its area. Each IT’s density on the sub-plane is randomly assigned according to the relation of trap’s density versus trap’s energy.9,22,23) The procedure is repeated until all sub-regions are assigned; thus, the entire IT’s density at HfO2/Si interface of each device vary from 0:8 1010 to 6 1011eV1cm2.24,25,33–36) Therefore, 196 randomly generated 3D device samples with 2D random ITs at HfO2/ Si interface are simulated to assess the influence of ITF.
Owing to lack of well-established compact models for the 16-nm-gate CMOS devices, by using the coupled device-circuit simulation technique,3–5)the circuit level fluctuations are estimated for the CMOS inverter circuit, as shown in Fig. 1(c), where the flowchart of coupled device-circuit simulation is shown in Fig. 1(d). To estimate the inverter’s NM property, electrical characteristics of each randomly generated device in the tested circuit are first calculated by the 3D device simulation. The obtained result is then used as devices’ terminal characteristics in the coupled device-Substrate S Y X D W = 16 nm 16 nm
(c)
Interface Trap 2 nm 2 nm 1.5 1012cm-2; 753 random ITs in (224 nm)2region Lg= 16 nm224 nm
224 nm
Vout Vin VDD PMOS Mean = 4 Random ITs in (16 nm)2sub-region 40 30 20 10 0 Histogram (Number) 50 0 1 2 3 4 5 6 7 8 Each IT ’s density (eV -1cm -2) Substrate S D 16 nm(d)
Lg= 16 nm High-κκ(a)
Substrate S D High-κ Substrate S D High-κ Substrate S D High-κ Substrate S D High-κ Substrate S D High-κ Substrate S D High-κ NMOS 3D Device Simulation Device Characteristics CMOS Inverter Circuit Formulation Coupled Device-Circuit Simulation V V+ΔV V Meets Final Value? Output Device and Circuit Characteristics Yes No Nodal Voltage V = 0(b)
Fig. 1. (Color online) (a) The simulated structure and source of random interface traps (pink dots: each IT has2 2 nm2size) appearing at the interface of HfO2/Si film. (b) Simulation setting for fluctuation of random ITs. We first generate 753 acceptor-like traps for N-MOSFETs in a large plane, where the corresponding trap’s concentration in the plane is around1:5 1012cm2and the total number of generated traps follows the Poisson distribution. The energy of each random interface trap on the plane is assigned according to a distribution of trap’s density.9,22,23)Then, the entire plane is partitioned into
sub-planes (size:16 16 nm2), where the number of random interface traps in every sub-plane may vary from 1 to 8 and the average number is 4. Consequently, the density of interface traps at the16 16 nm2interface of HfO2/Si film is varying from0:8 1010to6 1011eV1cm2. (c) The totally random generated N- and P-MOSFET devices are simulated for noise margin calculation of 16-nm CMOS inverter circuit using coupled device-circuit simulation. (d) Flow of coupled device-circuit simulation.
Y. Li and H.-W. Cheng Jpn. J. Appl. Phys. 51 (2012) 04DC08
circuit steady-state simulation. The nodal equations of the tested inverter circuit are formulated and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit and device equations), which are solved simultaneously to obtain the circuit transfer characteristics. We notice that the device characteristics obtained by device simulation, such as distributions of potential and current density, are input in the inverter circuit simulation through device’s contact terminals. Notably, to explore influences of combined RDs and random ITs on NMs of CMOS inverter circuit, the random dopants and random ITs are generated respectively, and then randomly positioned into device channel at HfO2/Si interface of each device simultaneously. Simulation method of RDF follows the details appearing in our earlier work.3–5,32)
3. Results and Discussion
We first compare the random ITs-induced Vth (Vth,ITs)
calculated by the 1D and 2D approaches, as listed in Table I, the 1D calculation (Vth,ITs¼ 15 mV) is lower than that of
our calculation owing to without considering random distribution of ITs along finite width direction in the 1D simulation. Figure 2(a) shows the totally random ITs-induced fluctuations of ID–VGcurves of the 16-nm-gate
N-MOSFETs, where the red solid line indicates the nominal case (i.e., the 3D device simulation with zero random ITs) and the gray dashed lines are all fluctuated cases. Figures 2(b) and 2(c) are extracted on-state current (Ion)
and off-state current (Ioff) as functions of the number of ITs,
where each symbol shows each random IT-fluctuated result. As shown in Fig. 2(d), the value of Vthis determined from a
current criterion that the drain current larger than 107 ðW=LÞA, where L and W are the gate length and width, respectively. The Vth increases (and then the on-/off-state
current decreases accordingly) as the number of ITs increases. The simulated Vth,ITsis 26.3 mV which is smaller
than the results of RDF (Vth,RDs¼ 43 mV). The random
ITs-position-induced different fluctuations of characteristics in spite of the same number of ITs, as marked by open bar in inset of Fig. 2(d), where the magnitude of the spread characteristics increases as the number of ITs increases. To focus on the impact of random ITs on physical characteristic, Fig. 3(a) shows Ioff–Ion plot of the 16-nm-gate N-MOSFETs
induced by random ITs; light-pink dots are for device whose number of random ITs is equal or greater than 4, and the rest Table I. Comparison of Vthand CGcalculated by 1D IT’s method and
our approach for the 16-nm N-MOSFETs.
Vth CG(10 3fF) (mV) at VG¼ 0:4 V at VG¼ 0:8 V 1D ITs Method 15 0.02 0.22 This work 26.3 0.21 0.28 Number of ITs 0 2 4 6 8 10 Ion (A) 2x10-6 3x10-6 4x10-6 5x10-6 6x10-6 7x10-6 8x10-6 VG (V) 0.0 0.2 0.4 0.6 0.8 ID (A) 10-10 10-9 10-8 10-7 10-6 10-5 N-MOSFET Vthfluctuation Iofffluctuation Number of ITs Ioff (A) 0 1x10-9 2x10-9 3x10-9 4x10-9 5x10-9 6x10-9 Number of ITs Vth (V) 0.20 0.25 0.30 0.35 0.40
Random ITs’ number effect Random ITs’ position effect (b) (a) (c) (d) 0 2 4 6 8 10 0 2 4 6 8 10 Ionfluctuation
Fig. 2. (Color online) (a) The totally random ITs-induced fluctuations of ID–VGcurves of the 16-nm-gate N-MOSFET, where the red solid line indicates the nominal case and the gray dashed lines are all fluctuated cases. (b) Ion, (c) Ioff, and (d) Vthare extracted fluctuations as a function of the number of ITs, where each symbol shows each random IT-fluctuated result.
Off-state Potential Distribution (VG= 0 V; VD= 0.8 V)
Ion (A)
2e-6 3e-6 4e-6 5e-6 6e-6 7e-6 8e-6 I of f (A) 0 1e-9 2e-9 3e-9 4e-9 5e-9 6e-9 # of Random ITs < 4 16 nm 16 nm D 16 nm 16 nm S D 8 ITs 16 nm 16 nm S D 4 ITs (a) (b) 4 ITs (c) (d) S S D S D -1.0 0.0 (eV) S D 16 nm 16 nm S D 4 ITs 16 nm 16 nm S D 4 ITs 16 nm 16 nm S 8 ITs (b’’) (d’’) (c’’)
4 ITs 4 ITs 8 ITs
(b’) (d’) (c’)
D
S
D
# of Random ITs > 4
Off-state Potential Distribution (VG= 0 V; VD= 0.8 V)
On-state Current Distribution (VG= VD= 0.8 V)
On-state Current Distribution (VG= VD= 0.8 V)
Fig. 3. (Color online) (a) Plot of Ioff–Ionof the 16-nm-gate N-MOSFET induced by random ITs. Light pink dots are for the number of random ITs is equal or greater than 4 and the rest parts are marked as dark pink. Three cases are selected among 196 simulations to show different random number and position effects. (b) Among four ITs, one IT near source end. (c) Eight ITs are randomly distributed at the interface of HfO2/Si film and they are a little bit away from source end. (d) Among four ITs, three ITs are near source end. (b0)–(d0) are their off-state surface potential (VG¼ 0 V and VD¼ 0:8 V) with respect to (b)–(d), respectively. (b0)–(d0) are their corresponding on-state surface current density (VG¼ VD¼ 0:8 V).
parts are marked as dark-pink dots. Three cases are selected among 196 simulations to demonstrate random number-and-position associated local repulsive coulomb field as well as disturbed surface current conducting path. Figures 3(b) and 3(d) are the two cases which have same number of ITs (4 ITs). These two devices have similar Ion owing to similar
current conduction areas, as shown in Figs. 3(b00) and 3(d00). However, their Ioffare different because random ITs near the
source end locally results in relatively higher local spike of potential barriers and thus raises Vth, compared with ITs
appearing in the drain end [Fig. 3(b0)]. Random number effect of ITs at HfO2/Si interface are major obstacles to electrons and disturbed surface current conducting path, which is explained in Figs. 3(c) and 3(d). The two cases have similar Ioff but different Ion owing to random number
effect. As shown in Figs. 3(c00) and 3(d00), although 8 ITs in Fig. 3(c) positioning away from the source end have weakened interaction with mobile electrons due to the relatively larger drift velocity and electron transport energy, many local spikes of potential barriers still effectively impede surface current conduction which is even stronger than that of ITs appearing in the source end, as shown in Fig. 3(d00). Thus, the device with random ITs of Fig. 3(c) has minimal Ion, compared with the case of Fig. 3(d). The
random ITs-fluctuated DIBL effect is pronounced for the 16-nm-gate N-MOSFETs, as shown in Fig. 4(c). In the weak inversion region there is a potential barrier at the channel region owing to a balance between drift and diffusion current. The barrier height decreases as VD increases, as
shown in Fig. 4(a); it results in an increased ID, as shown in
Fig. 4(b), which is controlled not only by VG, but also by VD.
The DIBL effect could be observed through the ID–VG
curves of a device under the linear (VD¼ 0:05 V) and
saturated (VD¼ 0:8 V) cases, as shown in Fig. 4(b), deriving
by the lateral shift of Vthdivided the difference of VDin inset
of Fig. 4(c). Figure 4(c) shows the ITs-fluctuated DIBL
characteristic of the 16-nm-gate N-MOSFETs, the DIBL decreases as the number of ITs increases due to ITs decrease the probability of electric-field lines penetrating from drain to source. The tendency of increasing fluctuation of DIBL follows Vth as the number of ITs increases. The maximum
gm (gm,max) and the output resistance (ro) of transistor as
functions of the number of ITs are shown in Figs. 5(a) and 5(b). Since gm varies with (VGS Vth), gm,max decreases
owing to Vth is increased with increasing the number of
ITs; similarly, rois increased as the number of ITs increases.
The random position of ITs results in rather different fluctuations of characteristics despite the same number of ITs. Furthermore, the magnitude of the spread characteristics increases as the number of ITs increases.
Gate capacitance of MOSFET devices is one of important AC parameters, comparison between the 1D ITF simulation and our approach is listed in Table I for VG¼ 0:4 and 0.8 V.
VGcalculated by 1D method is underestimated. Figure 6(a)
shows the random ITs-fluctuated gate capacitance–gate voltage (CG–VG); where the lateral shift of CG is a result
of the variation of Vth; and the substantially altered slopes of
CG–VG curves can be attributed to the random-ITs-position
Lateral Position from Source to Drain (nm)0 5 10 15 20
Surface Potential (V) 0.4 0.6 0.8 1.0 1.2 1.4 VD = 0.05 V VD = 0.80 V Barrier Lowering Source Drain Lg VG (V) 0.0 0.2 0.4 0.6 0.8 ID (A) 10-10 10-9 10-8 10-7 10-6 10-5 VD = 0.80 V VD = 0.05 V ΔVth (a) (b) Number of ITs 0 2 4 6 8 10 DIBL (mV/V) 200 225 250 275 300 D th V V DIBL Δ Δ = (c)
Fig. 4. (Color online) (a) Plot of the surface potential of 16-nm-gate nominal N-MOSFET for VG¼ 0:8 V and VD¼ 0:05 and 0.8 V (linear and saturated cases). (b) Plot of two ID–VGcurves for VG¼ 0:8 V and VD¼ 0:05 and 0.8 V (linear and saturated cases). (c) DIBL versus the number of random ITs.
Number of ITs 0 2 4 6 8 10 gm,max (S) 12.5x10-6 15.0x10-6 17.5x10-6 20.0x10-6 22.5x10-6 th GS g on m V V V I g = − (a) Number of ITs 0 2 4 6 8 10 ro (Ohm) 104 105 106 ( )2 1 th GS D ds o V V I V r − = (b)
Fig. 5. (Color online) (a) gm,max(b) and rowith respect to the number of random ITs for the 196 random ITs-fluctuated N-MOSFETs.
VG (V) 0.0 0.2 0.4 0.6 0.8 CG (fF) 0.003 0.004 0.005 0.006 0.007 0.008 0.009 N-MOSFET VG (V) 0.0 0.2 0.4 0.6 0.8 Normalized C G Fluctuation (%) 0 2 4 6 8 100% Averaged G× G C C σ Normalized CG Fluctuation = (a) (b) Number of ITs 0 2 4 6 8 10 Cutof f Frequency fT (GHz) 300 350 400 450 g m T C g f π 2 = Number of ITs 0 2 4 6 8 10
Intrinsic Gate Delay
T ime τ (ps) 0.5 1.0 1.5 2.0 on dd GV I C / = τ (c) (d)
Fig. 6. (Color online) (a) The random ITs-fluctuated CG–VGcurves for the studied 16-nm-gate N-MOSFETs, where the nominal case is red and the fluctuated data are in gray. (b) The normalized CGfluctuation. (c) The cutoff frequency versus the number of random ITs. (d) The intrinsic gate delay versus the number of random ITs.
Y. Li and H.-W. Cheng Jpn. J. Appl. Phys. 51 (2012) 04DC08
effect, which was also observed for devices under influence of RDF.5) The normalized CG fluctuation versus VG, as
shown in Fig. 6(b), is normalized by the nominal CG. The
result implies the importance of random-ITs-position effect. Notably devices with high VG, the screening effect of the
inversion layer of the devices can not effectively screen the variation of potential, and thus, the normalized CG still
suffers from sizeable fluctuation which is different from RDF’s results.5) The results of gm and CG enables us to
estimate the cutoff frequency and intrinsic gate delay time of the studied 16-nm-gate N-MOSFETs, as shown in Figs. 6(c) and 6(d), respectively, where the insets give the definition of these quantities. The cutoff frequency is decreased and is increased as the number of ITs increases. With the decreasing gmand increasing CG, the cutoff frequency of the
device decreases with increasing ITs’ number. is increased as the dopant number increases due to the decreasing on-state current and increasing CG. Their fluctuation magnitude
is increased as the number of ITs increases. The random ITs’ effect not only causes fluctuations in Vth and ID but
also affects CG of the transistor. For the 16-nm-gate
P-MOSFETs, not shown here, we do perform similar simulations, in order to study the NM of the 16-nm-gate CMOS inverter circuit.
Figure 7(a) shows the transfer characteristic (plot of Vout Vin) of the random ITs-fluctuated 16-nm-gate CMOS
inverters. Two points on the voltage transfer curve determine the circuit’s NMs. The two points on the voltage transfer curve are defined as those values of Vin where the
incremental gain is unity; the slope is1 V/V. Figures 7(b) and 7(c) show the NMs for the logic ‘‘1’’ and ‘‘0’’,NMHand
NML, respectively, as a function of the ITs’ number. In
addition, even the cases with the same number of ITs, their NMs are still different due to ITs’ random position effect. The NML increases as the number of ITs increases because
of the increased Vthof the 16-nm-gate N-MOSFETs. For the
NMH, as numbers of ITs in the 16-nm-gate P-MOSFETs
increase, the increased Vth of the device may decrease the
VIH of the Vout Vincurve and, thus, increase theNMH. As
listed in Table II, both the fluctuations of NML (NML¼
20:3 mV) and NMH (NMH¼ 20:1 mV) are smaller than
the RDs-induced NML,RDs of 35 mV and NMH,RDs of
30 mV, respectively. RDs-induced NML and NMH
fluctua-tions are 42 and 33% larger than ITs-induced data. If we assume the random ITs and random dopants are independent and identically distributed (iid) random variables, statistical sums of variances of the random ITs and the random dopants calculated by using formulas ð2NML,ITsþ 2NML,RDsÞ1=2
and ð2NMH,ITsþ 2NMH,RDsÞ1=2 are 40.4 and 36.1 mV,
respectively. As summarized in Table II, the NML,RDs+ITs
and NMH,RDs+ITs resulting from the combined random ITs
and random dopants are 37.6 and 33.1 mV. Therefore, the iid assumption with respect to RDs and ITs may not always hold because it does not consider the interaction between ITF and RDF (the results according to iid assumption are 7.5 and 9.1% overestimation) which should be subject to further studies.
4. Conclusions
In this study, we have focused on electrical and transfer-characteristic fluctuations in 16-nm-gate TiN/HfO2 MOSFET devices and inverter circuit induced by random ITs at HfO2/Si interface. The preliminary findings of this study indicate the random ITs’ effect not only causes fluctuations in Vth and current but also affects the gate
capacitance of the transistor. In contrast to random-dopant fluctuation, the screening effect of inversion layer cannot effectively screen potential’s variation; thus, devices still have noticeable fluctuation of gate capacitance under high gate bias. The DIBL and the cutoff frequency decrease, and the intrinsic gate delay time increases as the number of ITs increases together with their increased fluctuation. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs’ fluctuations are also increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices. Random ITs near the source end result in significant locally enhanced spikes of surface potential which not only fluctuates Vth but also perturbs carrier’s
transport. Additionally, the interaction between RDs and ITs should be subject to further investigation for clearer understandings. Reduction of the fluctuation resulting from random ITs at HfO2/Si interface could be explored by reducing the entire density of random ITs; for example, if the entire IT’s density vary from 0:8 109 to 6
Vin (V) 0.0 0.2 0.4 0.6 0.8 VOUT (V) 0.0 0.2 0.4 0.6 0.8 Slope = -1 (a)
Number of ITs (N-MOSFET)
0 2 4 6 8 10 NM L = V IL (V) 0.15 0.20 0.25 0.30
Number of ITs (P-MOSFET)
NM H = V DD -V IH (V) 0.20 0.25 0.30 0.35 (b) (c) 0 2 4 6 8 10
Fig. 7. (Color online) (a) The random ITs-fluctuated voltage transfer curves (Vout Vin) of the 16-nm-gate CMOS inverter circuits. The parts of slope =1 indicate the low and high noise margins of the inverter. (b) and (c) show noise margins,NMLandNMH, as a function of the dopant number in the 16-nm-gate N- and P-MOSFETs.
Table II. Comparison of NMLand NMHinduced by the random ITs (in mV), the random dopants, and the combined random ITs and dopants for 16-nm CMOS inverter circuit. Statistical sums of variances of the random ITs and the random dopants are calculated by using formulasð2NML,ITsþ 2NM
L,RDsÞ1=2andð2NMH,ITsþ 2NMH,RDsÞ1=2, respectively, where we assume that the random ITs and random dopants are independent and identically distributed random variables.
NML NMH
Random ITs 20.3 20.1
Random dopants 35.0 30.0
Statistical sum 40.4 36.1
1010eV1cm2 at HfO2/Si interface of each 16-nm-gate
N-MOSFET device (a tenth of the original setting in this work), Vth will be reduced from 26.3 to 10.2 mV (about 61.2%
reduction). Notably, preliminary result of the interaction between random dopants and interface traps in 16-nm-gate HKMG MOSFET devices was reported in ref.37. We are currently calibrating fabricated and measured 16-nm HKMG CMOS samples.
Acknowledgments
This work was supported in part by National Science Council (NSC), Taiwan under contracts Nos. NSC-99-2221-E-009-175 and NSC-100-2221-E-009-018, and by the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan under a 2011–2012 grant.
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