應用於無線個人通訊低功率分時帶通和差調變類比數位換器

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(1)國立交通大學電機與控制工程研究所碩士論文應用於無線個人通訊低功率分時帶通和差調變類比數位換器. A Low Power Time Interleaved Band-pass Sigma Delta A/D Converter for Wireless Personal Communication. 研究生：陳育聖指導教授：指導教授：董蘭榮博士. 中華民國九十四年七月.

(2) 應用於無線個人通訊低功率分時帶通和差調變類比數位換器 A Low Power Time Interleaved Band-pass Sigma Delta A/D Converter for Wireless Personal Communication 研究生：陳育聖. Student：Yu Sheng Chen. 指導教授：董蘭榮. Advisor：Lan-Rong Dung. 國立交通大學電機與控制工程學系碩士論文 A Thesis Submitted to Department of Computer and Information Science College of Electrical Engineering and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master in Electrical and Control Engineering October 2005 Hsinchu, Taiwan, Republic of China. 中華民國九十四年七月 II.

(3) 應用於無線個人通訊低功率分時帶通和差調變類比數位換器. 學生：陳育聖. 指導教授：董蘭榮博士. 國立交通大學電機與控制工程研究所摘. 要. 帶通類比數位轉換器對電容的誤差以及高速度的處理上，面臨著對誤差極為靈敏，以及功率消耗極高的問題。因此我們採用了分時系統 (Time Interleaved System) 並且搭配上合成雜訊轉移函式 (NTF Synthesis) ，利用四個低通的三角積分 (ΔΣ) 類比數位轉換器合成一帶通類比數位轉換器。利用四個 ADC 的 channel 分時操作，每個一個 ADC 通道僅須操作在四分之一的帶通類比數位轉換器的工作頻率，如此一來除了可大幅降低 ADC 的功率消耗，延長電池的使用時間。此外，由於每一個 ADC channel 為一個 single loop low-pass sigma delta ADC，此架構之 ADC 對於電容的不匹配，及 OP DC gain 的要求較為寬鬆不靈敏，因此我們亦可在設計電路上得到附加的好處，以及避免掉非理想效應及製程飄移所帶來的問題，以達到所求之解析度。 III.

(4) A Low Power Time Interleaved Band-pass Sigma Delta A/D Converter for Wireless Personal Communication. Student：Yu Sheng Chen. Advisor：Dr. Lan-Rong Dung. Department of Electrical and Control Engineering National Chiao Tung University ABSTRACT The thesis proposes a low power four path time-interlaeved sigma-delta modulator with switched-opamp technique for personal wireless communication applications, such as the GSM system. In this thesis, we design a time interleaved bandpass sigma delta modulator by using four channels with lowpass sigma delta modulator, and implement by TSMC.18 μm 1P6M CMOS models. And, to avoid gain and offset mismatch produce by each channel, additional reference channel calibrated the errors by off-chip digital calibration technique described in section 3.3. We implement the bnadpass A/D converter by low power technique and we overcome the non-ideal effect by off-chip calibration.. IV.

(5) Table of Contents Chapter 1 Introduction ……………………………………………………………1 1.1 Motivation ………………………………………………………………1 1.2 Thesis Organization ………………………………………………………2 Chapter 2 Sigma Delta Modulator …………………………………………………3 2.1 The Basic Concept of Sigma Delta A/D Converter………………………3 2.1.1 Quantization Error ……………………………………………………3 2.1.2 Oversampling Technique………………………………………………6 2.1.3 Noise-Shaped Sigma-Delta Modulator……………………………9 2.2 The Lowpass Sigma Delta Modulator…………………………………12 2.2.1 First Order Lowpass Sigma Delta Modulator………………………12 2.2.2 Second Order Lowpass Sigma Delta Modulator……………………15 2.3 The Bandpass Sigma Delta Modulator …………………………………18 2.3.1 Transformation of the LP and BP Sigma Delta Modulator…………19 2.3.2 Second-Order Bandpass Sigma-Delta Modulator …………………21 2.3.3 Fourth-Order Bandpass Sigma-Delta Modulator …………………22 Chapter 3 Design of the Low-Power Bandpass Sigma-Delta Modulator ………25 3.1 Prototype of Switched-Capacitor Resonator………….…………………25 3.1.1 Resonator in Z-Domain………………………………………………25 3.1.2 Discrete-Time Resonator Topologies ..………………………27 3.1.3 The Design Challenge of Bandpass Sigma Delta Modulator..………29 3.2 Design A Time Interleaved Bandpass Sigma Delta ADC………………30 3.2.1 Time Interleaved System & Noise Transfer Function Synthesis……30 3.2.2 System level Design and Simulation of a Bandpass Modulator ….…32 3.3 Gain and Offset Calibration in Time Interleaved System………………36 3.3.1 The Gain and Offset Mismatch in Time Interleaved System………36 2.3.2 The Fully Digital Background Calibration….…………………37 Chapter 4 Implementation of Bandpass Sigma Delta Modulator ……………43 4.1 Block Diagram of Four Path Bandpass Modulator ….…………………43 4.1.1 Four Path Bandpass Modulator……………………………………43 4.1.2 Second Order Sigma Delta Modulator …....………………………44 4.2 Design and Simulation of Sub-Circuits…………………..………………46 4.2.1 Wide Swing Constant-Transconductance Bias Circuit…….……46 4.2.2 The Fully Differential Folded Cascode Operational Amplifier.. ….…48 4.2.3 Comparator…………………………………………………….……51 V.

(6) 4.2.4 Clock Generator…………………………………………….. ….…53 4.3 Implementation and Simulation Report………………….………………54 4.3.1 Layout Flooplan and Layout Consideration………………….………54 4.3.2 Simulation Result of the Four Path Bandpass Modulator..………57 Chapter 5 Conclusions ……………....…………………………………………59 Reference ……………………………………………………………………………60. List of Table Table 3.1 Simulation Result of Second Order Lowpass SDM…………….……… 34 Table 4.1 Transistors Size of the bias circuit……………......……………..…...…… 47 Table 4.2 Transistors Size of the Operational Amplifier ……………......………..… 49 Table 4.3 Performance summary of the Operational Amplifier………....….……… 51 Table 4.4 Transistor Size of the latch comparator ……..……………………...….… 53 Table 4.5 The Capacitor Array Name ………………......….……………………..… 55 Table 4.6 Summary of the Simulation………………………………......….……… 58 Table 5.1 Comparison with other works…………………….……………………… 59. List of Figures Figure 1.1 Block diagram of a time interleaved ADC ……….………………... 2 Figure 2.1 Quantizer and its linear model …………………………………….. 4 Figure 2.2 The probability density function for the quantization error …….……... 4 Figure 2.3 Oversampled A/D conversion with simple quantization and downsampling ……………………………………………7 Figure 2.4 (a) A simplified oversampled A/D conversion and (b) the magnitude frequency response of the low-pass filter………………………...………. ..7 Figure 2.5 Quantization noise power spectral density of Nyquist rate and oversampling rate ………………………………………...………... ..9 Figure 2.6 Block diagram of an oversampling Σ∆ A/D converter…...…………. 11 Figure 2.7 (a) a general Σ∆ modulator (b) linear model of the Σ∆ modulator…… 11 Figure 2.8 A first order oversampled Σ∆ modulator ………………...……….. 13 Figure 2.9 The power spectral density of a first order VI.

(7) oversampled Σ∆ modulator …………………………………… 15 Figure 2.10 A second order oversampled Σ∆ modulator ……...….……...…….. 15 Figure 2.11 The power spectral density of zero-, first-, second-order oversampled Σ∆ modulator …...……..………...………...…….. 16 Figure 2.12 The SNR v.s. OSR with different order sigma delta modulator …….….18 Figure 2.13 A Bandpass Sigma-Delta Modulator………………………...………. 19 Figure 2.14. (a) Lowpss Sigma Delta Modulator (b)Bandpass Sigma Delta Modulator………………………...………. 19. Figure 2.15 STF & NTF of The Bandpass Modulator at 3/4 Sampling Frequency. 20 Figure 2.16 NTF Poles and Zeros for Lowpass and Bandpass Modulator………….. 20 Figure 2.17 The Second Order Bandpass Sigma Delta Modulator ………………….21 Figure 2.18 NTF(Z) Frequency Response of 2nd Bandpass Modulator…...………. 22 Figure 2.19 The Fourth Order Bandpass Sigma Delta Modulator………...………. 23 Figure 2.20 NTF(Z) Frequency Response of 4th Bandpass Modulator…...………. 23 Figure 3.1 Forward Euler Resonator (FE)……………………………. ………....…. 27 Figure 3.2 Lossless Discrete Integrator (LDI)……………………………………….28 Figure 3.3 Double Delay Resonator (DD)…………………………………………... 28 Figure 3.4 Time Interleaved System ( N-Path Structure )……………………….. 30 Figure 3.5 Output Spectrum of the Four Path Modulator..……………………..…. 32 Figure 3.6 System Architecture of Matlab Simulation…………………...…………. 32 Figure 3.7 The Second Order Lowpass Sigma Delta Modulator………………..…. 33 Figure 3.8 The Power Spectrum Density of the Second Order Lowpass SDM…….. 34 Figure 3.9 The Four Path Bandpass Sigma Delta Modulator……...………....…….. 35 Figure 3.10 The Power Spectrum Density of the Four Path Bandpass SDM……… 35 Figure 3.11 The Top View of The Calibration Circuit ……………………….…….. 38 Figure 3.12 Blocks of The Calibration Circuit ……….……………..……….….….. 38 Figure 3.13 The state diagram of the FSM_T ……….…………..….…….………...39 VII.

(8) Figure 3.14 Clock Generator ..……….…………..….…….……………….….. 40 Figure 3.15 The state diagram of FSM_O………….…………..….…….………...41 Figure 3.16 The concept datapath diagram of OffGain…………..….…….………...42 Figure 3.17 The Final Output After Calibration……….…………..….……………...42 Figure 4.1 Clock Path of Four Path Bandpass Sigma Delta Modulator…….….….. 44 Figure 4.2 Fully Differential CMOS implementation of a 2nd SDM..……….….….. 45 Figure 4.3 Wide Swing Constant-Transconductance Bias Circuit.…………....….. 47 Figure 4.4 The fully Differential Folded Cascode Operational Amplifier…..…..... 49 Figure 4.5 Common-mode Feedback Circuit………………………..………..…..... 50 Figure 4.6 Simulation Gain and Frequency Response of the OPamp with 3pF load.. 51 Figure 4.7 The Latch Comparator Circuit…………………...………….……….. 52 Figure 4.8 Two Phase Non-overlap Clock Generator…..………..……….….….. 53 Figure 4.9 Tim waveforms of two phase non-overlap clocks ……..……….…...….. 54 Figure 4.10 The Layout Floorplan of the Four Path Bandpass Modulator _A……. 54 Figure 4.11 The Placement of The Capacitors…………..…………...……….. 56 Figure 4.12 The Layout Floorplan of the Four Path Bandpass Modulator _B..….. 56 Figure 4.13 The Layout of the Four Path Bandpass Sigma Delta Modulator.……. 57 Figure 4.14 TT Corner Power Spectral Density…………………………… …….... 58. VIII.

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