Abnormal threshold voltage shift under hot carrier stress in Ti1xNx/HfO2 p-channel
metal-oxide-semiconductor field-effect transistors
Jyun-Yu Tsai, Ting-Chang Chang, Wen-Hung Lo, Szu-Han Ho, Ching-En Chen, Hua-Mao Chen, Tseung-Yuen Tseng, Ya-Hsiang Tai, Osbert Cheng, and Cheng-Tung Huang
Citation: Journal of Applied Physics 114, 124505 (2013); doi: 10.1063/1.4822158 View online: http://dx.doi.org/10.1063/1.4822158
View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/114/12?ver=pdfcov Published by the AIP Publishing
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Abnormal threshold voltage shift under hot carrier stress in Ti
12xN
x/HfO
2p-channel metal-oxide-semiconductor field-effect transistors
Jyun-Yu Tsai,1Ting-Chang Chang,1,2,a)Wen-Hung Lo,1Szu-Han Ho,3Ching-En Chen,3 Hua-Mao Chen,4Tseung-Yuen Tseng,3Ya-Hsiang Tai,4Osbert Cheng,5
and Cheng-Tung Huang5
1
Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 2
Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan 3
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 4
Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan
5
Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan
(Received 29 July 2013; accepted 9 September 2013; published online 25 September 2013) This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1xNx p-channel metal
oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S.S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (Vd). However, our experimental data
indicate that S.S. has no evident change under CHCS, but threshold voltage (Vth) shifts positively.
This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such Vthdegradation is not observed in the saturation region during
stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different Vth behaviors in the linear and saturation regions.
Additionally, the influence of different nitrogen concentrations in HfO2/Ti1xNxp-MOSFETs on
CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-Nit
occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior.VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4822158]
Consumer electronic products, which are combined dis-play design,1,2 memory circuits,3–5 and IC circuits, have become considerably more popular in the last few years. To achieve high speed and light weight, the continuous scaling down of metal oxide semiconductor field electrical field tran-sistors (MOSFETs) is driving conventional SiO2-based
dielectric to be only a few atomic layers thick, leading to ex-cessive gate leakage current and reliability issues.6–8 To solve the leakage current problem, it is necessary to increase the physical thickness of the gate dielectric. One of the draw-backs of increasing the physical thickness, however, is that drive current will be decreased. Therefore, high-k material is highly recommended over a SiO2 gate insulator to reduce
both tunneling gate leakage and power consumption in CMOS circuits.9,10 Furthermore, the high-k/metal gate can be integrated with silicon on insulator techniques.11–13 Additionally, charge trapping in high-k gate stacks remains a key reliability issue, since it causes Vthshift and drive
cur-rent degradation14–17due to the filling of pre-existing traps in the high-k dielectric layer.18–20With the scaling down of MOSFETs, the issue of charge trapping effect is found to have great impact on channel hot carrier stress (CHCS)-induced device instability, since carriers tend to be injected into the high-k layer.21,22 However, these studies have mainly focused on characteristics of high-k/metal gate n-MOSFETs under CHCS. There are only a few studies on
p-MOSFETs even though p-MOSFETs are as important as n-MOSFETs in CMOS circuits. In this work, we therefore focus on the Vth shift characteristics during CHCS on
p-MOSFETs. It was found that the behavior of Vthshift is
to-ward the positive direction in the linear region, but does not change in the saturation region. Using capacitance-voltage (C-V) technique and observing the gate-induced drain leak-age (GIDL) current demonstrate that the charge trapping region under CHCS is mainly localized near the drain over-lap region, rather than throughout the overall high-k dielec-tric layer. In addition, we further investigated the impact of different Ti1xNx metal gate electrode compositions on
CHCS and found that the interface traps play an important role in Vth shift. A device with more interface traps has a
smaller Vthshift after CHCS.
HfO2/TiN p-MOSFETs with different concentrations of
Ti1xNxwere studied in this paper as an element of
high-performance 28 nm CMOS technology. These devices were fabricated using a conventional self-aligned transistor which progressed via the gate-first process. For gate-first process devices, high quality thermal oxides with thicknesses of 10 A˚ were grown on a (100) Si substrate as an interfacial ox-ide layer. After standard cleaning procedures, 30 A˚ of HfO2
film was sequentially deposited by atomic layer deposition. Next, 10 nm of TiN film was deposited by radio frequency physical vapor deposition, followed by poly-Si deposition as a low resistance gate electrode. The source/drain activation and poly-Si gate deposition were performed at 1025C. The channel and source/drain doping concentrations were about
a)Author to whom correspondence should be addressed. Electronic mail:
0021-8979/2013/114(12)/124505/5/$30.00 114, 124505-1 VC2013 AIP Publishing LLC JOURNAL OF APPLIED PHYSICS 114, 124505 (2013)
1 1018cm3and 1 1021cm3, respectively. In this study,
the dimensions of the selected devices were 1 and 10 lm in length with both 1lm in width. Identical devices with differ-ent concdiffer-entrations and thicknesses of Ti1xNx were also
investigated. These devices were subjected to the maximum substrate current Ib,max during CHCS conditions while at
-3.6 V/-4.5 V(L¼ 1/10 lm) drain voltages (Vd). The stress
was briefly interrupted to measure the drain current-gate voltage (Id-Vg) and substrate current-gate voltage (Ib-Vg)
transfer characteristics. All experimental curves were meas-ured using an Agilent B1500 semiconductor parameter ana-lyzer and a Cascade M150 probe station.
Figure 1shows the effects of CHCS on the characteris-tics of linear Id-Vg and corresponding Gm-Vg at
Vd¼ 100 mV for high-k/metal gate p-MOSFETs. The
stress condition Vg was selected at the maximum substrate
current Ib,max of CHCS conditions while Vd¼ 3.6 V.
Results show that there are degradations in the device during CHCS, which show a decrease in transconductance (Gm) and
positively shift in threshold voltage (Vth), drain current (Id),
however, seems to be invariant at Vg¼ 1.6 V.
Generally, according to the behavior of CHC effect on MOSFETs, there is a serious degradation at the drain side due to the creation of Nit, causing decrease in S.S, Id, and Gm
and increase in Vth.
However, a positive Vth shift (Vth became small) is
obtained under CHCS for high-k/metal gate p-MOSFETs. This suggests that the positive Vthshift results from electron
trapping in high-k layer during stress. When electron-hole pairs are produced by impact ionization, the stress voltage difference between gate and drain (Vgd) causes electron to
tend to inject into the gate side, as shown in the lower left inset of Fig. 1, resulting in the Vth shift. Further,
CHC-induced electrons flowing below the channel forms substrate current (Ib). The top right inset of Fig. 1 shows the Id-Vg
curve under semi-logarithmic scale before and after CHCS. It can be observed that the subthreshold swing (S.S.) was not affected, illustrating that Nit generation was insignificant.
Therefore, this result supports our assertion that the positive shift in Vth is indeed induced by electron-trapping in the
high-k layer located at the drain side rather than CHC-induced Nit.
In addition, it is likely that the injection carrier in the high-k dielectric is electrons. Fig. 2(a) shows the effect of CHCS on the GIDL characteristics by measurement of satu-ration Id-Vg and corresponding Ib-Vg from Vg¼ 0.5 V to
Vg¼ 1.6 V with Vd ¼ 2.4 V. The GIDL current decreases
with stress time, because the electrons trap in the high-k dielectric, which lead to a longer band-to-band tunneling path, in turn, reducing GIDL current, shown by the corre-sponding energy diagram in the inset of Fig. 2(a). Capacitance-voltage (C-V) measurement techniques indicate the location of electron trapping before and after CHCS. The gate-to-drain capacitance (Cgd) and gate-to-source
capaci-tance (Cgs) characteristics under initial and after CHCS are
measured and shown in Fig. 2(b)and its inset, respectively. Note that the Cgd-Vgcurve shifts in the positive direction
af-ter CHCS, but the Cgs-Vg curve has no significant change
before and after CHCS. This result supplies evidence that electron injection induced by CHCS is mainly trapped near the drain side of the high-k dielectric.
The correlation between the stress time and the Vthshift
is extracted from Id-Vgin linear and saturation region and is
shown in Fig.3(a). It can be seen that the Vthshifts in the
lin-ear region under CHCS, however, the Vth shift in the
FIG. 1. The characteristics of linear Id-Vg and corresponding Gm-Vg at
Vd¼ 100 mV for high-k/metal gate p-MOSFETs. The inset shows S.S. of
log Id-Vgcurve.
FIG. 2. (a) The saturation Id-Vgand corresponding Ib-Vgfrom OFF-state to
ON-state at Vd¼ 2.4 V. The inset shows the energy-band diagram cutting
from drain overlap region during CHCS. (b) Cgd-Vg and (inset) Cgs-Vg transfer characteristics under initial and after CHCS. Diagrams indicate their respective measurement methods.
saturation region is almost uninfluenced during stress. According to this, we suggest that the behavior can be attrib-uted to charge trapping-induced DIBL (drain-induced-bar-rier-lowering) effect. The electrons coming from impact ionization are trapped into the high-k layer at the drain side and result in DIBL behavior, lowering Vth. However, in the
saturation region, the source barrier height is dominated by higher Vd. According to the inset of Fig.2(b), Cgsshows no
significant change, illustrating no damage at the source, cor-responding to no Vthshift.
Furthermore, Figure3(b)shows a comparison of the Id
-Vg curves in the linear region after CHCS and saturation
region before CHCS. It can be seen that the influence of trap-ping does not extend to the source during saturation opera-tion. This is because saturation Vddepletes the trapping and
dominates channel potential.
To clearly illustrate that this phenomenon of electron trapping during CHCS being mainly trapped near the drain side, leading to the trapping-induced DIBL effect, channels of different lengths were examined. For the longer channel device, the stress condition was also selected at Ib,max. In
order to achieve the same amount of electrons, an Ibcurrent
of 10 lA, similar to the shorter channel device was selected, as shown in the inset of Fig.4. Based on the results in Fig.4, which shows a comparison of Vthas function of stress time
for short and longer channels, it can be seen that the Vthshift
for the long channel device has less degradation than the short one. This is because it is sufficiently long to endure the influence of drain voltage and trapping in the linear region, thereby suppressing the trapping-induced DIBL effect.
The impact of different composition Ti1xNx/HfO2
p-MOSFETs under CHCS was also investigated. Devices were fabricated with different metal gate stack concentrations: Ti1aNahas less nitrogen (N), while Ti1bNbhas more
nitro-gen (N). As has been previously shown, the nitronitro-gen of the metal gate can diffuse to the SiO2/Si interface during the
annealing process, causing additional defects.23 Therefore, the Ti1bNb device exhibits more interface states (pre-Nit)
by the charge pumping measurement,24 corresponding to more N, as shown in Figure 5(a). Figure 5(b) shows the charge trapping-induced Vth shift for Ti1xNx/HfO2
p-MOSFETs under CHCS. It can be observed that a smaller Vthshift under stress corresponds to a metal gate with higher
N concentration. This is due to channel mobility degradation from pre-Nit. The mobility degradation leads to a decrease in
impact ionization, causing fewer trapping carriers. Hence, fewer electron-hole pairs are generated, further reducing the probability of trapping behavior.
To further confirm that the pre-Nit results in this
phe-nomenon, a device with thinner high-k layer was utilized. Generally, N can diffuse to the SiO2/Si interface and easily
generate pre-Nit with a thinner high-k layer. Therefore, the
device with thinner HfO2should exhibit the least
degrada-tion due to more pre-Nit. Charge pumping current versus
gate voltage for Ti1bNb/HfO2p-MOSFETs with thinner and
thicker HfO2are shown in the inset of Figure6. Clearly, the
device with Ti1bNband thinner HfO2shows more
insignifi-cant Vthshift than that with thicker HfO2. The Vthshift for
the Ti1aNa/HfO2 device is also shown for comparison in
Fig. 6 to confirm that less charge trapping-induced DIBL behavior is due to more pre-Nit, reducing Vthshift.
This paper investigates the effect of channel hot carrier stress on Ti1xNx/HfO2p-MOSFETs. The positive Vthshift
can be observed in the linear region but no shift in the
FIG. 3. (a) The degradation of DVthversus stress time in linear and
satura-tion regions during CHCS. The inset shows the energy-band diagram to illustrate charge trapping-induced-DIBL effect. (b) The characteristics of Id
-Vg curves in saturation before CHCS and linear region after CHCS. The
inset shows the energy-band diagram in linear and saturation regions at ini-tial and after CHCS.
FIG. 4. The degradation of DVthversus stress time for L¼ 1 and 10 lm. The
saturation region under CHCS is due to trapping-induced DIBL effect. Electron trapping during CHCS being mainly trapped near the drain side, leading to the trapping-induced DIBL effect was also confirmed, which has been verified by modifying channel length. Investigation of charge trapping-induced DIBL behavior under CHCS for different metal gate
stack compositions showed that pre-Nit dominates the
amount of trapping carrier, since decreasing mobility reduces the impact ionization.
Part of this work was performed at United Microelectronics Corporation. The work was supported by the National Science Council under Contract No. NSC-102-2120-M-110-001.
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