Jung-Sheng Chen, Student Member, IEEE, and Ming-Dou Ker, Senior Member, IEEE
Abstract—A new proposed gate-bias voltage-generating
tech-nique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensa-tion has been successfully verified in an 8- m LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.
Index Terms—Analog circuit, biasing circuit,
low-tempera-ture polycrystalline silicon (LTPS), thin-film transistor (TFT), threshold-voltage compensation, threshold-voltage variation.
I. INTRODUCTION
L
OW-TEMPERATURE polycrystalline silicon (LTPS) thin-film transistors (TFTs) have attracted a great deal of attention in the applications with the integrated on-panel periph-eral circuits for active-matrix liquid crystal display (AMLCD) and active-matrix light-emitting diodes (AMOLEDs) [1]–[3]. Recently, LTPS AMLCDs integrated with driving and con-trol circuits on glass substrate have been realized in some portable systems, such as mobile phones, digital cameras, and notebooks. In the near future, the AMLCD fabricated in the LTPS process is promising toward system-on-panel (SoP) or system-on-glass (SoG) applications, especially for achieving a compact, low-cost, and low-power display system [4].The LCD data driver contains shifter registers, level shifters, digital-to-analog converters (DACs), and output buffers. The bi-asing circuit is a critical circuit block for analog circuits on the LCD panel to achieve low power consumption, high speed, and high resolution. However, the poly-Si TFT device suffers from significant variation in its threshold voltage, owing to the nature of crystal growth in the LTPS process. The threshold-voltage variation across a 2.7-in panel was about 300 mV [5]. The vari-ation could even be as large as 1 V in some high-performance TFT devices across a large substrate area [6]. The threshold-Manuscript received November 29, 2006; revised February 14, 2007. This work was supported in part by the Chunghwa Picture Tubes (CPT), Ltd., Taiwan, R.O.C., and in part by the Ministry of Economic Affair, Tech-nology Development Program for Academia, Taiwan, R.O.C., under Contract 95-EC-17-A-07-S1-046.
The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: jschen@ieee.org; mdker@ieee.org).
Digital Object Identifier 10.1109/JDT.2007.900916
voltage variations of TFT devices will cause large mismatches on the biasing voltages and currents in analog circuits to re-sult in nonuniformity of performances among analog circuits over the whole panel. The design with threshold-voltage com-pensation for analog circuits on glass substrate is a very impor-tant challenge for SoP applications. The design technique with switches and capacitors under multiphase clock operation were usually used to compensate for the threshold-voltage variation among TFT devices in LTPS AMLCDs [7]–[9]. Some design techniques with switch and capacitor under multiphase clock operation were used to reduce the offset voltage of the analog buffer in the LTPS process [7]. In LTPS technology, the on-panel output buffers with a pair of n-type and p-type TFT devices im-mune to the mismatch of threshold voltage were also reported [8], [9]. The mismatch of threshold voltage can be compensated by a holding capacitor or the mathematical product of voltage gain. Besides, the threshold-voltage-shift compensation tech-nique was used to compensate for the threshold-voltage vari-ation for differential amplifiers in analog circuits [10]. How-ever, those techniques [7]–[10] only emphasize the impact of threshold-voltage variation on the offset voltage of the analog buffers on glass substrate. The biasing circuit with threshold-voltage compensation for analog circuits in the LTPS process is not yet reported in the literature.
In this paper, a method to reduce the influence of threshold-voltage variation on the gate-bias threshold-voltage-generating circuit for analog circuits on glass substrate is proposed. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed biasing tech-nique with threshold-voltage compensation enables the analog circuits to be integrated and implemented in the LTPS process for an AMLCD panel.
II. IMPACT OF THRESHOLD-VOLTAGE VARIATION ONTFT I–V CHARACTERISTICS
In general, the TFT devices on glass substrate are usually de-signed in the saturation region for analog circuit applications. The small-signal gain and frequency response of analog circuits in the LTPS process are determined by transconductance and output resistance of TFT devices. The small-signal pa-rameters of transconductance and output resistance in TFT devices can be expressed, respectively, as
(1) (2) 1551-319X/$25.00 © 2007 IEEE
Fig. 1. Simulated waveforms of n-TFT drain currentI with 50% threshold-voltage variation of Gaussian distribution under different gate threshold-voltagesV in an 8-m LTPS process.
where is the mobility of carrier, denotes the effective channel length, is the effective channel width, is the gate oxide capacitance per unit area, is the threshold voltage of the TFT device, is the gate-to-source voltage of the TFT device, is the Early voltage, and is the drain current of the TFT device. Comparing (1) and (2), the drain current is the major factor for analog circuits in the LTPS process. Therefore, the performances of analog circuits in the LTPS process are dominated by the drain current of the TFT device. The drain current of the TFT device operated in the saturation region can be expressed as
(3) The channel-length modulation of the TFT device is not in-cluded in (3). The threshold voltage of the TFT device is an important parameter in (3), so the threshold-voltage variation among TFT devices will cause the variation on drain currents of TFT devices to degrade the circuit performances in analog cir-cuits on glass substrate. How to design a stable biasing circuit with threshold-voltage compensation to reduce nonuniformity of performances in analog circuits over the whole panel in the LTPS process is an important design challenge.
The HSPICE with Monte Carlo analysis can be used to sim-ulate and analyze the impact of threshold-voltage variation on drain current of the TFT device. The threshold-voltage varia-tion of the TFT device on glass substrate can be modeled by Gaussian distribution. The simulated waveforms of n-TFT drain current with 50% threshold-voltage variation of Gaussian distribution under different gate voltages in an 8- m LTPS process is shown in Fig. 1. The dimension of n-TFT device is m m. The gate voltage is biased from 1.3 to 4.3 V. In order to confirm that the n-TFT device is operated in the sat-uration region, the drain voltage of the n-TFT device is also biased from 1.3 to 4.3 V to keep the gate-to-drain voltage of 0 V. The simulated result shows that the n-TFT device with 50% threshold-voltage variation of Gaussian distribution causes the drain current with a variation as large as 22 A in the LTPS
currents in analog circuits to further result in nonuniformity of performances in analog circuits over the whole panel. For the SoP applications, reducing the impact of threshold-voltage vari-ation on performance among analog circuits in the LTPS process is a very important design challenge.
III. NEWPROPOSEDGATE-BIASVOLTAGE-GENERATING TECHNIQUEWITHTHRESHOLD-VOLTAGECOMPENSATION
A. Design Concept
The new proposed gate bias voltage generating technique with threshold-voltage compensation is illustrated in Fig. 2. The biasing current is a small current used to bias the
device operated in weak inversion region. When the device is operated in the weak inversion region, the gate control voltage can be written as
(4) where is the threshold voltage of device, and
is the applied biasing voltage. The drain current of device can be expressed as
(5) where is the threshold voltage of device. The and devices are drawn with the same device dimension. The threshold-voltage difference between and devices can be reduced as small as possible by symmetrical and com-pact layout in an adjacent location. Therefore, (5) can be further rewritten as
(6) The drain current of device can become inde-pendent of the threshold voltage and dominated by the voltage. The new proposed gate-bias voltage-generating tech-nique with threshold-voltage compensation does not need any extra clock signal and capacitor to reduce the impact of
Fig. 3. Complete circuit of the proposed gate-bias voltage-generating circuit with threshold-voltage compensation for analog circuits in LTPS technology.
threshold-voltage variation on the biasing circuit for analog circuits in LTPS processes.
B. Circuit Implementation
The complete circuit of the proposed gate-bias voltage-gen-erating technique with threshold-voltage compensation for analog circuit applications in LTPS technology is shown in Fig. 3. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation is formed with , ,
, , , and devices. The , , , and
devices form the current mirror. In order to reduce the power consumption and chip area of the new proposed gate-bias voltage-generating circuit, the and devices are used to realize the referenced current source. The and devices are operated in the saturation region to generate a biasing current through the current mirror of , , , and devices to bias device operated in the weak inversion region. The voltage can be expressed as
(7)
(8)
where is the voltage at the source node of device in pro-posed gate-bias generating circuit. The biasing current and can be written, respectively, as
(9) (10) where the is the dimension ratio of and in the current mirror. The factor is especially designed much larger than one to reduce the impact of biasing current variation
Fig. 4. Simulated gate control voltageV of the proposed gate-bias voltage-generating circuit with threshold-voltage compensation under different biasing voltagesV .
Fig. 5. Simulated gate control current V of the proposed gate-bias voltage-generating circuit with threshold-voltage compensation under the different biasing voltagesV with the 50% threshold voltage variation (Gaussian distribution) on n-TFT and p-TFT devices.
on gate control voltage of the new proposed gate-bias voltage-generating circuit.
The simulated gate control voltage of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages is shown in Fig. 4. The typical threshold voltage of an n-TFT device in an 8- m LTPS process is approximately 1.3 V. The voltage is biased from 0 to 3 V. The gate control voltage
is changed from 1.3 to 4.3 V. The gate control voltage of the new proposed gate-bias voltage-generating cir-cuit with threshold-voltage compensation is approximately . The HSPICE with Monte Carlo Analysis is used to verify the function of the new proposed gate-bias voltage-generating circuit with threshold-voltage compensation in LTPS technology. The simulated gate control current of the new proposed gate-bias voltage-generating circuit with threshold-voltage compensation under the different biasing voltages with the 50% threshold voltage variation (Gaussian distribution) of n-TFT and p-TFT devices is shown in Fig. 5. The variation on gate control voltage , which can be used to compensate the threshold-voltage variation of TFT
Fig. 6. Simulated drain currentI of the proposed gate-bias voltage-gen-erating circuit with threshold-voltage compensation under different biasing volt-agesV with the 50% threshold voltage variation (Gaussian distribution) of n-TFT and p-TFT devices.
device in the LTPS process, is 0.675 V. The simulated drain cur-rent of the new proposed gate-bias voltage-generating circuit with threshold-voltage compensation under different biasing voltages with the 50% threshold-voltage vari-ation (Gaussian distribution) of n-TFT and p-TFT devices is shown in Fig. 6. The device dimension of device is m m. The gate-to-drain voltage of device is set to zero voltage to be operated in the saturation region. The simulated results show that the 50% threshold-voltage variation with Gaussian distribution of n-TFT and p-TFT devices causes only a variation of 3.84 A on the drain current in the new proposed gate-bias voltage-generating circuit with threshold-voltage compensation. Comparing the simulated results of Figs. 1 and 6, the new proposed gate-bias generating circuit with threshold-voltage compensation can effectively reduce the impact of threshold-voltage variation on the biasing circuit in the LTPS process.
IV. EXPERIMENTALRESULTS
The new proposed gate-bias generating circuit with threshold-voltage compensation has been fabricated in an 8- m LTPS technology. Fig. 7 shows the chip photograph of the new proposed gate-bias generating technique with threshold-voltage compensation. The test chip size of the new proposed gate-bias generating circuit with threshold-voltage compensation circuit is 517 389 m in 8- m LTPS technology. The averaged power consumption of the proposed gate-bias generating circuit with threshold-voltage compensation is only 47 W under the supply voltage of 10 V. In this study, the definitions of mean value and variation (%) of currents in these measured results are adopted as
(11) (12) where , , , and are drain currents of sample1, sample2, sample3, and sample4 of four LPTS n-TFT devices
threshold-voltage compensation fabricated in an 8-m LTPS process.
Fig. 8. Measured dependence of variation (%) on the gate voltageV among four LTPS n-TFT devices in different panel locations.
in different panel locations, respectively, and the # is a sample number from 1 to 4. The power supply voltage is set to 10 V. Fig. 8 shows the measured dependence of variation (%) on the gate voltage under four LTPS n-TFT devices in dif-ferent panel locations. The device dimensions of four n-TFT de-vices are kept at m m in an 8- m LTPS process. The gate voltages of these samples are biased from 1.3 to 4.3 V. The gate-to-drain voltage of the n-TFT device is set to 0 V to keep the n-TFT device operating in the saturation region. Because the gate-control voltage of the new proposed gate-bias gener-ating circuit is , the gate voltage from 1.3 to 4.3 V is normalized from 0 to 3 V. The variation (%) among four LPTS n-TFT devices in different panel locations is decreased from 195% to 30%, when the gate voltage is increased from 0 to 3 V. The measured results have confirmed that the variation (%) of four LPTS n-TFT devices in different panel locations under low gate voltage is large, but that under high gate voltage is low.
The measured dependence of variation (%) on the biasing voltage among four LTPS test circuits of the new pro-posed gate-bias generating circuit with threshold-voltage com-pensation in different panel locations is shown in Fig. 9. The variation (%) among four LPTS test circuits in different panel locations is decreased from 73% to 5%, when the gate voltage is increased from 0 to 3 V. Comparing the measured results between Figs. 8 and 9, the new proposed gate-bias generating
Fig. 9. Measured dependence of variation (%) on the biasing voltageV among four LTPS test circuits of the new proposed gate-bias generating tech-nique with threshold-voltage compensation in different panel locations.
technique with threshold-voltage compensation can effectively reduce the impact of threshold-voltage variation on the biasing current or biasing voltage for analog circuits in SoP or SoG applications.
V. DISCUSSION
When the referenced current source is realized with an ideal referenced current source, the simulated results show that variation of is only 0.27 A under 50% threshold-voltage variation (Gaussian distribution) of n-TFT and p-TFT devices. In order to achieve the low power con-sumption and small chip area, the referenced current source in the proposed gate-bias voltage-generating circuit with threshold-voltage compensation is realized by and devices. Because the voltage is dependent on threshold voltages of n-TFT and p-TFT devices, the threshold-voltage variation will cause some variations on the voltage and biasing current ( and ) to degrade the perfor-mances of the proposed gate-bias voltage-generating circuit with threshold-voltage compensation. The variation of is finally increased from 0.27 to 3.84 A under 50% threshold voltage variation (Gaussian distribution) of n-TFT and p-TFT devices. In order to reduce the impact of referenced current variation on circuit performance, the and refer-enced current source can be further replaced by the modified n-TFT threshold-voltage referenced current source [11]. The complete circuit of the proposed gate-bias voltage-generating circuit with n-TFT threshold-voltage referenced current source for analog circuit applications in LTPS technology is shown in Fig. 10. When the referenced current source is realized with modified n-TFT threshold-voltage referenced current source, the simulated results show that the variation of is only 0.36 A under 50% threshold-voltage variation (Gaussian distribution) of n-TFT and p-TFT devices, as shown in Fig. 11. Because the threshold voltages of n-TFT devices have the same variation trend in the local panel location, the biasing current with modified n-TFT threshold-voltage referenced current source can further reduce the variation on performance of the proposed circuit.
Fig. 10. Complete circuit of the proposed gate-bias voltage-generating circuit with modified n-TFT threshold-voltage referenced current source for analog cir-cuits in LTPS technology.
Fig. 11. Simulated drain currentI of the proposed gate-bias voltage-gen-erating circuit with modified n-TFT threshold-voltage referenced current source under different biasing voltagesV with the 50% threshold voltage variation (Gaussian distribution) of n-TFT and p-TFT devices.
VI. CONCLUSION
A new gate-bias generating technique with threshold-voltage compensation has been presented to reduce the impact of threshold-voltage variation on analog circuit performance in LTPS technology. The new proposed gate-bias generating cir-cuit with threshold-voltage compensation has been successfully verified in an 8- m LTPS process. The measured results have confirmed that the impact of threshold-voltage variation on drain current of the n-TFT device can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias generating technique with threshold-voltage compensation can be applied to realize analog circuits in the LTPS process for SoP or SoG applications.
REFERENCES
[1] H. G. Yang, S. Fluxman, C. Reita, and P. Migliorato, “Design, measure-ment and analysis of CMOS polysilicon TFT operational amplifiers,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 727–732, Jun. 1994. [2] T. Matsuo and T. Muramatsu, “CG silicon technology and development
of system on panel,” in SID Tech. Dig., 2004, pp. 856–859.
[3] Y. Matsueda, R. Kakkad, Y. S. Park, H. H. Yoon, W. P. Lee, J. B. Koo, and H. K. Chung, “2.5-in. AMOLED with integrated 6-bit gamma com-pensated digital data driver,” in SID Tech. Dig., 2004, pp. 1116–1119.
mismatch compensated analogue buffer for driver-integrated poly-Si TFT LCDs,” Electron. Lett., vol. 41, no. 2, pp. 65–66, Jan. 2005. [10] P. Madeira and R. Hornsey, “Analog circuit design using amorphous
silicon thin film transistors,” in Proc. IEEE Canad. Conf. Elect. Comput. Eng., 1997, pp. 633–636.
[11] P. R. Gray, P. J. Hurst, S. H. Lewis, and P. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2001, pp. 307–313.
Jung-Sheng Chen (S’03) received the B.S.
de-gree in electronics engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C., in 2000, and the M.S. degree in engineering and system science from National Tsing-Hua University, Hsinchu, Taiwan, R.O.C., in 2002. He is currently working toward the Ph.D. degree in electrical engineering at National Chiao-Tung University, Hsinchu.
His current research interests include analog circuit design, mixed-signal circuit design, and circuit reliability.
and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in TFT LCD display. He has been invited to teach or to consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the Sci-ence-Based Industrial Park, Hsinchu, Taiwan, R.O.C., Silicon Valley, San Jose, CA, Singapore, Malaysia, and mainland China.
Dr. Ker has served as member of the Technical Program Committee and Ses-sion Chair of numerous international conferences. He was selected as the Dis-tinguished Lecturer of the IEEE Circuits and Systems Society for 2006–2007. He has also served as an Associate Editor of the IEEE TRANSACTIONS ONVERY
LARGESCALEINTEGRATION(VLSI) SYSTEMS. He was elected as the President of Taiwan ESD Association in 2001. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by the Junior Chamber International (JCI). In 2005, one of his patents on ESD protection design has been awarded with the National Invention Award in Taiwan.
