Current-Mode Synthetic Control Technique for
High-Efficiency DC–DC Boost Converters
Over a Wide Load Range
Yi-Ping Su, Yean-Kuo Luo, Yi-Chun Chen, and Ke-Horng Chen, Senior Member, IEEE
Abstract— This paper proposes a current-mode synthetic
con-trol (CSC) technique for the design of boost converters to over-come the difficulty in designing a current-ripple hysteresis boost converter and to maintain high conversion efficiency over a wide load range. The CSC technique has a high accuracy because of the additional voltage path through the error amplifier. A smooth load transient response is maintained when the operation transits from continuous conduction mode with a nearly constant switch-ing frequency to discontinuous conduction mode with a load-dependent switching frequency. Generally, ripple performance, light-load efficiency, and switching frequency are traded off in the design of hysteresis control regulator. In this paper, a balance among the load-dependent switching frequencies at light loads results in high power conversion efficiency compared with conventional pulsewidth modulation converter and attains compact ripple performance. The experimental results show that the output voltage ripple can be kept < 50 mV over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA when the switching frequency is decreased from 5 to 2 MHz.
Index Terms— Boost converter, current-mode synthetic control
(CSC), hysteresis control regulator.
I. INTRODUCTION
P
ORTABLE electronics products, such as cellular phones, laptops, and diverse multimedia equipment, use battery as the main power source. To extend the battery life, portable devices stay in sleep mode with a very low static current but require a fast wakeup response to reach the normal mode, which consumes much higher operating current. Therefore, suitable converters used in portable devices require fast tran-sient response from the standby to normal mode [1]–[5]. Furthermore, high efficiency must be guaranteed over a wide load range [6]. Basically, hysteresis control, either in current-or voltage-ripple control mode, can address fast transient requirement [7]–[9]. In addition, hysteresis control is self-stabilized if the equivalent series resistance (ESR) of the output capacitor is large enough.Basically, the voltage-ripple hysteresis mode modulator must regulate the output voltage within the voltage hysteresis Manuscript received March 21, 2013; revised June 25, 2013; accepted July 25, 2013. Date of publication August 23, 2013; date of current version July 22, 2014.
The authors are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: susu.supy@ gmail.com; q1892111@nckualumni.org.tw; m432567.ece97g@nctu.edu.tw; khchen@cn.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2013.2277491
Fig. 1. Examples of current-ripple hysteresis control in (a) buck and (b) boost converter.
window [9]–[11]. Its transient response is fast due to the fast operation of the comparator, but it is difficult to interleave (multiphase) due to complexity in derivation of the clock signal [11]–[16]. Another disadvantage is that the output ripple must be large enough to increase noise margin [8], [9], [11]; hence, a larger ESR value is necessary. In other words, interference immunity must be enhanced by a large ESR, but it suffers from large transient voltage variation. Selection of the output capacitor is limited with large ESR.
On the other hand, the current-ripple hysteresis mode mod-ulator requires a current sensing circuit to obtain current information [17]–[20]. Fig. 1(a) shows an example of a current-ripple hysteresis buck converter. Inductor current, iL, is regulated within the hysteresis window. Large ESR value is not necessary. It is, however, hard to determine the switching clock because of ground bounce and switching noise at the intersection region. In other words, the low noise immunity seriously affects the regulation performance. In addition, the advantage of current-ripple hysteresis control is not suitable for a boost converter because it is difficult to determine the off-and on-time even if the switching noise is ignored [17]–[19]. The reason is that a conventional current sensor, which uses a scaled sensing MOSFET, senses inductor current only when the low-side power switch turns on. Thus, it cannot provide a full-range sensing mechanism, as shown in Fig. 1(b). Even if the current sensing can be obtained by a sensing resistor in series with the inductor, conversion efficiency will be greatly deteriorated because of large conduction loss.
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Fig. 2. (a) Synthetic current-ripple regulator. (b) Inductor current is emulated by the synthetic ripple which is a much cleaner signal.
To improve noise immunity and conquer the difficulty of realizing current-ripple control in boost converter, the synthetic-ripple modulator, which is shown in Fig. 2(a), is proposed to obtain an almost noise-free synthetic current ripple by integration [21], [22]. The synthetic-ripple capacitor
Cr adopted in synthetic ripple generator is used to filter out the noise, as shown in Fig. 2(a). The waveform of synthetic current-ripple signal, Vs, is shown in Fig. 2(b). In addition, the introduction of the error amplifier can enhance regulation accuracy. The system, however, contains two poles, thus requiring a complex compensation network, such as the proportional–integral–differential (PID) compensator.
With the disadvantages in prior arts, the ripple-controlled technique should have the following advantages: the switch-ing frequency should be nearly constant under steady-state condition and can be easily obtained for multiphase opera-tion. In addition, the switching frequency can be extended to further reduce the switching power loss at light loads during standby operation. The accuracy of the load regulation has to be improved. In addition, dependence on large ESR, which improves noise immunity, should be minimized, thereby reducing transient voltage variation and output ripple.
This paper introduces a current-mode synthetic control (CSC) technique to include the dc inductor current information for simplifying compensation network. Because the noise immunity is improved by the CSC technique, the output ripple can be kept smaller than those in the prior arts with a small ESR value. Because a nearly constant switching frequency in steady state is maintained, the capability of the multiphase architecture is easily achieved. Furthermore, optimum and smooth transition between pulsewidth modulation (PWM) and pulse frequency modulation (PFM) modes is realized. That is, the switching period with CSC technique is extended to reduce the switching power loss and prolong the battery life of the portable devices during standby mode. The proposed CSC technique is introduced in Section II. The system stability analysis is described in Section III, showing the simplified compensation network. Circuit implementation is described in
Fig. 3. Architecture of the proposed CSC circuit.
Section IV. The experimental results are shown in Section V. Finally, a conclusion is summarized in Section VI.
II. CSC TECHNIQUE
The proposed CSC technique is shown in Fig. 3. Because the dc inductor current information is introduced, the com-pensation network is simplified from PID to PI compensator, which contains a resistor, RZ, and a capacitor, CCOMP. The inductor current is sensed by the current sensing circuit, Ri, to generate current sense signal, Vsense, which contains dc inductor value and current ripple. The ripple of Vsensecan be limited in the hysteresis window, VW, equivalently. The error amplifier is adopted for load regulation improvement. Because the noise immunity is improved by the CSC technique, the output ripple can be kept smaller than those of the prior arts with small ESR value. In addition, the CSC technique contains a synthetic clock generator (SCG), which generate system clock, Vclk, providing the nearly constant switching frequency during continuous conduction mode (CCM) operation and variable switching frequency during discontinuous conduction mode (DCM) operation for high efficiency. The zero-current detector (ZCD) is activated in the DCM operation.
A. Detail Operation of CSC
The current-mode hysteresis window is composed of the upper and the lower bound voltage, VH and VL, respectively. The hysteresis window of the proposed synthetic current-mode control is designed as the VW, which is a constant value. The relationship between VH and VL can be shown in (1)
VH = VL+ VW where
VL = Vcomp. (1)
Because worse load regulation performance in conventional current-mode hysteresis control comes from the lack of voltage regulation loop, VL is equal to Vcompwhich is the output of the error amplifier in CSC control. That is, the proper definition of
VL = Vcomp improves load regulation. During the increasing inductor current subinterval, the duty cycle is determined adequately by comparing the current sense signal, Vsense, and
Vcomp, as shown in Fig. 4(a). During the decreasing inductor current subinterval, SCG circuit emulates and follows the
Fig. 4. CSC technique forces the system to operate in (a) CCM operation at heavy loads and (b) DCM operation at light loads for power saving. (c) Smooth transition between CCM and DCM operations.
decreasing inductor current to generate the synthetic current ripple, Vramp, with the slope which is proportional to m2 by using the difference between Vin and Vout. To determine the switching frequency of CSC in CCM operation, Vramp is limited in the hysteresis window, VW. The switching frequency is expressed as (2) fs(CCM) = km2 VW where m2 = (Vout− Vin) L ∝ (Vout−Vin) (2)
where Vinis the input voltage, Vout is the output voltage, L is the inductor value, m2 is the slope of decreasing inductor current, and k is the proportionality constant. It can be
Fig. 5. CSC technique can (a) reduce the switching power loss and thus (b) improve the power conversion efficiency.
observed that switching frequency in CCM operation is nearly constant with a fixed hysteresis window and input and output conditions.
By the SCG circuit, the synthetic clock signal, Vclk, which shows the beginning of each switching period, maintains nearly constant switching frequency and output voltage ripple in CCM. To ensure the accuracy of switching frequency,
Vclk should be a small pulse to reset Vramp to its initial state VH. A large Vclk width causes a frequency deviation because of the offset between Vramp and Vsense.
B. Modulation Method in Different Load Conditions
At heavy loads, the system is in CCM operation. The sys-tem switching frequency depends on hysteresis window VW. Fig. 4(a) shows that the switching frequency is nearly constant during CCM operation to ensure high driving capability and constant frequency operation. Accuracy is guaranteed com-pared with the prior arts.
On the other hand, the system is in DCM operation at light loads. In contrast to the PWM control, the switching period is extended to reduce switching power loss in DCM operation. Fig. 4(b) shows that during the DCM operation, the synthetic current-mode waveform is kept constant once the inductor current becomes zero, as detected by the ZCD. In other words, the off-time is extended if the signal ZC is equal to one when ZCD detects zero inductor current. The output load is simply supplied by the output capacitor, Cout, because both M1 and
M2 in Fig. 3 are switched off. The decreasing output voltage gradually causes the increasing in Vcomp to be higher than the Vramp, again. Therefore, the switching frequency during the DCM operation is reduced to further minimize switching power loss and increase the conversion efficiency at light loads, as shown in Fig. 5(a) and (b), respectively. The switching
frequency dependent on load current makes the switching power loss proportional to the switching frequency.
At very light loads, the on-time of M1 is further reduced to decrease the average inductor current. Therefore, the zero-current period increases significantly and occupies most of the switching periods. The slope of increasing in Vcomp can be derived in (3) mEA= d Vcomp dt ≈ gm(EA) CCOMP Iload Cout 1 fs(DCM). (3) In DCM operation, the switching frequency is determined by the hysteresis window, VW. Thus, the value of mEA can decide the switching frequency, as shown in (4)
fs(DCM)≥ mEA VW = Iloadgm(EA) VWCoutCCOMP (4) where gm(EA) is the transconductance of the error amplifier,
CCOMP is the compensation capacitor in Fig. 3, Iload is the loading current, Cout is the output capacitor, and VW is the hysteresis window. As shown in (4), the switching frequency decreases with the reduction of load current.
C. Smooth Transition Between CCM and DCM
In current-mode PWM control, the system enters into DCM operation with a constant switching frequency at light loads [23]. To obtain high efficiency, PFM can be included in the conventional current-mode control. Unfortunately, the transition between PWM and PFM will induce a large transient voltage variation [8], [24], [25]. In addition, optimum and smooth transition between PWM and PFM is hard to attain because of variations of loading or input/output condition. In contrast, the CSC technique can smoothly decrease the load-dependent switching frequency at light loads and achieve optimal mode transition.
Fig. 4(c) shows that the CSC technique can smoothly transit from DCM to CCM when the load current changes from light to heavy. As load current increase at point A, the lack of energy at Vout causes Vcomp to increase, thereby raising the hysteresis window. The increase in Vcomp results in the decrease in zero inductor current periods and forces the operation mode entering into the CCM at point A. The advance of Vclk pulse at point B increases the switching frequency from fs to fs. On the contrary, the mode transition from CCM to DCM can be achieved spontaneously. Therefore, a smooth transition between DCM to CCM ensures smaller output ripples comparing with the prior arts with PWM/PFM hybrid mode control.
D. Compact Design Between Output Ripple and Switching Frequency
The voltage ripple can be reduced with higher switching frequency. Thus, a converter with low frequency suffers from worse ripple performance and larger output voltage drop. In addition, an annoying sound is produced when switching frequency is near or below the audio frequency. Therefore, the modified DCM operation is shown in Fig. 6. After a zero current is detected by ZCD, Vramp slowly ramps down with
Fig. 6. Modified DCM operation in CSC technique, which introduces the small auxiliary slope maafter the zero current is detected.
the small auxiliary slope kma rather than keeping constant in Fig. 4(b) to prevent the converter operating at a very low switching frequency. At very light-load condition, the switching frequency can be derived by modifying (4) and expressed in (5) fs(DCM,aux)≥ kma 2VW + kma 2VW 2 + Iloadgm(EA) VWCoutCCOMP (5) where gm(EA) is the transconductance of the error amplifier,
CCOMP is the compensation capacitor in Fig. 3, Iload is the loading current, Cout is the output capacitor, VW is the hysteresis window, and kma is the small auxiliary discharge slope. As shown in (5), the auxiliary slope helps to suppress the reduction of switching frequency effectively. Furthermore, even if the load current is equal to zero, the switching frequency is able to be kept beyond audio frequency band (20 Hz–2 kHz). As shown in (6), the minimum switching frequency can be properly designed considering the maximum allowable output ripple,VOUT
fs(DCM,aux)I
load=0=
kma
VW > 20 kHz > f
s(DCM). (6)
III. CIRCUITIMPLEMENTATION
A. Synthetic Clock Generator
As shown in Fig. 7(a), the SCG circuit, which ensures nearly constant switching frequency in CCM operation, includes two parts—high linearity in–out subtractor in Fig. 7(b) and hys-teresis clock generator in Fig. 7(c). To emulate the decreasing inductor current, discharging current Idiff is generated by the difference of Vin and Vout. Hysteresis clock generator limits
Vrampbetween VH and VL for current-mode hysteresis control. The switching frequency and Vclkare determined by hysteresis clock generator with the dependence on the operation mode, which is represented by zero-current detection signal, ZC.
In Fig. 7(b), VinFF (a scaled-down Vin) and Vfb (a scaled-down Vout) are level shifted by folded flipped voltage fol-lowers (FFVFs) to VinFF and Vfb, respectively, as shown in (7) [22], [26]
Vfb− VinFF= V
fb− VinFF. (7)
FFVFs can ensure wide input range and high linearity. The voltage difference crossing on the resistor, Rgm, generates the
Fig. 7. (a) Proposed SCG circuit in the CSC technique. (b) In–out subtractor. (c) Hysteresis clock generator.
error signal, IERROR, and is mirrored to the output of in–out subtractor. Finally, Idiff, which is proportional to the difference between Vin and Vout, is obtained and expressed as (8)
Idiff = 2IERROR = 2Vfb− VinFF Rgm = 2βVout− Vin Rgm ∝ Vout− Vin where β = RF 2 RF 1+ RF 2 VinFF= βVin Vout= βVfb. (8) Fig. 7(c) shows that Idiff is mirrored by transistors M3A and M3Bto constitute discharging currents Id1and Id2, which form the slopes of m2and ma, respectively. The upper bound voltage, VH, defines the starting point of the emulation of the decreasing inductor current. At the start of the switching period, the transistor M5introduces charging current Ic, which is much higher than Id1 and Id2, flowing into the ramp capacitor Cramp to ramp up Vramp rapidly to the VH. On the other hand, the lower bound voltage, VL, determines the end
Fig. 8. ZCD operation. Off-time is too (a) long and (b) short.
time of the decreasing inductor current, that is, the next starting point of the switching period.
In the DCM operation at light loads, switch SWA turns off and switch SWB turns on when the ZCD circuit senses zero inductor current. Transistor I3Bdischarges Crampwith the auxiliary slope ma. Thus, the switching frequency decreases to reduce the switching power loss and efficiency can be improved at light loads, as shown in (5).
B. Zero-Current Detector
The accuracy of ZCD affects the power conversion effi-ciency at light loads. Generally, implementation of zero-current detection involves the use of a simple comparator by directly comparing switching node VX and Vout in Fig. 3 [22], [27]. The comparator offset voltage and the driver’s propagation delay, however, postpone the turnoff timing of the high-side power switch (M2 in Fig. 3), resulting in negative inductor current and the degradation of power conversion efficiency at light loads.
Fig. 8 shows examples of nonoptimal zero-current switch-ing. If the zero-current switching is activated too early, the high-side power switch is disabled with a positive inductor current value. Therefore, the parasitic diode at the high-side power switch will be turned on automatically to conduct the inductor current, as shown in Fig. 8(a). VX is stretched to a voltage value higher than Vout because of a conductive drop voltage of body diode, which is typically 0.7 V. On the other hand, a reverse inductor current occurs with the detection delay of zero inductor current, as shown in Fig. 8(b). Before the high-side power switch turns off, a deep undershoot of VX occurs, and VX is lower than Vout until the ringing phenom-enon happens. This reverse current phenomphenom-enon causes energy loss and low power efficiency.
Thus, the ZCD circuit, which calibrates the zero crossing point according to the comparator offset and propagation delay, is proposed, as shown in Fig. 9. The offset and delay are measured first at the wafer level; then, a seven-bit calibrator is used to calibrate the offset voltage or delay. Three test pads are placed in VX, Vout, and ZCD. A ramped-down test voltage at
VX with an initial value higher than Voutis applied to monitor the ZCD signal. Ideally, the ZCD signal is triggered from low to high when VX is equal to Vout. The input offset voltage of comparator X2 can be obtained according to the delay or
Fig. 9. Proposed ZCD circuit with self-calibration.
Fig. 10. Proposed current sensing circuit.
postponement level of ZCD signal. The resistor string, Rx, is then adjusted by the trimming method to find the optimal zero-current switching point. This test method also can be used to calibrate the delay between ZCD and Pg (gate driver of M2 in Fig. 3) by measuring the delay time. The same process is applied while the triggered signal is changed at Pg.
C. Current Sensing Circuit
Fig. 10 shows the proposed current sensing circuit. Transis-tors MS1, MS2, and MS4are the required switches for turning on/off during sensing procedure. Transistor MS3is the sensing MOS with the scaled down ratio of N-type power MOSFET,
M1. During the inductor-charging period, Ng is equal to Vin to turn on M1 and MS3 simultaneously. MS2 and MS1 are turned off, and MS4 is turned on to transmit the voltage of
VX to node, N1. With the common-gate amplifier, which is composed of MG1 and MG2, node N2 can be tracked to the
N1. Therefore, the sensed current, Isense, which is the scaled down of the inductor current by the aforementioned ratio, is generated automatically by MS3 and mirrored by M3 and
M4 to flow through Resnes. Finally, the current sensed signal,
Vsense, is obtained.
D. Error Amplifier With On-Chip Compensator
Fig. 11 shows the proposed design of the error amplifier and the on-chip compensator. To reduce the die area and achieve
Fig. 11. Schematic view of the error amplifier with the on-chip compensator and the CM technique.
Fig. 12. Synthetic waveform is limited within the hysteresis window defined by the synthetic-ripple control.
the goal of system on a chip, an on-chip compensator using capacitance multiplier (CM) technique is adopted [19], [28]. Capacitor C1, which is a pure capacitor with the value of 6 pF, is greatly amplified by CM technique. The effective capacitance is expressed in (9)
Ccomp= C1× (1 + M) (9)
where M is the mirror ratio between transistors MP51 and transistor MP52. In addition, a small capacitor C2is introduced to reduce the transient noise and adjust transient performance.
IV. SYSTEMSTABILITYANALYSIS
Small-signal modeling and system stability compensation for both conventional synthetic current-ripple regulator and the proposed CSC technique are analyzed and compared as follows.
A. Small-Signal Modeling of Conventional Synthetic Current Tipple Hysteresis Mode Modulator
Fig. 12 shows that the conventional synthetic current-ripple hysteresis mode modulator limits the inductor current ripple within the hysteresis current window (IW) with upper and lower bound current, ip and iv, respectively.
The switching period, Ts, is equal to the summation of
ton and toff in the CCM operation. Considering the small-signal analysis, the value of each variable can be written as the summation of the dc term and its perturbation. After linearization, (11)–(14) can be derived from (10)
IW
Toff(t) = m2(t) Ts(t) = Ton(t) + Toff(t)
Fig. 13. Small-signal model of the conventional current-ripple hysteresis mode modulator. where VW = k IW ˆtoff = − IW · L · ( ˆvout− ˆvin) (Vout− Vin)2 (11) ˆts = ˆton− IW · L · ( ˆvout− ˆvin) (Vout− Vin)2 (12) ˆip = ˆic+ Vinˆton+ Tonˆvin 2L (13) ˆton = 2L Vin(ˆiP− ˆic) − Ton Vinˆvin. (14) Therefore, the d can be derived as (15)
ˆd = Dˆton− Dˆtoff Ts = D 2L Vin ˆip− ˆic − Ton Vinˆv in + L· IW · D (Vout− Vin)2 ˆvout− ˆvin · (Ts)−1. (15) Simplifying (15), can be shown as (16)
ˆd = Fm· ip− ic + Fgˆvin+ Fvˆvout where Fm = 2D· D VW , Fg= − 1 Vout · IW 2D D, Fv = D Vout · IW 2D D. (16) With synthetic current-ripple operation, the inductor current can be expressed as (17)
ic(t) =
gm
Cr
Vin(t) · Ton(t) . (17) Then, the (ˆiP− ˆic) term can be expressed as (18)
(ˆiP− ˆic) = ip Cr+ gm· (2L) Cr . (18)
Thus, (15) can be expressed as (19)
ˆd = Fm· 1+ gm· (2L) Cr ip − Fg · ˆvin+ Fv · ˆvout . (19) TABLE I PARAMETERS IN(21)
Fig. 14. Synthetic waveform is limited with the hysteresis window defined by the CSC technique.
Consequently, the conventional synthetic current-ripple hys-teresis converter is similar to voltage-mode controlled con-verter [29] because the duty variation, ˆd, does not contain the
dc inductor current information, which can be verified in (19). The small-signal model of the conventional synthetic current-ripple hysteresis mode modulator is shown in Fig. 13, and the control-to-output transfer function is shown in (20).
R is the output resistance, and RESR is the ESR of output capacitor Cout Gvc= ˆv out ˆvcomp = Fm · Gvd 1− Fv· Gvd where Gvd = ˆvout ˆd ˆvin=0 = Vout D · 1− s L D2R (1 + s RESRCout) 1+ s L RD2+ s 2 LCo D2 . (20) Therefore, Gvccan be simplified as (21) with two poles and two zeros, including one right-half-plane (RHP) zero and one left-half-plane (LHP) zero [23], [30]–[32]. The parameters are shown in Table I Gvc= Gvc0· 1−ω s z(RHP) 1+ω s z(ESR) 1+2ωζ 0s+ s2 ω2 0 . (21)
Obviously, the system contains a pair of complex pole and two zeros, including one RHP zero and one LHP zero. The frequency response of the conventional synthetic current-ripple hysteresis mode modulator is similar to that of the voltage-mode PWM technique [29]. Thus, PID compensation should be used for the system stability.
B. Small-Signal Modeling of the Proposed CSC Technique
Fig. 14 shows that the CSC technique limits the inductor current within the hysteresis current window, with the upper
Fig. 15. Small-signal model of the proposed CSC technique. TABLE II
PARAMETERS OFSMALL-SIGNALMODEL IN THE
PROPOSEDCSC TECHNIQUE
Fig. 16. Closed-loop diagram of the boost converter using the CSC technique. and lower current bounds ip and iv, respectively. The current sensing circuit (Ri) senses the positive slope of the inductor current. Thus, the on-time value ton is decided by comparing the inductor current with ip. On the other hand, the negative slope of ir, which is formed by the SCG circuit of the CSC technique, can determine the off-time toff value once ir is smaller than the iv.
Similarly, the d can be obtained in (23) from (22)
IW Ts(t) = m 2(t) and ip = iL + m1(t) · dTs (22) ˆd = Fm·
( ˆvcomp− Ri · ˆiL) + Fvˆvout− Fgˆvin
where Fm= 2· D IW · D· Ri , Fg= IW · Ri 2· D · Vout, Fv= D· IW · Ri 2· D · Vout. (23) The small-signal model of the proposed CSC technique is shown in Fig. 15, and Gvc can be derived as (24)
Gvc= ˆv out ˆvcomp = Fm· Gvd 1− Fv· Gvd+ Fm· Gid· Ri. (24)
Fig. 17. Error amplifier with the PI compensator. (b) Bode plot of the closed-loop gain T(s).
Fig. 18. Chip micrograph of the proposed converter. TABLE III
DESIGNSPECIFICATIONS
The designed value of Fm· Gid· Ri is much larger than that of 1− Fv· Gvd. Thus, the Gvc can be simplified as (25), and
Fig. 19. Output ripple and switching frequency in DCM operation under different load current conditions. (a) Iload = 10 mA. (b) Iload = 20 mA. (c)Iload = 30 mA. (d) Iload= 50 mA. (e) Iload= 70 mA. (f) Iload= 300 mA.
the parameters are shown in Table II
Gvc = ˆvout ˆvcomp = Fm· Gvd Fm· Gid· Ri = Gvc0· 1−ω s z(RHP) 1+ω s z(ESR) 1+ωs p1 . (25)
Obviously, the system contains only one dominate pole and two zeros, which includes one RHP zero and one LHP zero. The frequency response of the CSC technique is sim-ilar to that of the current-mode PWM technique [33]–[40]. In other words, PI compensation is suitable and can be easily implemented on the chip [19], [28]. In addition, the advantage of the proposed CSC technique is verified by the removal of the slope compensation required in conventional
Fig. 20. Measurement results of the proposed converter with load transient ranges from (a) 150 to 300 mA and (b) 200 to 400 mA.
current-mode PWM control. That is, the proposed CSC tech-nique simplifies the compensation process and improves the power conversion efficiency at light loads because of the load-dependent switching frequency, which is more suitable for portable devices to extend the battery life.
C. Loop Gain Analysis With PI Compensator for the System Stability
Fig. 16 shows the closed-loop diagram of the boost con-verter using the CSC technique. The closed-loop gain T(s) is expressed in (26). β is the sensor gain, which is equal to
RF 2/(RF 1+RF 2). Gc(s) is the compensation transfer function composed of an error amplifier and a PI compensator, as shown in Fig. 17(a). The PI compensator contributes one low-frequency pole-zero pair, (ωpc andωz)
T(s) = β · Gvc(s) · Gc(s). (26) ωpc is the dominant pole and ωz cancels the effect of the output pole ωp1. As a result, the gain-bandwidth of the system expands. Simultaneously, the dc gain is enlarged to enhance load regulation of the system because of the high-gain error amplifier. The Bode plot of the proposed system with the compensator is shown in Fig. 18(b). ωpc and ωz are expressed as (27). gm and Ro are the transconductance
Fig. 21. Measurement results of the proposed converter with line transient changes from (a) 3.2 to 4.5 V and (b) 4.5 to 3.2 V.
and the output resistance of the error amplifier, respectively.
Rz and Ccomp are the compensation resistor and capacitor, respectively ωpc= 2π fpc= 1 Ro· Ccomp and ωz = 2π fz = 1 Rz· Ccomp. (27) V. EXPERIMENTALRESULTS
The test chip was fabricated using the UMC 0.3-μm BCD process with a small inductor for compact printed-circuit board area. The chip micrograph is shown in Fig. 18. The chip area is 1553μm × 1225 μm, and the specifications of this proposed design is listed in Table III.
Fig. 19 shows the output ripple and switching frequency in the DCM and CCM operations under different load cur-rent conditions. The variable switching frequency can ensure reduction of the switching power loss.
The output voltage and the inductor current waveforms dur-ing load transient response are shown in Fig. 20. The settldur-ing times when Vin = 3.6 V are ∼ 15 and 16 μs when the load
Fig. 22. Measurement results of the proposed converter with load transients (9) from (a) 25 to 200 mA and (b) 200 to 25 mA.
transient current is 150–300 mA, and ∼ 27 and 21 μs when the load transient is 200–400 mA, respectively. Fig. 21 shows the line transient response when the input voltage changes from 3.2 to 4.5 V with the loading of 200 mA. The overshoot voltage and drop voltage at the output are 51 and 34 mV, respectively. Fig. 22 shows the transient waveforms from DCM to CCM and from CCM to DCM. The light load is 25 mA and the heavy load is 200 mA. The smooth transient corresponds to the proposed operation shown in Fig. 4(c). In Fig. 22(a), the boost converter is operating in DCM at light load. Once the load current increases, the inductor current starts to increase to depart from the DCM mode. By the CSC technique, the switching frequency increase smoothly. This can be verified by observing inductor current ripple. The gradual decrease of the inductor current ripple shows the increase of switching frequency. On the contrary, Fig. 22(b) shows smooth transition from CCM to DCM operation.
The relationship among load current, switching frequency, and output ripple is shown in Fig. 23(a). The conventional PWM controlled boost converter has constant switching fre-quency of 5 MHz at both light and heavy loads. With the proposed CSC technique, the switching frequencies at different loads are almost the same in the CCM operation. On the other hand, the switching frequency decreases with the decrease in load current in the DCM operation. The input and output
Fig. 23. Performance of (a) switching frequency and output ripple and (b) efficiency during the load range.
TABLE IV
COMPARISONTABLE
voltages are 3 and 5 V, respectively. Fig. 23(b) shows the efficiency comparison between conventional boost converter with the PWM control, as shown in Fig. 23(a) and the proposed structure. When the CSC technique is disabled, the proposed boost converter acts as a conventional PWM controlled converter. The switching frequency of 5 MHz is generated by fixed-frequency CLK generator in Fig. 18. The power efficiency is deteriorated owing to the switching loss at light loads with a constant switching frequency. When acti-vating the CSC technique, the fixed-frequency CLK generator
is disabled. The switching frequency of the proposed boost converter can be effectively reduced at light load. As a result, the efficiency can be maintained at 78% at load current of 10 mA, demonstrating that the efficiency can be kept high with the implementation of the CSC technique. Table IV shows the performance comparison with prior arts. To compare with prior arts, FOM is defined in (28)
FOM≡ ηmin· Iload
ripple· droop · L · C. (28) With higher light-load efficiency, ηmin, and larger load range, Iload, larger FOM can be obtained. On the contrary, output ripple, load transient droop, inductor, and capacitor values should be kept small. As shown in Table IV, the proposed CSC technique has the largest FOM and the best performance compared with prior arts.
VI. CONCLUSION
The proposed CSC technique for boost converters over-comes the difficulty of implementing a current-ripple hystere-sis control and improves efficiency over a wide load range. The CSC technique offers high accuracy similar to that of the current-mode control without the need for complex slope compensation. The load-dependent switching frequency at light loads results in high power conversion efficiency. The experimental results show that the output voltage ripple can be kept <50 mV over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA.
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Yi-Ping Su was born in Taipei, Taiwan. She received
the B.S. degree from the Department of Electri-cal Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2009. She is currently pur-suing the Ph.D. degree with the Institute of Elec-trical Engineering, National Chiao-Tung, Hsinchu, Taiwan.
She is a member of the Mixed Signal and Power Management IC Laboratory, Institute of Electrical Engineering, National Chiao-Tung University. Her current research interests include power management and analog integrated circuits design.
Yean-Kuo Luo was born in Tainan, Taiwan. He
received the B.S., M.S., and Ph.D. degrees from the Institute of Microelectronics, National Cheng-Kung University, Tainan, Taiwan, in 2001, 2003, and 2012, respectively.
He is a Faculty Member with the Mixed Signal and Power Management IC Laboratory, Institute of Electrical Control Engineering, National Chiao-Tung University, Hsinchu, Taiwan.
Yi-Chun Chen was born in Taoyuan, Taiwan. He
received the B.S. degree in electrical and control engineering and the M.S. degree from the Depart-ment of Electrical Engineering and Institute of Electrical Control Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 2008 and 2010, respectively.
He is currently with Richtek Technology Corpo-ration, Chupei City, Taiwan. He is a Member of the Mixed Signal and Power Management IC Labora-tory, National Chiao-Tung University. His current research interests include power-management-integrated circuit design and analog-integrated circuits.
Ke-Horng Chen (M’04–SM’09) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
He was a part-time IC Designer with Philips, Taipei, from 1996 to 1998. From 1998 to 2000, he was an Application Engineer with Avanti, Ltd., Taipei. From 2000 to 2003, he was a Project Man-ager with ACARD, Ltd., where he was engaged in designing power management ICs. He is currently the Director of the Institute of Electrical Control Engineering and a Professor with the Department of Electrical Engineering, National Chiao-Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or co-author of more than 100 papers published in journals and conferences and holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display TV, and red, green, and blue (RGB) color sequential backlight designs.
Dr. Chen has served as an Associate Editor of the IEEE TRANSACTIONS
ONPOWERELECTRONICSand the IEEE TRANSACTIONS ONCIRCUITS AND
SYSTEMS—PARTII: EXPRESSBRIEFS. He has been a member of the Editor-ial Board of Analog Integrated Circuits and Signal Processing since 2013. He is on the IEEE Circuits and Systems (CAS) VLSI Systems and Applications Technical Committee, and the IEEE CAS Power and Energy Circuits and Systems Technical Committee. He joins Society for Information Display and International Display Manufacturing Conference Technical Program Sub-Committees. He was the Tutorial Co-Chair of IEEE Asia Pacific Conference on Circuits and Systems in 2012. He is the Tack Chair of Integrated Power Electronics of IEEE International Conference on Power Electronics and Drive Systems for 2013. He is a Technical Program Co-Chair of IEEE International Future Energy Electronics Conference for 2013.
