高性能長壽命可撓式有機薄膜電晶體元件之製作與研究(III)

行政院國家科學委員會專題研究計畫 成果報告

高性能長壽命可撓式有機薄膜電晶體元件之製作與研究 (III)

研究成果報告(精簡版)

計 畫 類 別 ： 個別型

計 畫 編 號 ： NSC 98-2221-E-011-141-

執 行 期 間 ： 98 年 08 月 01 日至 99 年 07 月 31 日 執 行 單 位 ： 國立臺灣科技大學電子工程系

計 畫 主 持 人 ： 范慶麟

計畫參與人員： 碩士班研究生-兼任助理人員：林禹佐 碩士班研究生-兼任助理人員：黃兆弘 博士班研究生-兼任助理人員：楊宗憲 博士班研究生-兼任助理人員：邱秉誠

報 告 附 件 ： 出席國際會議研究心得報告及發表論文

處 理 方 式 ： 本計畫涉及專利或其他智慧財產權，2 年後可公開查詢

中 華 民 國 99 年 09 月 28 日

高性能長壽命可撓式有機薄膜電晶體元件之製作與研究(III)

“Investigation and fabrication of flexible organic thin film transistor devices with high performance and long lifetime (III)”

計畫編號：NSC98-2221-E-011-141

執行期間：98 年 08 月 01 日 至 99 年 07 月 31 日 主持人：范慶麟 國立台灣科技大學電子工程系副教授

I. 中文摘要

本計劃利用自行組裝之高密度電漿化學氣相 沉積系統製作出低於 100 ℃的二氧化矽(SiO₂

)薄

膜並應用於有機薄膜電晶體(OTFTs)之閘極絕緣 層上，研究結果顯示有機薄膜電機體搭配此低溫

(< 100 ℃)二氧化矽閘極絕緣層可獲得良好的元件

電特性，且其元件電特性亦可比得上與有機薄膜 電晶體搭配高溫沉積之二氧化矽閘極絕緣層。因 此，本計畫所提出之低溫(< 100 ℃)二氧化矽閘極 絕緣層是非常適合有機薄膜電晶體的低溫製作應 用於塑膠基板上。

關鍵字 關鍵字 關鍵字

關鍵字：：：：有機薄膜電晶體、五苯環素、二氧化矽、

閘極絕緣層。

I. Abstract

We report on a low-temperature-processed organic thin-film transistor (OTFT) using hollow-cathode chemical vapor deposition (HC-CVD) SiO

₂

as the gate insulator below a processing temperature of 100 ℃. The physical properties of SiO

2

deposited using the HC-CVD are studied using various deposition temperatures, RF powers and TEOS/O

2

ratios. OTFTs with HC-CVD-deposited SiO

2

gate insulators were fabricated below 100 ℃ without the gate insulator surface treatment. We obtained good OTFT electrical characteristics including a threshold voltage (V

TH

) of -2.9 V, a field-effect mobility (µ

FE

) of 2.3 × 10

^-2

cm

²

V

^-1

s

^-1

, a sub-threshold swing (SS) of 0.516 V/decade and an on/off current ratio (I

_on

/I

_off

) of 1.27 × 10

⁵

. To our knowledge, this is the first time that the low-temperature deposition (<100 ℃) of SiO

₂

using the HC-CVD technique was successfully applied to OTFT gate insulator fabrication.

Keywords: organic thin film transistor (OTFT), pentacene, SiO

2

, gate insulator.

II. Introduction

In recent years, organic thin-film transistors

(OTFTs) have been intensely investigated due to their flexibility, lightweight and especially low cost for potential use in applications such as radio-frequency identification tags (RFID), large-area sensors and active-matrix flat panel display backplanes (AMFPDs) [1-4]. In general, silicon dioxide (SiO

2

) is one of the most widely used gate insulators in solid-state electronic and optoelectronic devices. For the conventional OTFT SiO

₂

-based gate insulator, the thermal oxide grown in a furnace is commonly used as the gate insulator deposition technique due to its superior electrical properties. However, such deposition temperatures are too high for plastic substrate applications.

Because most plastic substrates have upper limit working temperatures below 200 ℃, for example, PES, PEN, etc, the OTFT fabrication temperatures must be lowered to be compatible with plastic substrates. In a recent report, Lee et al demonstrated that OTFTs fabricated onto a glass substrate below 300 ℃ using plasma-enhanced chemical vapor deposition (PECVD)-deposited SiO

2

as the gate insulator [5]. However, this fabrication temperature is still not low enough for OTFT applications on plastic substrates. Park et al demonstrated that OTFTs could be fabricated onto a plastic substrate below 200 ℃ using e-gun deposited SiO

2

as the gate insulator [6]. Although this fabrication temperature is compatible with plastic substrates, e-gun-deposited SiO

2

generally exhibited quite a rough surface, which may have a detrimental impact on the OTFT electrical performance.

Hollow-cathode chemical vapor deposition

(HC-CVD) is a modified version of the

plasma-assisted CVD [7]. Because its geometry can

promote hot electronic oscillations inside the

cathode tube, thereby producing a hollow-cathode

discharge and exhibiting a plasma density of one to

two orders of magnitude higher than conventional dc

diode discharge, such a process can produce a high

electronic flux with low ion energy onto the

substrate. This process facilitates low-temperature

growth and simultaneously enhances the device performance. In this work, we construct a HC-CVD system to deposit SiO

2

at a process temperature below 100 ℃, to serve as the gate insulator for OTFTs. The physical properties of SiO

₂

deposited using HC-CVD are studied using various process parameters, including the deposition temperature, RF power and TEOS/O

2

ratio. The OTFTs with HC-CVD-deposited SiO

₂

gate insulator showed good electrical performance without the gate insulator surface treatment. These results show that low-temperature-processed OTFTs, below 100 ℃, can be achieved using HC-CVD SiO

₂

as the gate insulator. Our topic is focused on the fabrication and application of the low-temperature SiO

2

gate insulator for OTFTs. From our experiment’s results, OTFTs fabricated below 100 ℃ with a HC-CVD SiO

2

gate insulator can indeed perform similar to those fabricated at higher temperatures. Thus, we believe that low-temperature-processed (<100 ℃) OTFTs delivering a good performance will enable potential applications on plastic substrates.

III. Experimental details

The HC-CVD system employed in the experiment is illustrated in figure 1. A radio frequency of 13.5 MHz was used to excite the hollow-cathode plasma.

Gas flows were regulated by mass flow controllers (PC-540, Protec Instruments), and the chamber pressure was measured using a pressure controller (600 series, MKS). The cathode was a cylindrical-shaped tantalum tube, 23 cm in length and 8 cm in diameter, locked into a stainless steel holder. The distance between the cathode and the substrate was adjustable. The substrate holder was the anode, made of a 10.5 × 10.5 cm aluminum frame fixed onto a water-cooled and tungsten-wire-heated holder for adjusting a wide range of temperatures.

Fig. 1. A schematic diagram of the HC-CVD system.

The SiO

₂

films were deposited onto n-Si wafers using nitrogen, oxygen and tetraethoxysilane (TEOS) precursors using the HC-CVD system with varied deposition temperatures from 80 to 350 ℃, RF power from 250 to 350 W and TEOS/O

₂

ratios from 65/100 to 65/200. The films were characterized using the chemical wet etching rate (HF:H

2

O = 1:50), refractive index and Fourier transform infrared spectroscopy analysis. The OTFTs were fabricated, with process temperatures maintained below 100 ℃, onto a heavily doped n-type silicon wafer (resistivity

<0.020 Ω cm, 500 µm thick) acting as the bottom gate electrode with a bottom contact structure. 130 nm thick SiO

2

, acting as the gate insulator, was deposited using the HC-CVD system under an RF power of 300 W at 50 mTorr. The substrate temperature was maintained at 80 ℃ during the deposition process. The flow rates of N

2

, O

2

and TEOS were fixed at 80, 200 and 65 sccm, respectively. The metal Pt/Cr (70 nm/2 nm) source-drain electrodes were deposited onto the gate insulator using the lift-off method. Finally, pentacene (purchased from Sigma Aldrich), without any further purification, was deposited by thermal evaporation (base pressure of 2 × 10

^-6

Torr) at a rate of 0.1-0.2 Å s

^-1

to a total thickness of 50 nm with the substrate held at room temperature. The source-drain width and length of the devices were 500 µm and 10

µm, respectively. The OTFTs were stored in a glove

box (O

2

< 0.1 ppm and H

2

O < 0.1 ppm) and measured at room temperature in a dark environment using a semiconductor parameter analyzer (HP4145B, Hewlett-Packard). The surface morphology of the pentacene film was observed using an atomic force microscope (AFM).

IV. Results and discussion

4.1. Characterization of HC-CVD SiO

2

films Figure 2 shows the relationship between the SiO

2

deposition rate and deposition temperature under RF powers of 250 W, 300 W and 350 W, respectively. It was found that the deposition rate increased with increasing RF power through the whole deposition temperature range. This increase in deposition rate with RF power can be explained by an enhanced generation of precursors and radicals because RF power directly affects the extent of dissociation of gas molecules. In addition, the deposition rate increased with the deposition temperature from 80 to 150 ℃ and then started to decrease above 150 ℃.

This behavior is typical of adsorption-controlled

reactions. An increase in the deposition temperature

increases the kinetic energy of the active species,

which also increases the desorption probability and thus reduces the adsorption probability [8].

Therefore, at a deposition temperature below 150 ℃, the chemical adsorption-reaction dominates and the deposition rate increases with temperature. At a deposition temperature above 150 ℃, the desorption region dominates and the deposition rate decreases with temperature.

Figures 3(a) and (b) show the dependences of the SiO

2

etching rate and refractive index at different deposition temperatures for the TEOS/O

2

ratios of 65/100 and 65/200, respectively. It was found that the etching rate of SiO

2

films in diluted HF significantly decreased with increasing deposition temperature from 80 to 350 ℃, as shown in figures 3(a) and (b). It is well known that SiO

2

deposited at low temperatures has an essentially lower atomic bonding energy and tends to be less dense [9, 10].

Thus, SiO

₂

deposited at 350 ℃ was denser than the other samples, resulting in the lowest etching rate.

With a further decrease in TEOS/O

₂

ratio from 65/100 (0.65) to 65/200 (0.325), the etching rate of SiO

₂

films through the entire deposition temperature range was found to decrease by about 50%, as shown in figures 3(a) and (b). It has been reported [11] that SiO

2

deposited at low temperatures with higher TEOS/O

2

ratios will cause the ethoxy groups of the TEOS molecule to get incorporated into the film disrupting the connectedness of the SiO

4

tetrahedra resulting in a porous low density film along with a high etching rate. In addition, Vallée et al also reported that SiO

2

deposited with higher TEOS/O

2

ratios, particularly at low temperatures, produced porous films along with high void fractions and high etching rates [12]. Thus, the TEOS/O

₂

ratio is an important parameter in controlling the quality of the deposited films. The refractive index values are also plotted in figure 3. The refractive index of SiO

₂

films in figures 3(a) and (b) was found to be higher than the thermal oxide value of 1.46. This higher refractive index was attributed to the formation of non-stoichiometric films. However, with a further increase in deposition temperature, the refractive index of SiO

2

films tends to shift toward the value of 1.46. This means that some changes in the film structure, such as changes in the film composition and variation in the film density, must have occurred.

These results are consistent with the tendency

between the etching rate and the deposition temperature, which found that film quality became more thermal-like for increasing deposition temperature.

Fig. 2. Dependence of SiO

₂

deposition rate on deposition temperature at different RF powers.

Fig. 3. SiO

₂

etching rate and refractive index versus

deposition temperature at TEOS/O

₂

ratios of (a) 65/100 and

(b) 65/200.

Figure 4 shows the typical FTIR spectrum obtained from SiO

2

deposited at 80 ℃. The three characteristic absorption bands due to Si-O-Si were observed at 1065 cm

^-1

, 810 cm

^-1

and 450 cm

^-1

corresponding to stretching, bending and rocking motions of oxygen atoms, respectively, and absorption bands at 930 cm

^-1

and 3300 cm

^-1

assigned to the OH vibration of the associated Si-OH and water, respectively. This Si-OH bond was detected from the FTIR spectrum and is due to the incorporation of OH-related groups in the film during deposition and water absorption by exposure to air after deposition. It has been reported that SiO

₂

deposited at lower deposition temperatures has higher pore volume in its matrix, which favors the incorporation of water when it is exposed to the ambient atmosphere [9, 13]. Thus, we presume that SiO

2

deposited at 80 ℃ may contain more vacant defects, which may affect the film properties, such as film density and stability.

Fig. 4. FTIR spectrum of SiO

₂

deposited at 80 ℃

℃℃℃ by the

HC-CVD system.

4.2. Electrical characterization on OTFTs OTFTs with HC-CVD-deposited SiO

2

gate insulators were fabricated below 100 ℃ without the gate insulator surface treatment. The device output (I

DS

versus V

DS

) and transfer (log10|I

DS

| versus V

GS

) characteristics with a W/L of 500 µm/10 µm are shown in figure 5. The OTFTs showed good saturation behavior as well as a high on-current of 6.79 µA. The field-effect mobilities and threshold voltages were calculated in the saturation regime by fitting the |I

_DS

|

^1/2

versus V

_GS

data to the square law:

_{DS FE OX}

(

_{GS TH}

)

²

2 V V

L C W

I = µ − , (1)

Fig. 5. (a) The output characteristics (I

_DS

versus V

_DS

) of OTFTs fabricated below 100 ℃

℃℃. (b) The transfer ℃

characteristics (I

_DS

versus V

_GS

) of OTFTs fabricated below 100 ℃

℃℃℃.

where µ

FE

is the field-effect mobility, C

OX

is the capacitance density of the gate insulator, V

TH

is the threshold voltage, and W (width) and L (length) are the dimensions of the semiconductor channel defined by the source and drain electrodes. The maximum and minimum values of drain current (I

DS

) at a drain voltage (V

DS

) of -10 V are designated as I

on

(on-current) and I

_off

(off-current), respectively

[14-16]. The OTFTs fabricated below 100 ℃

showed a field-effect mobility (µ

FE

) of 2.3 × 10

^-2

cm

²

V

^-1

s

^-1

, a threshold voltage (V

TH

) of -2.9 V, a

sub-threshold swing (SS) of 0.516 V/decade and an

on/off current ratio (I

on

/I

off

) of 1.27 × 10

⁵

at V

DS

of

-10 V. Normally, the OTFT performances,

particularly the carrier mobility and on-current, can

be strongly influenced by the grain size of the

semiconductor [17-20]. The large grains can

Fig. 6. AFM image (10 × 10 µm

²

) of pentacene grown on 80

℃

℃

℃

℃ deposited SiO₂

.

decrease the carrier scattering during carrier transport to result in good device performances. The smaller grains tend to have more grain boundaries, resulting in the carrier transport through this material to be significantly degraded by the grain boundaries.

Figure 6 shows the grain morphology of the pentacene film grown on the 80 ℃ deposited SiO

2

gate insulator. A large average grain size of about 4.6 µm was observed, and therefore it led to a reduction of the grain boundaries at the channel region. This may explain why the mobility and on-current are greatly enhanced. Gate leakage current through the 80 ℃ deposited SiO

2

gate insulator is also plotted in figure 5(b). The gate leakage current for OTFTs was measured while gate voltage swept from 5 V to -20 V when V

_DS

was -10 V. It was found that the inferior gate leakage current eventually resulted in a low I

on

/I

off

of 10

⁵

. We presume that the large gate leakage current might have come from a leak path through the gate insulator, due to the less dense formed SiO

2

at 80 ℃.

However, OTFTs fabricated below 100 ℃ still exhibited a sufficient magnitude of I

_on

/I

_off

for electrical circuit applications and even better than those in published papers on SiO

2

-based gate

insulators produced using low-temperature deposition techniques, such as PECVD and e-gun evaporator [5, 6]. Table 1 summarizes the detailed device parameters, where the data from OTFTs using the above-mentioned techniques are included for comparison. As can be seen in table 1, the performance of our below 100 ℃ fabricated OTFT is comparable with those of other low-temperature-fabricated devices, but with the additional merit of a better SS, higher I

_on

/I

_off

and lower fabrication temperature.

V. Conclusions

Low-temperature OTFTs were fabricated using HC-CVD SiO

2

as the gate insulator below a processing temperature of 100 ℃. The physical properties of SiO

2

deposited using HC-CVD were also studied using various deposition temperatures, RF powers and TEOS/O

₂

ratios. The OTFTs without the gate insulator surface treatment showed good electrical characteristics, comparable with those in published papers with SiO

2

-based gate insulators using low-temperature deposition techniques. These results confirm that a SiO

₂

gate insulator, deposited using HC-CVD at a deposition temperature of 80 ℃, can be used as a good candidate for low-temperature-processed (<100

℃)

OTFT applications.

Acknowledgments

This work was supported by the National Science Council of Republic of China (contract nos NSC 97-2221-E-011-135 and NSC 98-2221-E-011-141), and equipment support was provided by the National Nano Device Laboratory.

References

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Sakurai T 2004 Proc. Natl Acad. Sci. USA 101 9966

Table I. The electrical characteristics comparison for OTFTs with PECVD, e-gun and HC-CVD deposited SiO

₂

as the gate

insulator, respectively.

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[4] Zhou L, Park S, Bai B, Sun J, Wu S C, Jackson T N, Nelson S, Freeman D and Hong Y 2005 IEEE Electron

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[7] Liang G T and Hong F C N 1998 J. Mater. Res. 13 3114 [8] Patrick W J, Schwartz G C, Chapple-Sokol J D,

Carruthers R and Olsen K 1992 J. Electrochem. Soc. 139 2604

[9] Baklanov M R, Vasilyeva L L, Gavrilov T A, Dultsev F N, Mogilnikov K P and Nenasheva L A 1989 Thin Solid

Films 171 43

[10] Idris I and Sugiura O 1998 Japan. J. Appl. Phys. 37 6562 [11] Deshmukh S C and Aydil E S 1994 Appl. Phys. Lett. 65

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[12] Vall´ee C, Goullet A, Nicolazo F, Granier A and Turban G 1997 J. Non-Cryst. Solids 216 48

[13] Theil J A, Tsu D V and Lucovsky G 1990 J. Electron.

Mater. 19 209

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[17] Horowitz G and Hajlaoui M E 2000 Adv. Mater. 12 1046 [18] Tan H S, Cahyadi T, Wang Z B, Lohani A, Tsakadze Z,

Zhang S, Zhu F R and Mhaisalkar S G 2008 IEEE

Electron Devices Lett. 29 698

[19] Carlo A D, Piacenza F, Bolognesi A, Stadlober B and Maresch H 2005 Appl. Phys. Lett. 86 263501

[20] Moon M R, Nam E, Woo J, Lee S, Park K, Jung D, Kim

H and Lee H J 2009 Thin Solid Films 517 4161

國科會 國科會 國科會

國科會補助 補助 補助 補助專題研究計畫成果報告自評表 專題研究計畫成果報告自評表 專題研究計畫成果報告自評表 專題研究計畫成果報告自評表

請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用 價值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）、是 否適合在學術期刊發表或申請專利、主要發現或其他有關價值等，作一綜合評 估。

1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估

■ 達成目標

□ 未達成目標（請說明，以 100 字為限）

□ 實驗失敗

□ 因故實驗中斷

□ 其他原因 說明：

2. 研究成果在學術期刊發表或申請專利等情形：

論文：■已發表 □未發表之文稿 □撰寫中 □無 專利：□已獲得 ■申請中 □無

技轉：□已技轉 ■洽談中 □無 其他：（以 100 字為限）

3. 請依學術成就、技術創新、社會影響等方面，評估研究成果之學術或應用價 值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）（以 500 字為限）

本計劃利用自行組裝之高密度電漿化學氣相沉積系統製作出低於 100 ℃的二氧化矽薄膜 並應用於有機薄膜電晶體(OTFT)之閘極絕緣層上，如圖一所示。研究結果顯示有機薄膜電機 體搭配此低溫(< 100 ℃)二氧化矽閘極絕緣層可獲得良好的元件電特性，且其元件電特性亦可 比得上與有機薄膜電晶體搭配高溫沉積之二氧化矽閘極絕緣層。因此，本計畫所提出之低溫

(< 100 ℃)二氧化矽閘極絕緣層是非常適合有機薄膜電晶體的低溫製作並有利於與有機發光二

極體(OLED)的整合於塑膠基板來達成主動式驅動可撓面板(AMOLED)並應用在新穎的電子產 品 上 來 提 升 國 內 軟 性 電 子 產 業 的 競 爭 力 。 目 前 本 計 畫 之 研 究 成 果 已 投 稿 至 國 際 期 刊

Semiconductor Science and Technology 並已被刊登(Vol. 25, p. 075006, 2010.)。

圖一圖一

圖一圖一、本實驗室利用自行組裝之高密度電漿化學氣相沉積系統製作出低溫(<100 ℃)二氧化矽 閘極絕緣層並應用於可撓式有機薄膜電晶體元件。

國科會補助專題研究計畫項下出席國際學術會議心得報告 國科會補助專題研究計畫項下出席國際學術會議心得報告 國科會補助專題研究計畫項下出席國際學術會議心得報告 國科會補助專題研究計畫項下出席國際學術會議心得報告

日期：99 年 9 月 27 日

一、參加會議經過

研討會第一天(6 月 22 日)：於台灣時間早上 08:45 從桃園國際機場搭乘全日空班機飛往日 本成田國際機場，並於日本時間 13:00 抵達，隨即搭乘機場巴士至東京羽田機場，於日本 時間 17:45 從羽田機場搭乘全日空班機飛往富山，並於 18:45 抵達富山，隨後抵達富山國際 會議中心辦理辦到(Registration)，報到完後隨即前往飯店 check in 並休息，準備參加明天議 程。

研討會第二天(6 月 23 日)：於早上 10:00 至下午 17:30 參加 Oral Session A1(Organic TFT)，

一連串聽了好幾場受邀學者與學生的演講，而令學生最感興趣的演講內容有三場，分別為 來自韓國的 Jin Jang 教授、日本的 Takao Someya 教授及日本的 Hiroki Maeda 教授。其中韓 國的 Jin Jang 教授所演講的題目與學生目前在研究的主題有些類似，而在 Jin Jang 教授的 演講內容中，探討了照光對 Organic TFT 與 Oxide TFT 的影響以及劣化機制，教授也藉此 把元件經照光過後的現象一一清楚的分析並說明，因此學生在此場演講中收穫良多並產生 許多靈感可以實現在學生目前的研究主題上；而另外兩場之所以感興趣的原因是因為兩位 日本教授把 Organic TFT 的應用產品一一的介紹，而且也把他們目前的研究方向順帶一提 的介紹，並在演講內容中秀出了他們所製作出的大面積感應器(Sensor)與 UXGA Organic

TFT 可撓式面板，令台下的聽眾嘆為觀止，而學生在本年度計畫所提出的研究內容也是關

於可撓式 Organic TFT，恰巧藉由兩位大師級的教授對軟性電子的介紹，可讓學生在 Organic

TFT 研究領域上變得更寬廣。聽完演講後，於晚上 18:00 參加大會辦的晚宴，隨後於晚宴

完後學生去準備接下來的 Poster presentation。在 Organic and Inorganic Materials and Devices

I Poster Session 海報展覽中，有 67 張來自各國的研究團隊參與，在海報展覽中，學生也與

其他參展中的教授與學生討論自己的研究內容，並一一回答問題，而學生也到韓國 Jin Jang 教授所參展的海報攤位前，向教授討教了幾個有關照光在 Organic TFT 上的幾個問題，Jin

Jang 教授也和藹可親的為學生解答，令學生感謝不已。海報展於晚上 20:00 結束，隨後學

生就收拾海報並返回飯店休息，準備參加明天議程。

研討會第三天(6 月 24 日)：於早上 10:00 至中午 12:00 參加 Oral Session A6(Oxide TFT(1)) 與 A7(Oxide TFT(2))，一連串聽了有關 Oxide TFT 的材料介紹、電氣特性改善技術介紹與 元件產品應用等，讓學生有助於除了 Organic TFT 研究領域外而在 Oxide TFT 研究領域上 獲得許多知識，讓學生增廣見聞。聽完演講後，於下午 13:20 至 17:40 參加了 Organic and

Inorganic Materials and Devices II & Nano Technologies Poster Session，在此海報展覽中有來

計畫編號 NSC 98－2221－E－011－141－

計畫名稱

高性能長壽命可撓式有機薄膜電晶體元件之製作與研究(III)

出國人員

姓名

^邱秉誠

服務機構 及職稱

國立台灣科技大學 電子所/博士班研究生

會議時間 99 年 6 月 22 日至 99

年 6 月 25 日

會議地點

日本富山 (富山國際會議中心)

會議名稱 (中文)

有機及無機電子材料與相關奈米科技國際研討會

(英文) Organic and Inorganic Electronic Materials and Related Nanotechnologies

發表論文 題目

(中文)

五苯環有機薄膜電晶體之製作搭配多種低溫化學氣相沉積二氧化矽薄膜

作為閘極絕緣層

(英文) Fabrication of Pentacene-based Organic Thin-Film Transistor with Various

Low-Temperature CVD SiO

2

as Gate Insulator

主題與內容，也因此讓學生認識了許多朋友，同時也感謝成功大學陳貞夙教授的學生，陪 伴學生參與了這幾天的會議過程及會議結束後的育樂活動。海報展覽結束後於晚上 18:00 參加大會舉辦的晚宴，於 20:00 晚宴結束後，隨即返回飯店休息，準備參加明天最後一天 的議程。

研討會第四天(6 月 25 日)：於早上 9:00 至早上 11:40 參加了 Oral Session A8(Organic

Photovoltaic Cells(2))與 A9(Organic Devices)，在這兩小時多的演講中，有來自日本受邀的

學者與學生針對有機太陽能電池及有機發光二極體做了許多介紹，不管是結構上、材料上 以及光電效率上做了許多詳細的分析探討，讓學生對於有機研究領域嘆為觀止。演講完畢 後，研討會於早上 11:40 舉行閉幕，隨後學生就自行在富山國際會議中心附近逛逛及拍照 作紀念，逛完後隨即回飯店整理行李，準備明天回台灣。

回程(6 月 26 日)：於早上 10:00 自飯店 check out 後，隨即搭乘公車自富山機場，隨後搭乘 全日空班機飛往東京羽田機場，於中午 12:15 抵達東京，隨後學生在東京待了半天並進行 觀光旅遊，並於晚上 19:00 搭乘全日空班機飛回台灣桃園國際機場，結束此次研討會之行 程。

二、與會心得

此次前往日本參加EM-NANO2010研討會，是學生第一次自行前往其他國家參加國際性研討會，

於研討會期間除了在相關專業領域有相當大的收穫外，第一次與英文溝通的方式與當地居民與學 者進行溝通與討論，藉由此次外文溝通經驗，讓學生更有勇氣以英文與他人交談，此外，在日本 生活的五天中體驗到與在台灣不同的風俗名情外，也充分感受到日本人民在服務態度、交通禮貌 及生活環境維護的用心與努力，這可供作為我們台灣人民的參考模範。這次的行程讓我見識到不 一樣的人、事、物，不僅提升自己的專業知識上，也讓自己知道有哪些不足許要加強的地方，我 很珍惜此次難得的機會，讓我受益良多。

三、考察參觀活動(無是項活動者略)：

四、建議：

希望國科會能每年補助本實驗室研究人員出席國外研討會之相關費用。

五、攜回資料名稱及內容

大會手冊(Abstract Booklet of the 2010 International Symposium on Organic and Inorganic

Electronic Materials and Related Nanotechnologies )：內容為此研討會四天之議程安排與相關研究主

題之內容摘要。

六、其他

國科會補助計畫衍生研發成果推廣資料表

日期 2010年09月28日

國科會補助計畫

研發成果名稱

發明人 (創作人)

技術說明

技術移轉可行性及 預期效益 技術/產品應用範圍

產業別

計畫名稱:

計畫主持人:

計畫編號: 學門領域:

(中文)

(英文)

成果歸屬機構

(中文)

(英文)

高性能長壽命可撓式有機薄膜電晶體元件之製作與研究(III) 范慶麟

98 -2221-E -011 -141 - 固態電子 有機薄膜電晶體之疏水性二氧化矽閘極絕緣層製造方法

Fabrication of hydrophobic SiO2 gate insulator for organic thin-film transistor

國立臺灣科技大學 范慶麟,邱秉誠,林昶志

本專利利用一個簡易的沉積方法來製造具疏水性的二氧化矽薄膜作為有機薄膜 電晶體之閘極絕緣層。此疏水性二氧化矽閘極絕緣層即藉由電漿化學氣相沉積 系統並使用四乙氧基矽烷前驅物在一百度以下製造。由於四乙氧基矽烷前驅物 在一百度以下會有部分乙氧基矽烷分子未解離而殘留下疏水性的甲烷官能基。

然而這個疏水性的甲烷官能基會使二氧化矽薄膜的表面呈現疏水的特性，也因 此幫助了後續有機主動層(五苯環素)的結晶成長，進而提升有機薄膜電晶體的 元件特性。

This patent used a simple deposition method to fabricate hydrophobic SiO2 as an organic thin-film transistor gate insulator. The SiO2 gate insulator, deposited at 80 ℃ by plasma CVD using tetraethoxysilane (TEOS) precursor gas, contained hydrophobic methyl (CH3) functional groups due to incompletely dissociated TEOS molecules. These CH3 functional groups made the SiO2 surface more hydrophobic, and thus facilitated crystalline growth of the pentacene film resulting in enhanced device performance.

其他工業製品製造業

有機薄膜電晶體

由於本技術製程溫度極低且不涉及其他複雜製程，所以有利於有機薄膜電晶體的低溫 製作並與有機發光二極體的整合於塑膠基板來達成主動式驅動可撓式面板，使其可運 用在新穎的消費性電子產品上來提升軟性電子產業價值與增進國內面板廠商之競爭力

。

註：本項研發成果若尚未申請專利，請勿揭露可申請專利之主要內容。

98 年度專題研究計畫研究成果彙整表

計畫主持人：范慶麟 計畫編號：98-2221-E-011-141- 計畫名稱：高性能長壽命可撓式有機薄膜電晶體元件之製作與研究(III)

量化

成果項目 ^{實際已達成}

數（被接受 或已發表）

預期總達成 數(含實際已

達成數)

本計畫實 際貢獻百

分比

單位

備 註 （ 質 化 說 明：如 數 個 計 畫 共 同 成 果、成 果 列 為 該 期 刊 之 封 面 故 事 ...

等）

期刊論文 0 0 100%

研究報告/技術報告 4 4 100%

研討會論文 1 1 100%

論文著作 篇

專書 0 0 100%

申請中件數 3 3 100%

專利 已獲得件數 0 0 100% 件

件數 0 1 100% 件

技術移轉

權利金 0 0 100% 千元

碩士生 2 2 100%

博士生 2 2 100%

博士後研究員 0 0 100%

國內

參與計畫人力

（本國籍）

專任助理 0 0 100%

人次

期刊論文 7 10 100%

研究報告/技術報告 0 0 100%

研討會論文 3 3 100%

論文著作 篇

專書 0 0 100% 章/本

申請中件數 2 2 100%

專利 已獲得件數 0 0 100% 件

件數 0 0 100% 件

技術移轉

權利金 0 0 100% 千元

碩士生 0 0 100%

博士生 0 0 100%

博士後研究員 0 0 100%

國外

參與計畫人力

（外國籍）

專任助理 0 0 100%

人次

其他成果

(

無法以量化表達之成 果如辦理學術活動、獲 得獎項、重要國際合 作、研究成果國際影響 力及其他協助產業技 術發展之具體效益事 項等，請以文字敘述填 列。)

無

成果項目 量化 名稱或內容性質簡述

測驗工具(含質性與量性) 0

課程/模組 0

電腦及網路系統或工具 0

教材 0

舉辦之活動/競賽 0

研討會/工作坊 0

電子報、網站 0

科 教 處 計 畫 加 填 項

目 計畫成果推廣之參與（閱聽）人數 0

國科會補助專題研究計畫成果報告自評表

請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用價 值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性） 、是否適 合在學術期刊發表或申請專利、主要發現或其他有關價值等，作一綜合評估。

1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估

■達成目標

□未達成目標（請說明，以 100 字為限）

□實驗失敗

□因故實驗中斷

□其他原因 說明：

2. 研究成果在學術期刊發表或申請專利等情形：

論文：■已發表 □未發表之文稿 □撰寫中 □無 專利：□已獲得 ■申請中 □無

技轉：□已技轉 ■洽談中 □無 其他：（以 100 字為限）

3. 請依學術成就、技術創新、社會影響等方面，評估研究成果之學術或應用價 值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）（以 500 字為限）

本計劃利用自行組裝之高密度電漿化學氣相沉積系統製作出低於 100 ℃的二氧化矽 (SiO2)薄膜並運用在有機薄膜電晶體(OTFTs)之閘極絕緣層上，研究結果顯示有機薄膜電 機體搭配此低溫(< 100 ℃)二氧化矽閘極絕緣層可獲得良好的元件電特性，且其元件電特 性亦可比得上與有機薄膜電晶體搭配高溫沉積之二氧化矽閘極絕緣層。因此，本計畫所提 出之低於 100 ℃二氧化矽(SiO2)閘極絕緣層是非常適合有機薄膜電晶體的低溫製作並有 利於與有機發光二極體(OLED)的整合於塑膠基板來達成主動式驅動可撓面板(AMOLED)並 應用在新穎的電子產品上來提升國內軟性電子產業的競爭力。目前本計畫之研究成果已投 稿至國際期刊 Semiconductor Science and Technology 並已被刊登(Vol. 25, p. 075006, 2010.)。