Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs

Characterization and Modeling of Edge Direct

Tunneling (EDT) Leakage in Ultrathin Gate Oxide

MOSFETs

K. N. Yang, H. T. Huang, Student Member, IEEE, M. J. Chen, Senior Member, IEEE, Y. M. Lin, M. C. Yu, S. M. Jang,

Douglas C. H. Yu, and M. S. Liang

Abstract—This paper examines the edge direct tunneling

(EDT) of electron from n

polysilicon to underlying n-type drain

extension in off-state n-channel MOSFET’s having ultrathin gate

oxide thicknesses (1.4–2.4 nm). It is found that for thinner oxide

thicknesses, electron EDT is more pronounced over the

conven-tional gate-induced-drain-leakage (GIDL), bulk band-to-band

tunneling (BTBT), and gate-to-substrate tunneling, and as a

result, the induced gate and drain leakage is better measured per

unit gate width. A physical model is for the first time derived for

the oxide field

at the gate edge by accounting for electron

subband in the quantized accumulation polysilicon surface. This

model relates

to the gate-to-drain voltage, oxide thickness,

and doping concentration of drain extension. Once

is known,

an existing DT model readily reproduces EDT

–

consistently

and the tunneling path size extracted falls adequately within the

gate-to-drain overlap region. The ultimate oxide thickness limit

due to EDT is projected as well.

Index Terms—Author: Please e-mail [email protected] for

more info..

I. I

T

HE off-state drain leakage is one of the big issues for

aggressively shrunk MOSFET’s. The well recognized

mechanisms are the gate-induced-drain-leakage (GIDL) [1],

[2], the bulk band-to-band tunneling (BTBT) [3], and the

drain-induced-barrier-lowering (DIBL) enhanced subthreshold

conduction. In the case of reverse substrate bias for suppression

of DIBL or subthreshold leakage, the bulk BTBT dominates

[4]. On the other hand, the gate leakage due to direct tunneling

(DT) [5] was measured per unit oxide area and a certain

criterion of 1 A/cm set the ultimate limit of scalable oxide

thicknesses [6], [7]. Recently, Yang et al. [8] have originally

explored a dominant off-state leakage component via edge

direct tunneling (EDT) of electron from n

polysilicon to

underlying n-type drain extension. Also carried out in [8] is

the -

modeling obtained by following the procedure in [9],

[10]. However, some parameters of great relevance were not

clarified yet, such as the tunneling path area and the dopant

Manuscript received August 21, 2000; revised November 2, 2000. This work was supported by the National Science Council under Contract 89-2215-E-009-049. The review of this paper was arranged by Editor C.-Y. Lu. K. N. Yang, H. T. Huang, and M. J. Chen are with the Reliability Physics Lab-oratory and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.

Y. M. Lin, M. C. Yu, S. M. Jang, D. C. H. Yu, and M. S. Liang are with the Research and Development Department, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(01)03245-2.

(a)

(b)

(c)

Fig. 1. (a) HRTEM images of three nMOSFET gate stacks.T values extracted from the canvases correspond to 2.16, 1.88, and 1.49 nm, respectively. (b) The oxide thickness extraction using C-V method was based on van Dort’s model [13] and successive researchers [14], [15]. Best fitting produces

T of 2.3, 2.05, and 1.5 nm, respectively. (c)I–V fitting to find T .T values extracted by electron DT model [9], including quantization effect in accumulation layer underV < V are 2.40, 2.15, and 1.47 nm, respectively.

concentration of drain extension. In particular, the oxide field

is an essential input parameter to the DT

-

model in [9],

Fig. 2. ComparingT extracted from several techniques.

[10], and is usually gained by means of the so-called

-integration technique [11]. However, unlike the whole area

counterpart, it is impossible to assess such oxide field at the

gate edge for the situation that the overlap capacitance is too

small to detect using present

-

equipment.

In this paper, we report that as scaled gate oxide thickness

ap-proaches the DT regime, the EDT of electron from n

polysil-icon to underlying n-type drain not only dominates the gate

leakage, but also can prevail over the conventional GIDL, in

agreement with [8]. This phenomenon is more pronounced for

thinner oxide thicknesses, and EDT can even compete over the

bulk BTBT in the case of reverse substrate bias not mentioned in

[8]. It is clarified that the gate leakage in stand-by mode indeed

originates from the edge part rather than the whole gate oxide,

and thus should be measured per unit gate width rather than per

unit oxide area as in [6], [7]. Also presented is a physical model

for the first time derived for the oxide field

at the gate edge

by accounting for electron subband in the quantized

accumula-tion polysilicon surface. This model is valuable in enabling

con-sistently the reproduction of EDT – , the extraction of EDT

path size and dopant concentration of drain extension, and even

the projection of ultimate oxide thickness.

II. E

C

The n poly-gate nMOSFET’s were fabricated by a 0.18-um

process technology [12]. The gate oxides were grown in dilute

wet oxygen ambient to three different thicknesses. The gate

di-mension was drawn to

m . Accurate

determina-tion of ultrathin oxide thickness

is strongly demanded.

Three techniques in terms of high resolution TEM (HRTEM),

polysilicon depletion and quantum mechanics (QM) corrected

–

[13]–[15], and DT

–

[9] were adopted as shown in

Fig. 1, through which consistent results were achieved as

com-pared in Fig. 2. Fig. 1(a) just shows highly-localized HRTEM

cross section while the variation across the wafer is depicted in

Fig. 2 in terms of a bar. Our

–

data in Fig. 1(b) was

mea-sured in parallel mode with 1-MHz AC frequency. QM

cor-rected

–

fitting based on van Dort’s model for surface

quan-tization [13], [14] was carried out to extract physical

. In

particular, the singular point problem encountered around the

flat-band voltage

was eliminated by adopting a modified

version [15]. In Fig. 1(b),

–

fitting for

nm is

limited to nondistorted range,

V

V, where the

tunneling current effect or others can be neglected.

–

fitting

(a)

(b)

(c)

Fig. 3. (a) Band diagram located at channel region far from drain extension. Accumulation hole DT (I ) and accumulation electron DT current

(I ) both contribute to gate-to-substrate tunneling current. (b) Schematic

cross section near gate/drain overlap region underV < 0 V and V = 0V . Different tunneling paths are shown. (c) Band diagram located at gate/drain overlap region, showing EDT and GIDL under off-state condition.

in Fig. 1(b) also produced the n polysilicon dopant

concentra-tion

cm

and the effective channel dopant

concentration

cm

, all being found to be

consistent with the SIMS doping profile. In Fig. 1(c), the

de-vices were biased in poly accumulation (negative gate voltage,

) with source, drain, and p-well tied to ground, and

the oxide field strength

was obtained in advance by means

of the

–

integration technique [11]. With the effective mass

for Franz-type dispersion relationship in the

oxide, the conduction electron DT –

fitting in Fig. 1(c)

ex-tracted

and

nm from three samples.

Note that as all data go closer to the straight line with the unity

slope in Fig. 2, more confidence for DT –

extracted

, as

well as its subsequent applications in consistently calculating

the EDT current of electron from n

polysilicon to underlying

n-type drain, can all be ensured.

Fig. 3 illustrates the tunneling leakage paths and related

band diagrams. With source open and under

, the

(a)

(b)

(c)

Fig. 4. Displaying the measured terminal currents versus V for three differentT (a), (b), and (c) underV = 0V and source open. The aspect ratioW=L = 10 m/0:5 m. (a) EDT dominates the drain leakage in

1 V < V < 1:8 V. (b) The edge tunneling mechanism dominates I for 0 V < V < 2:2 V, and GIDL constitutes drain leakage for V > 2:2 V.

(c) The edge tunneling mechanism prevails over the drain leakage current. Note that gate-to-substrate tunneling is an important leakage source forI in

0:5 V < V < 2 V.

measured drain current

, gate current

, and bulk current

are plotted in Fig. 4 versus

for three different oxide

thicknesses. Fig. 4 reveals that the drain current primarily

comprises the GIDL, the bulk BTBT, and the gate current,

implying the EDT as the origin of the latter component. It can

be observed that the EDT dominates the gate leakage, and

there exists a certain range where the EDT prevails over the

conventional GIDL and bulk BTBT. This phenomenon is more

pronounced for thinner oxide thicknesses. In Fig. 4(c) for 1.47

nm thick oxide, the polarity of the bulk current is reversed due

to gate-to-substrate tunneling.

With source grounded and

V, the measured terminal

currents versus both polarities of

are plotted in Fig. 5 for

substrate bias

and

V. Obviously, for

nm

the bulk BTBT at

V dominates the drain leakage in

(a)

(b)

(c)

Fig. 5. Measured terminal current versus gate voltage. The aspect ratio

W=L = 10 m/ 0:5 m. With source grounded and V = 1 V, (a)–(c) shows

the measured terminal currents versus both polarities ofV for substrate bias

V = 0 and 01 V. (b) and (c) exhibits that off-state drain current does not

come from GIDL or bulk BTBT but EDT due to the evidence,I  I .

V

V, while such role is replaced by EDT

for thinner oxides. In Fig. 5(b) and (c),

for

V, which seems to be unchanged with and without substrate

bias, supporting the EDT mechanism responsible. This implies

that EDT is only dependent on the vertical electrical field but

not the lateral electrical field; that is, the edge tunneling can be

assumed as one-dimensional approximation. Besides, we found

experimentally that the EDT leakage is indeed proportional to

the gate width, regardless of the aspect ratio

. This means

that the gate leakage in stand-by mode (i.e., only source and

gate tied to ground) should be adequately measured per unit gate

width.

III. EDT M

An analytic electron DT model [9] was again employed in

this study. One essential physical parameter, namely, oxide field

at the gate edge, has to be estimated under each value of

. In our work, the mentioned

–

integration technique

failed to extract

because EDT occurs only within the area

of gate/drain overlap region and it is difficult to measure such

small capacitance in the overlap part. First of all, oxide field at

the gate edge can be obtained by solving the following equation:

(1)

where

is the potential drop in the polysilicon and

is

that in the drain extension region. The charge

available for

the tunnel process is modeled as field induced, i.e.,

(2)

Due to the lowest quantized energy, the accumulated electrons

mainly fill in the first subband. Thus, relating this sheet charge

density to the number of occupied subband states constructs the

charge conservation relationship

(3)

where

is the quasi-Fermi level in the n -polysilicon and

is the degeneracy factor. Using triangle-like electrostatic

po-tential approximation to the polysilicon surface, the quantized

energy of the first subband, can be calculated directly with

Som-merfeld-Wilson’s quantization rule

(4)

Applying the first subband approximation to the accumulated

n

poly gate and the deep depletion approximation to the

un-derlying drain extension region as shown in Fig. 6, we get

(5)

(6)

where

is the dopant concentration of drain extension. Here,

and

were used to

approximate the band-structure for

oriented n

-polysil-icon grains [9]. As a result, (1) can further be rearranged as

(7)

where

Thus, it is easy to get

by solving (7) numerically. With the

effective edge-tunneling area

, the EDT –

model reads [9]

(8)

Fig. 6. Band diagram drawn along gate/SiO /drain extension. The accumulation potential bending,V , with two-dimensional electron gas (2-DEG) concept and the silicon surface potential bending,V , with the deep depletion approximation are adopted in the procedure ofE extraction.

Fig. 7. Comparison of the EDT calculation and experiment. The extracted effective EDT range is 6.25 nm wide from the gate edge, equal for three different oxide thickness.W = 10 m.

where

sheet charge of the accumulation layer;

electron impact frequency on the n -poly/SiO

inter-face;

is the modified transmission probability considering

in-terface reflection factor [9].

Once

was quantified, an excellent reproduction for

different oxide thicknesses was achieved with

/cm and effective mass

resulting from

Franz-type dispersion relation in tunnel oxide, as depicted

in Fig. 7. The tunneling path extracted was 6.25 nm wide

from the gate edge (due to

extracted). This is

quite reasonable since the drain extension beneath the gate is

less than 0.01

m. Therefore, the consistent modeling work

validates the EDT as the origin of the leakage of concern.

It is recognized that the drain extension may be considered a

nonscalable factor [16], implying a constant

of 6.25 nm in

the scaling direction. With this in mind, the conventional

crite-rion of 1 A/cm can be transferred to 0.625

A/cm. Using the

roadmap parameters [17], the electron EDT current is calculated

versus scaling generation oxide thickness as shown in Fig. 8. In

this figure, the new criterion due to electron EDT sets the

ulti-mate oxide thickness of around 1.4 nm.

(a)

(b)

Fig. 8. (a) The calculated electron DT current per gate width versus scaling generation oxide thickness in NMOSFET’s. The inset shows the scaling parameters from [17]. (b) Exhibiting the EDT path in the structure of NMOSFET.L = 6:25 nm.

IV. C

The EDT of electrons from n

polysilicon to underlying

n-type drain extension has shown its tremendous impact on the

drain leakage and gate leakage. This effect is more pronounced

for thinner oxide thicknesses. It is clarified that the gate leakage

in practical stand-by mode should be measured per unit gate

width, particularly for MOSFETs with oxide thickness less than

2.40 nm. Eventually, a physical model cited in the literature

does reproduce consistently experimental EDT –

character-istics and its tunneling area extracted indeed falls within the

gate-to-drain overlap region. The ultimate oxide thickness due

to electron EDT has also been projected based on the model.

A

The authors wish to thank T. K. Kang for many stimulating

and helpful discussions.

R

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K. N. Yang was born in Yuen-Lien, Taiwan, R.O.C.

He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University (NCTU), Taiwan, in 1998 and 1999, respectively. He is currently pursuing the Ph.D. degree in electronics engineering with the research group of Prof. M.-J. Chen at the Department of Electronics, NCTU.

His interests include modeling and reliability physics of MOSFETs structure.

H. T. Huang (S’98) received the B.E. degree in

electrical engineering from the National Cheng-King University, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electronics engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 1988, 1990, and 2000, respectively.

From 1990 to 1992, he served in the Chinese army as a Tactical Control Officer. Since 1992, he has been with Ta-Hua Institute of Technology, Chung-li, Taiwan. His research interests are curently the reliability issues such as TDDB, soft breakdown, trap-assisted tunneling leakage, etc., in deep submicron CMOS.

M. J. Chen (S’78–M’85–SM’98) received the

B.S. degree in electrical engineering with highest honors from National Cheng-Kung University, Taiwan, R.O.C. , in 1977, and the Ph.D. in electrical engineering from National Chiao-Tung University, (NCTU) Hsinchu, Taiwan, in 1985. Since 1985, he has been with the department of Electronics Engineering, NCTU, where he is Professor. From 1987 to 1992, he was a Principal Consultant sy TSMC, where he led a team to build process window and design rule. In 1996 and 1997, he enabled the ERSO/ITRI vidoe A/D converters and the TSMC mixed-mode CMOS processes, respectively. His current areas are nanoscale reliability physics and next-generations electronics. He has graduated six Ph.D. students and had been granted four U.S. patents and six Taiwan patents.

Professor Chen is a Co-Winner of the 1992 and 1993 Chinese Young En-gineer Paper Award, and a Co-Winner of the 1996 Acer Distinguished Ph.D. Dissertation Award. He is a member of Phi Tau Phi.

Y. M. Lin was born in Taipei, Taiwan, R.O.C.,

in 1968. He received the B.S. degree in electrical engineering from the Tatung Institute of Technology in 1991, the M.S. degree in electrical engineering from the National Hsin-Hua University in 1993, and Ph.D. degree in electronic engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 1997. His Ph.D. dissertation focused on process issues of interpoly-silicon dielectric and intermetal dielectric and their impacts on device reliability.

From 1994 to 1995, he worked on intermetal di-electric development for 0.35–m CMOS at Taiwan Semiconductor Manufac-turing Company (TSMC), Hinchu. Since September 1999, he is responsible for gate quality silicon and high-k gate dielectric for 0.1–m CMOS at TSMC. He is now with Sematech for process development and reliability of gate quality silicon.

M. C. Yu was born in Hsinchu, Taiwan, R.O.C.,

in 1968. He received the B.S. degree in electrical engineering from National Tsing-Hua University, Hsinchu, in 1991, and the M.S. degree in electrical engineering from Tohoku University, Sendai, Japan in 1997, under the sponsorship of the Ministry of Education of Taiwan.

In 1997, he joined Taiwan Semiconductor Manu-facturing Copmany Ltd., Hsinchu, where he has been engaging in research and development for the ultra-thin gate dielectric process and characterization.

S. M. Jang received the B.S. and M.S. degrees

from the National Tsing-Hua University, Hsinchu, Taiwan, R.O.C., in 1985 and 1987, and the Ph.D. de-gree form the Massachusetts Institute of Technology (MIT), Cambridge, in 1993, all in materials science and engineering.His dissertation work included SiGe CVD technology, kinetics, and thermal stability for HBT application. Sponsored by IBM and SRC, his research was conducted in the Microsystems Technology Laboratories, MIT under the guidance of Prof. R. Reif in electrical engineering.

He joined Taiwan Semiconductor Manufacturing Company LTD., Hsinchu, Taiwan, in 1993. He has sucessfully developed ozone-TEOS, spin-on coating, HDPCVD dielectrics, PECVD SiON antireflection layer, and CMP processes for 0.5–0.18 m COMS technologies. He is now the Mamager of Dielectric/CMP/Diffusion Projects in the Advanced Module Technology Division, R&D, responsible for the modules of shallow trench isolation, gate stack, ultrashallow junction, interpoly-metal dielectric, low-dielectric-constant intermetal dielecrtic, and oxide, tungsten, and copper CMP for 0.13 m generation and beyond. He has authored oe co-authored more than 40 technical papers and has received 48 U.S. patents and 50 Taiwanese patents.

Dr. Jang is a member of Phi Tau Phi.

Douglas C. H. Yu received the Ph.D. degree from the

Material Engineering Department, Georgia Institute of Technology, Atlanta.

He was with AT&T Bell Laboratories, Allentown, PA. The projects he invloved include PECVD thin film processing, 256 k/1 Mb SRAM process integration and yield improvement, 0.35/0.25 µm ultrahigh performance logic device development, modular BiCMOS and MiM process integration. He later joined Taiwan Semiconductor Manufacturing Company, Ltd., Hinchu, Taiwan, R.O.C., where he lead a module team to successfully develop TSMC 0.5m, 0.35 m, and 0.18

m core logic technologies. He performed yield improvement and transferred

the process to manufacturing. He also managed an advanced technology team to develop and qualify TSMC 1st Cu technology for 0.18m technology. Currently he manages a module team to develop TSMC Cu/low-k interconnect, gate stack, salicide, and shallow-trench-isolation, etc. He has been awarded 91 U.S. patents with another 90 patent applications pending. Also, he has numerous publications in technical journals and conferences, all in VLSI processing/device/integration area.