[PDF] Top 20 Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
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Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
... designed for the previous stan- dards, where VBS and MRF are not supported, the parameter of our design is set as the single-iteration 4SS with one reference ...processes and supply ... See full document
10
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
... Analysis, Fast Algorithm, and VLSI Architecture Design for ...Chen, and Liang-Gee Chen, Fellow, IEEE Abstract—Intra prediction with rate-distortion constrained mode ... See full document
24
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
... instead of SATD to estimate the bit-rate influenced by ...removed and about 40% hardware cost can be ...size and controlled by FSM as shown in ...save power consumption and processing ... See full document
13
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications
... Furthermore, if the PERFORMANCE OF CANDIDATE LEVEL DR FOR THE PROPOSED PARALLEL power is very low, we can even support only half-pel or integer- ARCHITECTURE.. pel resolution with one re[r] ... See full document
4
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
... 2. Architecture mapping: Parallel 2-D adder tree architecture [18] is adopted as the basic architec- ture in our design and shown in ...SRAMs for inter-MB DR. Reference pixels are read ... See full document
17
A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
... Terms—H.264/AVC, motion estimation, video ...flexible and powerful with the development of semiconduc- tors, digital signal processing, and communication ... See full document
6
Analysis and architecture design of variable block-size motion estimation for H.264/AVC
... line for FBSME, and the other is the dotted line for ...tics of each hardware and see that the similar architectures has similar hexagonal plots and ...vides low hardware ... See full document
16
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC
... VLSI architecture for frac- tional motion estimation of ...analyzed and two decom- posing techniques are proposed to parallelize the algorithm for hardware with ... See full document
4
Global elimination algorithm and architecture design for fast block matching motion estimation
... GEA and its architecture design for fast block matching ...Our algorithm can solve several problems en- countered by ...block, and then to precisely compare the best ... See full document
10
Parallel global elimination algorithm and architecture design for fast block matching motion estimation
... elimination algorithm and architecture for fast block ...distortion estimation, only a few most probable candidates are required to determine the final motion vector with ... See full document
4
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
... window for MB pipeline scheme severe quality degradation especially for sequence which needs many intra MB’s, like an action movie in which motion estimation often fails to find a good ...from ... See full document
4
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
... Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, and Tian-Sheuan Chang, Senior Member, IEEE ... See full document
10
Hardware architecture design of an H.264/AVC video codec
... complexity and memory access requirement make the hardwired codec solution a tough ...methodology for H.264/AVC video codec. The system architecture and scheduling will be ... See full document
8
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
... constant and sufficient memory bandwidth, regardless of the limited and dynamic bandwidth resources available for power-limited mobile ...that, for D1 (704 576) picture sizes, ME ... See full document
10
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
... or low-power applications, the cycle time available to decode an MB is very ...engine for CAVLD appears as the throughput bottleneck of the ...engine for CAVLD to overcome this ... See full document
4
Low-power parallel tree architecture for full search block-matching motion estimation
... Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan E-Mail: {sslin, pctseng, ...novel low-power parallel tree architecture is pro- posed for full search ... See full document
4
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC
... Proposed architecture with SRMC scheme. Fig. 8. Schedule of SRMC scheme in the proposed ...B. Architecture Design Fig. 7 shows the architecture of ...values, and the PMD ... See full document
6
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
... price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real- time ...sequential, and highly ... See full document
16
Design of anMC Interpolation Architecture for H.264 Video Decoder
... a motion compensated hybrid Discrete Cosine Transform ...requirements of high quality and low bit rate, it adopts many advance and precision coding ...process of ... See full document
8
Content-Aware Fast Motion Estimation Algorithm
... category algorithm which can reduce the number of search points but it needs thresholds and is not suitable for sudden motion ...drawbacks of previous works, we propose the ... See full document
6
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