[PDF] Top 20 Substrate-triggered ESD protection circuit without extra process modification
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Substrate-triggered ESD protection circuit without extra process modification
... a Circuit Design Engi- ...of ESD protection and latch-up in CMOS integrated cir- cuits, he has published over 120 technical papers in international journals and ...in ESD protection ... See full document
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ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... or without the proposed substrate-triggered ...not triggered by such a voltage ...the substrate-triggered design, the voltage wave- form on the pad is observed and shown in ...be ... See full document
10
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... the circuit analysis and experimental results, the substrate-triggered technique has been confirmed to contin- ually improve ESD robustness of ESD protection devices ... See full document
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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... on-chip ESD protection cir- cuits has been successfully investigated in a ...CMOS process. By using the substrate-triggered technique, the STSCR device has the advantages of ... See full document
9
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... (ESD), ESD protection circuit, mixed-voltage I/O circuits, substrate-triggered ...IMPROVE circuit operating speed and performance, the device dimensions of MOSFET had been ... See full document
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Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
... on-chip ESD protection design is proposed to solve the non-uni- form turn-on phenomenon of multi-finger gate-grounded nMOS ...under ESD stress, so its source terminal is connected to the base ... See full document
9
ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
... CMOS process. ESD clamp circuits, the sizes of ESD-protection devices at the RF input node can be further reduced without sacrificing ESD ...the ESD-protection ... See full document
11
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... RF ESD protection for 60-GHz fre- ...under ESD stress ...of ESD protec- tion device under normal RF circuit operating conditions [18], ...high ESD robustness, and low RF ... See full document
10
Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
... CMOS process. By using the substrate-triggered technique, the DTDB, STDB, and STLB devices can provide much higher ESD ro- bustness within a smaller layout area, as compared to the traditional ... See full document
14
Initial-on ESD protection design with PMOS-triggered SCR device
... on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be ... See full document
4
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
... CDM ESD current in path 2. The NMOS transistor (Mn3) can be turned on by ESD current dis- charging through the ESD clamp between VSSIO and VSS lines to generate a gate-to-source voltage (Vgs) of NMOS ... See full document
4
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
... on-chip ESD protection circuits are ...accidentally triggered by noise pulses when the ICs are operated in the application ...whole-chip ESD protection in CMOS ICs without ... See full document
21
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... new ESD protection scheme with an ESD_BUS and a high- voltage-tolerant ESD clamp circuit for a SoC with ...CMOS process. The ESD stresses on the mixed-voltage I/O pad and ... See full document
8
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... The substrate driver in the ESD detection circuit is guaran- teed to be kept in off state under the normal circuit operating ...the ESD detection circuit rather than the ... See full document
10
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... on-chip ESD protection cir- cuits has been successfully investigated in a ...CMOS process. With both the substrate and n-well triggered currents, the switching voltage and turn-on time ... See full document
11
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
... II. S TACKED -NMOS T RIGGERED S ILICON -C ONTROLLED R ECTIFIER The cross-sectional view and layout of the stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) device are shown in Fig. 1(a) and (b), ... See full document
3
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... a Circuit Design ...in ESD protec- tion design and latchup prevention have been widely used in modern IC prod- ...in ESD protection design and latchup prevention by more than 150 IC design ... See full document
13
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
... new ESD protection circuit with low parasitic capaci- tance, large swing tolerance, high ESD robustness, and good latchup immunity has been developed for the gigahertz power ...test ... See full document
8
New transient detection circuit for system-level ESD protection
... detection circuit for system-level electrostatic discharge (ESD) protection is ...detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be ... See full document
4
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
... and ESD robustness of the MOS-triggered SCR devices are increased by increasing the channel lengths, particularly in the PMOS-triggered SCR ...and ESD robustness of the MOS-triggered ... See full document
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