This work demonstrates a 10GHz all digital frequency synthesizer for the high speed serial data communication systems. With the dual mode phase detector, the loop rapidly locks to the target frequency and then reconstructs to a bang-bang PLL without resorting to the time to digital converter.
Governed by the proposed locking process monitor, the digital loop filter is automatically reconfigured and the loop bandwidth is self-adjusted during the frequency acquisition and phase tracking process. Less than 7µsec locking time and 0.9ps rms jitter including the trigger jitter of the oscilloscope have been measured.
A novel skew-compensated asynchronous phase accumulator is proposed, which preserves the advantage of low power dissipation of asynchronous counter while eliminating the accumulated timing skew issue.
A LC-DCO with a varactor bank incorporating 8-bits binary-weighted coarse tuning and 10-bits unity-weighted fine tuning to ensure linearity is presented. The frequency resolution is further enhanced by employing high speed dithering though an 8-bit MASH-11 ∆Σ modulator.
Using the UMC 90nm CMOS technology, the implemented prototype occupies only 0.352mm2 active area and manifests with power efficient of 0.71mW/GHz which is comparable with the state of the art frequency synthesizers.
Finally, because of the digital nature, the ADPLL can be further scaled down for future CMOS process and suitable in SOC designs.
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Reference
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Leipold, "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones," IEEE Journal of Solid-State Circuits, vol. 40, pp. 2203-2211, 2005.
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Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,"
ISSCC Dig. Tech. Papers, pp. 340-617, Feb. 2008.
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Vita
基本資料
中文姓名 楊松諭 英文姓名 Song-Yu Yang
聯絡電話 0911304667 電子信箱 xyz1029@msn.com 通訊地址 新竹市大學路 81 巷 27 號
戶籍地址 嘉義市宣信街 48 巷 67 號
宗教 基督教
教育背景
學歷 學校 系所 組別 時間
碩士 國立交通大學 電子所 系統組 94.9~97.11 畢
大學 國立交通大學 電子工程學系 90.9~94.6 畢
高中 嘉義市私立興華中學 87.9~90.6 畢
專長 類比積體電路(一)(二)
數位積體電路
有線傳輸通信積體電路設計 適應性訊號處理
數位通訊 修習科目
類比電路設計 Full-Custom Design Flow 專業能力
鎖相迴路設計 Cell-Based Design Flow
MATLAB/Simulink Verilog
HSPICE Design Vision
Spectre RF SOC Encounter
Virtuoso Office: Word, Excel, Power Point
熟悉軟體
Calibre
CIC 下線審查評鑑:B 斐陶斐榮譽會員 大三書券獎兩學期 大二書券獎兩學期 特殊表現