Locking Transient of the ADPLL during Phase Tracking Mode 22

After the initial frequency is locked roughly using the frequency acquisition mode, the fine tuning varactor bank of the DCO and the integral path of the loop filter are activated. Then the bang-bang phase tracking (PT) mode is entered and the system block diagram during this mode is illustrated in Fig. 3-5.

As already mentioned in Chapter 2, the architecture can be further simplified as a digital bang-bang PLL (BBPLL) where a binary phase detector (BPD) and a divided-by-N frequency divider are used instead of the binary

23

quantizer, the accumulators and the subtracter as shown in Fig. 3-6. The binary phase detector output Φ_EBB is set to -1 when the rising edge of the feedback clock leads the reference clock edge. Otherwise, ΦEBB is set to 1 to indicate that the feedback clock lags the reference clock. The variables D and Ψ_I introduced in Fig. 3-6 denotes the loop delay time normalized to one reference clock period 1/f_REF and the integral path output of the loop filter, respectively. In our design, the value of D is 0.5 which is introduced by the re-synchronizing operation before the digital loop filter output feds to the DCO.

The classical treatment of linear PLLs is done in the frequency domain by using of the Laplace transform or the Z-transform. Due to the presence of the

Fig. 3-5 System block diagram during bang-bang phase tracking mode.

Fig. 3-6 Equivalent system block diagram during bang-bang phase tracking mode.

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nonlinear binary phase detector block in the loop, this approach cannot be used for the ADPLL during PT mode. The fundamental aspect of BBPLL is the presence of limit cycles in the loop dynamics. In fact, a BBPLL cannot lock to the reference clock in a traditional sense, where the output of the phase detector and the loop filter voltages settle asymptotically around a fixed value, disturbed only by thermal noise.

In order to achieve more insight into the BBPLL characteristics before the analytic equations of the loop property are given, some results of the behavior

0 0.5 1 1.5 2

x 10^-5 9.8

9.85 9.9 9.95 10

x 10⁹

Time (sec)

Frequency (Hz)

(a)

0 0.5 1 1.5 2

x 10^-5 -2

-1 0 1 2

Time (sec)

Phase Error φφφφ (rad)

(b)

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simulations are shown. Fig. 3-7 shows the simulation results of the locking behavior and the phase plane of a BBPLL with D=0.5, where the phase error φ is the un-quantized phase difference between the reference clock and feedback signal.

It is clear from Fig. 3-7(a) that the BBPLL output frequency oscillates around a fixed value in locked state. The simulated phase plane is shown in Fig.

3-7(c), where the x-axis is the phase error and the y-axis is the integral path output ΨI of the loop filter. Since the loop dynamic tends to produce a phase detector output with duty cycle proportional to the loop frequency error when β is much lager the α, the integral path can be viewed as an inner frequency tracking loop [6]. Thus the dynamics of the integral path output ΨI can be treated as the behavior of the tracking frequency. When the stability conditions are met, the trajectory converges toward center and then enters a periodic orbit. In order to investigate the loop dynamics of the BBPLL, the time domain based approach proposed in [7] is used. Since only the loop dynamics in the presence of the hard

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

0 20 40 60 80 100 120 140

Phase Error _φφφφ (rad) Integral Path Output ψψψψ I

(c)

Fig. 3-7 (a) Simulated output frequency, (b) phase error versus time and (c) the phase plane of the BBPLL.

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nonlinearity is interested in this approach, it is assumed that all the PLL building blocks are free from any kind of physical noise source.

By indicating with tr and td the time instants of the rising edges of the reference and divided clocks, respectively, the logical output of the BPD can be express as:

( )^t

EBB = ∆

Φ sgn , (3-3)

where ∆t=tr-td. The DCO can be modeled as a linear block with output clock period TOUT depending linearly on the input control code CDCO:

DCO T free DCO

OUT T K C

T = _, − , (3-4)

where TDCO,free is the DCO free running period and KT is the period gain of the DCO which can be expressed in term of the frequency gain KDCO of the DCO KT=-KDCO(TDCO,free)².

Fig. 3-8 reveals the time diagram of the BBPLL. By inspecting Fig. 3-6 and Fig. 3-8, the behavior of the BBPLL can be described by the following nonlinear

Fig. 3-8 Time diagrams of the signals in the BBPLL (Adapted from [7]).

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With the definition of the following quantities:

β

equation 3-5 can be rewritten in the following simplified form:

[ ] [ ]

[ ]

In equation 3-6, some words are defined. The symbol τ denotes the timing error normalized to the quantization step NβKT of the loop, and x0 is the normalized difference between the period of the reference clock and the DCO free running period multiplied by N. The value of x0 is zero only if the two periods are identical which can never be met in a practical BBPLL implementation. However, the assumption x0=0 can be used as a starting point in order to simplify the analysis. It can be proved that a system with x0≠0 is

From this equation, the characteristics of the system can be described using only two state variables, namely τ and ΨI.

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3.2.2 Stability Conditions of the ADPLL during PT Mode

Next the conditions for stability will be given for ADPLL during PT mode.

Due to the presence of the nonlinear BPD, the conditions for stability of a BBPLL can not be derived directly form frequency domain analysis. Instead, the conditions for the BBPLL stability can be described by the existence of the orbit in the phase plane and can be expressed as [7]

R D

1 2

2

< + , (3-9)

which is independent of the multiplied ratio N and DCO frequency gain KDCO. From this equation for a given α, the minimum β is limited to (2D+1)α/2. Thus reducing β or increasing the loop latency would drive the BBPLL toward the instability limit. The conditions and characteristic mentioned above could be confirmed by the simulation results as shown in Fig. 3-9, where the simulations are performed with different combinations of loop parameters.

With constant loop delay, larger β tends to improve loop stability and locking speed. With the same loop filter parameters the longer the loop latency, the longer time the loop expends to achieve locked state. Further increasing of the delay will make the loop to diverge. It is worth noting that the BBPLL produces longer duration of the limit cycles with larger D which results in wider frequency variation in steady state.