Motivation

Chapter 1 Introduction

1.1 Motivation

1.1.1 Introduction of Frequency Synthesizers

Frequency synthesizers are the key building blocks for most of the modern electronic and communication systems, including radio receivers, mobile telephones, and satellite receivers. The basic goal of a frequency synthesizer is to generate a periodic signal with a given frequency and phase relationship with respect to a reference signal. The generated clock signal can be served as clock source for processors, transmit clock in high speed data interfaces, sampling clock for analog to digital convertor, and local oscillator signal for wireless transceiver which mixes the signal of interest to a different frequency. Many approaches of frequency synthesizers have been devised over the years, such as phase-locked loops (PLLs), direct digital synthesis (DDS), and frequency mixing. Among different approaches of frequency synthesizer, most state of the art high-performance frequency synthesizers are based on the phase-locked loops technique.

A phase-locked loop is a frequency control system with negative feedback.

By sensing the phase difference between the feedback path of a controlled oscillator and the input reference signal, a PLL generates a signal with the phase that has a fixed relation to the phase of a reference signal. It responds to both the frequency and the phase of the reference signal and automatically raises or lowers the frequency of a controlled oscillator until output signal is matched to the reference in both frequency and phase. A PLL can be used to generate a

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signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.

The basic structure of a phase-locked loop is illustrated in Fig. 1-1 [1], which consists of a controlled oscillator, a phase frequency detector, a loop filter, and a feedback frequency divider. In this architecture a controlled oscillator generates a periodic signal with a frequency fOUT determined by the value of controlled oscillator input. The output clock is divided by a feedback frequency divider having a frequency fFB=fOUT/N, where N is the divided ratio of the frequency divider. A phase frequency detector compares the phase or frequency difference between the feedback clock and a reference clock, having a frequency fREF. The output signal of phase frequency detector which carries the frequency or phase error information is then processed by a loop filter. The abrupt changes in the error information generated by phase frequency detector are then smoothed out by loop filter. Finally, the output of the loop filter feeds to the controlled oscillator and adjusts the frequency fOUT of the output clock. The loop reaches a steady state condition where fOUT=fREFN, and the given relationship between the output clock and reference clock is established if the loop is properly designed.

Fig. 1-1 Block diagram of a phase-locked loop

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The design of the CMOS integrated PLL based RF synthesizers remains one of the most challenging tasks in communication systems because they must meet the strict requirements of low-cost, low-power, monotonic implementation while also meeting the noise and transient specifications. In general, a frequency synthesizer design can be evaluated by the following considerations: Phase noise or jitter performance, spurious noise performance, frequency hopping speed, tuning bandwidth, rejection of supply or substrate noise, chip area, power consumption and portability for the design to transfer to a different technology node. However, there exist complicated design trade-offs among these criteria mentioned above. Therefore the requirements that a synthesizer must fulfill depend heavily on the specific application.

The conventional PLL based RF synthesizer is usually made as an analog building block. As the feature size of the CMOS technology becomes smaller, the low-voltage deep-submicrometer digital CMOS process allows more and more digital circuits to be integrated in a single ship with higher operation frequency while consuming less power due to smaller parasitic capacitance and lower supply voltage. The analog circuits, however, does not benefit much from the scaling of the CMOS devices. Indeed, the small voltage headroom, high leakage current and the noisy environment on a SOC make the design of high-performance synthesizers more and more difficult. Thus, many research efforts recently focus on the digitally intensive or digitally assisted approach of the RF synthesizer [2]-[4]. Next, a description of the target application and its requirements on the synthesizer will be given.

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1.1.2 Target Application and its Requirements

The rapidly growing volume of data transfer in telecommunication networks has motivated the widespread usage of the optical communication, which permits transmission over longer distances and at higher data rates than other forms of communication channels. Fig. 1-2 shows the block diagram of a generic optical communication system [5].

At the transmit side, the input parallel data is first converted to serial data by the serializer. Since the output of the serializer may suffer from nonidealities such as jitter and inter-symbol interference (ISI). The serial data is resampled by a flip-flop triggered by the clock multiplication unit (CMU) before the signal is sent to the laser driver. The output of retimer is then amplified to drive the laser diode. Finally, the optical signal is generated by the laser diode and guided by the optical fiber.

At the end of the fiber, a photodiode senses the light and produces electrical

Fig. 1-2 Block diagram of optical transmitter and receiver.

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current signal to the transimpedance amplifier (TIA). A high gain limiting amplifier (LA) follows the TIA and generates output signal with large voltage swing to provide logical levels. In order to perform synchronous operations such as retiming and deserializing on the random data, the receiver side must generate a clock. The task of generating such a clock from input data and retiming the data are performed by the clock and data recovery circuit (CDR). Finally, the original parallel data is reproduced by the deserializer.

The clock multiplication unit has been selected as our target in this thesis.

In the synchronous optical network (SONET) standard, the data rate of the bitstream carried by the digital signal is defined by the optical carrier (OC) level.

For example, the SONET OC-192 is a network line with transmission speeds of up to 9953.28 Mbit/s. Another major design consideration is the output jitter performance. The SONET specifications impose output peak-to-peak and rms jitter at the transmitter optical interface below 0.1UI and 0.01UI when integrated between 50 kHz and 80 MHz. These correspond to 10ps and 1ps for an OC-192 carrier. The goal of this work is to design a frequency synthesizer which generates a low jitter 10 GHz clock satisfying the SONET OC-192 specifications.