Generated Timing Jitter and Phase Noise

In general, the major noise sources of PLL are the external reference input noise and the internal oscillator natural noise. However, due to the presence of the bang-bang phase detector, the noise introduced by the quantization operation must be taken into consideration.

Fig. 3-20 Complete linearized model of the ADPLL during bang-bang phase tracking mode.

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In Fig. 3-21 the linearized model of the ADPLL is illustrated again including the internal and external noise sources. In particular φ_n,REF is the phase noise on the input reference clock, φn,BPD is the input referred noise due to the quantization of the binary phase detector, and φ_n,DCO is the phase noise on the DCO output produced by itself. It should be noted that only the deviation to their nominal value are considered for all the quantities in the analysis.

To find the total output noise of the ADPLL, the expression of the power spectral density (PSD) of each noise source is required. Since the signal generator is used for generating the reference clock in the practical implementation of the ADPLL, the phase noise PSD of the reference clock can be estimated as following expression according to the signal generator specifications [9]. The PSD of reference clock is estimate as:

( )∆f =^-132(dBc/Hz)

Sϕn,REF . (3-55)

In our analysis, the BPD is modeled as a linear block with a gain Kbpd,φ. In order to emulate the quantization effect of the BPD, a input refer jitter is introduced and defined as

( )ϕ ϕ ( )ϕ _ϕ

Fig. 3-21 Simplified linearized model of the ADPLL during bang-bang phase tracking mode with internal and external noise sources.

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To find the total output phase noise, an approximation of the PSD of φn,BPD is needed. In general, if the jitter of the reference clock is small compared to the BBPLL quantization step NΒKT, the BBPLL behaves like a first order ∆Σ modulator having a one bit quantizer with step 2NβKT. Thus, φn,BPD can be approximated as a white process with uniform distribution and variance (2NβKT)²/12. However, if the jitter of the reference clock increases, the ∆Σ loop will be overload and result in slewing [10]. Therefore the variance of φn,BPD will increase. To obtain the expression of its variance for larger input jitter, the approach proposed in [10] is resorted to simulation results. It shows that the jitter introduced by the BPD has a standard deviation which is roughly 3/4 of the standard deviation of the input jitter. From the above discussion, the PSD of the noise produce by the BPD can be defined as [10] simulation results, the analytic approximation may give more insight about the generation of phase noise in the circuit design phase. Consider the differential LC tank cross-coupled pair oscillator. The generated phase noise can be express as [11] value of the impulse sensitivity function (ISF) associated with that noise source, qmax is the maximum signal charge swing which is defined as the product of the

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tank capacitance and maximum signal swing CtankVswing, and ∆f is the the offset frequency from the carrier.

In a simplified stationary approach, the total noise power of the tank is mainly due to the cross-coupled transistor pair and the ohmic losses in the tank inductor: oscillation fosc, T is the temperature, k is Boltzmann constant, µn is the mobility of the carriers in the channel, Cox is the oxide capacitance per unit area, W and L are the width and length of the MOS transistor, respectively, and Vov is the gate drive of the MOS transistor. γ, however, may be between two and three in the short-channel devices. For simplicity, the output waveform can be assumed to be a sinusoidal waveform so that (Γrms)² equals to 0.5 [11]. HREF,OUT(∆f) and HDCO,OUT(∆f) denote the transfer function from reference signal to PLL output and from DCO output to PLL output which can be found by inspecting Fig. 3-21. Thus the transfer functions are

( )( )

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As an example, Fig. 3-22 shows the transfer functions and the output phase noise for the case with following loop parameters: fREF=40MHz, N=248, KDCOβ=19200, KDCOα=300, DCO free running frequency is 9.92 GHz. The DCO is assumed to have a LC oscillator with tank quality factor of 8, 1.2nH inductor, 0.8V output swing. To ensure oscillation, the cross-coupled pair transistors have their size of W=2µm and L=0.08µm. The result shows the loop bandwidth is about 150kHz. The result also reveals that the output phase noise at lower frequency is dominated by reference noise while it is affected by both DCO phase noise and reference noise at higher frequency.

In order to validate the expressions for the output phase noise obtained from the linearized theory, the results of the Simulink model are compared to the analytical expression. From Fig. 3-23 to Fig. 3-28 report the results of the simulations. It can be seen that the agreement between theory and simulation is good for most cases, excluding the one shown in Fig. 3-26. There is already a noticeable difference, meaning that in this case the dynamics of the BBPLL determines the output phase noise in a nonlinear way. By inspecting Fig. 3-23, Fig. 3-24 and Fig. 3-25, it can be noted that with constant KDCOα, larger KDCOβ can result in boarder loop bandwidth. However, increasing KDCOα and keeping KDCOβ unchanged will drive the loop toward the instability border and generate peaking on the output PSD. Therefore, in order to achieve better jitter performance, KDCOα should be minimized.

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10³ 10⁴ 10⁵ 10⁶ 10⁷

-140 -120 -100 -80 -60 -40

Frequency (Hz)

Phase Noise (dBc/Hz)

Simulation Linear Model

Fig. 3-23 Output phase noise with K_DCOα=3×10² and K_DCOβ=3.84×10⁴_.

10³ 10⁴ 10⁵ 10⁶ 10⁷

-130 -120 -110 -100 -90 -80

Frequency (Hz)

Output Phase Noise (dBc/Hz)

10³ 10⁴ 10⁵ 10⁶ 10⁷

-100 -50 0 50 100

Frequency (Hz)

Magnitude (dB)

Fig. 3-22 Example computation of ADPLL transfer functions and contribution of each noise source.

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53 optimum value of KDCOβ which minimizes the BBPLL output jitter for a given KDCOα. Fig. 3-29 reveals the simulation results of output rms jitter versus K_DCOβ and KDCOα. As expected, a smaller value of KDCOβ causes the BBPLL to be close to the instability limit, where the peaking, and also the jitter, increases dramatically. Bigger values of KDCOβ would stabilize the BBPLL on orbits with small radius. Nevertheless, increasing KDCOβ further will cause the jitter to grow, due to the border loop bandwidth and bigger quantization step in the proportional path of the BBPLL. Thus there exists an optimum value of KDCOβ, which minimizes the output jitter.

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KDCOαααα K DCOββββ

10¹ 10² 10³ 10⁴

10² 10⁴ 10⁶

Fig. 3-29 Output jitter versus K_DCOβ and K_DCOα.

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Chapter 4 Design and Implementation