The Linear Model of the ADPLL during PT Mode

An inspection of equation 3-32, 3-33 and 3-34 reveals that larger βKDCO and D will result in larger ∆ωpp and smaller ωm, thus increasing the power level of the spurs.

Their power level is at

dB

relative to the main carrier tone. In Fig. 3-16(b), the simulated output spectrum is shown and the expression above is confirmed. It should be noted that the analysis is performed under the noise-free assumption. Obviously, this is not a practical case. In fact, the noise will randomize the spurious energy.

3.3.2 The Linear Model of the ADPLL during PT Mode

Although the nonlinear model has been helpful to find the stability criterion and general properties of the trajectories, this approach can not successfully describe

41

the output noise performance under the more realistic assumptions of the presence of internal and external noise sources. A different approach will be demonstrated in the following sections. A continue-time linear model will build for the ADPLL during bang-bang phase tracking mode. Then the system transfer function will be derived to estimate the performance of the loop.

From the system architecture shown in Fig. 3-6, the difficulty to build the linear model for this system is the hard nonlinearity introduce by the binary phase detector. An approach for modeling the binary phase detector is reported in [8] where the phase detector is modeled as a linear block with a gain Kbpd as illustrated in Fig. 3-17. The symbol ∆t=tr-td is the difference between the rising edges instants of the reference (tr) and feedback clock (td). It is clear that in the locked state, the average value of the BPD output E[ΦEBB] converges to 0.

Assume that for some reason the probability distribution of ∆t is shifted away from its equilibrium point by a small amount η in the positive direction. In this case the average value of ΦEBB will be slightly positive. Following this circumstances, the phase detector gain can be defined as the rate of change in E[ΦEBB] due to a small shift η of the probability density function (pdf) around the locked condition:

[ ]

( ^{Φ =} ) _→ ⁺

∂

≡ ∂ | η _{η 0}

η ^{E shift}

K_{bpd EBB} . (3-37)

Under this definition, the value of Kbpd can be approximated as:

Fig. 3-17 BPD linearized model.

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Thus the nonlinear map in the presence of jitter on the reference and DCO clock can be written as:

[ ]

[ ]

[

]

t + =∆ + _j− _T ∆ −

∆ 1 β sgn , (3-40)

where tj is the timing jitter appeared on reference clock. To emphasize the fact that the loop has a non-integer loop delay of D=0.5, the above expression is reference and DCO clock is ∆t^*,∆t^* can assume values only on discrete states:

Z

The probability occupancy of the state n (∆t^*=nNβKT) is defined as:

[

]

43

In general, the ftj can be modeled as a Gaussian process with variance σtj

2 where σtj

2 denotes the jitter variance of reference clock. In formulas

( ) _^

In order to find f∆t, a statistical approach is used as following to obtain the value of qn. From a given state n, ∆t^* might go to state n+1, state n-1 or state n itself, and the transition probabilities from state m to state n is defined as

[

]

P

P_m,_n ≡ ∆ _k^*₊1∈ |∆_k^*∈ . (3-46) Under the assumption that σtj is much smaller than loop quantization step NβKT, the states n with |n|>2 occur with a probability which is negligibly small. Then the state diagram of the system describe in equation 3-41 can be simplified to a three state chain as illustrated in Fig. 3-18.

If f∆t is symmetrical around 0 then q-1=q1, P0,1=P0,-1=1/4 and P0,0=1/2. For the case that the loop stays in the same state at the next time index, there exist two possible situations. For example, it might go from state 0 to state 1 at time index k and stay in state 1 at the next time instance k+1 when ∆tk-1<0. Also, it might start from state 1 at the previous time instance k-1 and stay in state 1 at time index k. However, in this case it can never stay in state 1 at next clock cycle. Thus, by inspection of equation 3-41 and noted that σtj<<NβKT,

Fig. 3-18 State chain to approximating the BBPLL.

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To obtain the relationship between the state probability and transition probability, note that q0 can be expressed as: satisfy the normalization equation

1 1 3-38, the equivalence gain of the binary phase detector is



It should be noted that the above gain expression is defined in the unit of (sec)-1.

It can be simply converted to the expression in the unit of (rad)^-1 by applying the relationship

45

Fig. 3-19(a) and Fig. 3-19(b) show the discrete time model and the corresponding continuous time approximation of the digital loop filter, respectively. Before the phase error output ΦEL of the linearized phase detector is sent to the digital loop filter, the continuous-time signal ΦEL is first sampling by the reference clock, which is indicated with the continuous-to-discrete-time (C/D) block. Assume that ΦEL is a band-limited signal and the effect of aliasing is negligible. Then the sampling process can be replaced by a simple gain factor fREF. In the discrete-time IIR filter, the delay in the loop is modeled by the z^-1 operator defined as z=exp(j2πf/fREF). In Fig. 3-19(a), the signal reconstruction process is represented as a discrete-to-continuous-time (D/C) block. Obviously the DCO holds the frequency constant until the digital loop filter changes its output value. Consequently, the output sequence of the digital filter is reconstructed by the zero-order-hold operation which can be expressed as a sinc function in frequency domain. Finally, the approximated frequency response of

(a)

(b)

Fig. 3-19 (a) Discrete time model and (b) continuous time approximation of the digital loop filter.

46

Fig. 3-20 shows the complete model of the ADPLL during bang-bang phase tracking mode, which is obtained by substituting the different building blocks in Fig. 3-6 with their linear models. The DCO is modeled as integration operation with a gain 2πKDCO. The relationship between the phase of the output signal φOUT and feedback clock φFB is established by the division (1/N) block. The deviation of the loop transfer functions will be done according to the linear model and the phase noise performance will be analyzed later.