ADPLL in Frequency Acquisition Mode

At the beginning of the locking process, the frequency acquisition mode is first activated and the DCO is locked roughly to the desired frequency. During this mode, the integral path of the digital loop filter is disabled (α=0), and the system block diagram can be simplified as shown in Fig. 3-1. The scaling factor βFA

introduced in the figure denotes the forward path gain during frequency acquisition mode. In the frequency domain it controls the gain of the frequency detected in response to the frequency changed at the DCO output. The gain factor βFA also controls several key loop characteristics such as the loop stability, the transient response and the frequency error in the steady state.

In order to investigate in detail how βFA affect the loop behavior, a discrete time z-domain model is build. As mentioned in chapter 2, the block diagram can be rearranged by moving the accumulation operation after the subtractor and places a differential operator on feedback path as illustrated in Fig. 3-2. Two

Fig. 3-1 System block diagram during frequency acquisition mode.

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approximations are used in order to simplify the model. The first is to force the uniform sampling or PLL update rate, despite the presence of a small amount of jitter in the reference clock. This approximation is very accurate since the period deviation due to jitter is several orders of magnitude smaller than the DCO period. The second approximation is the infinite resolution of the phase detection which neglects the fact that the phase information is quantized by the divided DCO clock fDIV4. If the free running frequency of the DCO is ignored and is assumed to be 0, the closed loop transfer can be express as

( ) ( ) where KDCO,C denotes the frequency step per control code of the active varactor bank in the DCO during frequency acquisition mode.

According to the discrete time signal process theorem, the conditions for stability of a causal system can be derived by examining the position of its poles.

For a given system function of a linear and time invariant system, if the outermost pole is included in the unit circle on the pole-zero plot, the system is stable. Considering the system function of the ADPLL in frequency acquisition mode HFA,C(z), the pole-zero plot is illustrated in Fig. 3-3(a) for different KFA. It is clear that the loop stability requires KFA to be less then 1.To gain more clear Fig. 3-2 Equivalent system block diagram during frequency acquisition mode.

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insight into the time domain behavior, the damping factor which is derived from the equivalent continuous time poles by solving z=e^sT is shown in Fig. 3-3(b).

The result shows that for an over damping system, K_FA<0.244 for a critically damped system, KFA=0.244; and for an under damped system, KFA>0.244.

In order to validate the z-domain model of the ADPLL developed here, ADPLL during frequency acquisition mode

0 0.2 0.4 0.6 0.8 1

Fig. 3-4 Simulated time domain response of the ADPLL in frequency acquisition mode with 3 different KFA value.

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the simulation results of the time domain response with an initial frequency error of 5GHz. For KFA=0.5 it shows a fast response with overshooting while a slow response with longer settling time is obtained for KFA=0.08. The result shows a good agreement between simulation and the analytical model.

It should be noted by inspecting the result shown in Fig. 3-4 where some ripples appear on the output frequency in the steady state. This can be explained by taking the quantization effects into consideration. Due to the edge counting nature of the phase detection, the phase error between the reference clock and feedback is quantized with the resolution step determined by DCO clock rate.

When the loop settles, the phase error will be located between two quantization steps, leading to constant output of the phase detection. The phase error will remain unchanged until the accumulated phase error exceeds one quantization step. Then the phase error is corrected by the feedback loop. Thus ripples are generated on the output of phase detector and the output frequency.

Due to the limitation of the capture range, the frequency error after the loop is settled must be taken into consideration before entering the bang-bang phase tracking mode. As mentioned before, the output of the phase detector iterates between two adjacent values when the loop reaches steady state. In other words, the average of the output frequency in steady state indicates the desired clock rate NfREF. Therefore, the frequency offset of the loop can be characterized by the frequency step

C DCO FA FA

RES K

f _, =β _,

∆ . (3-2)

Equation 3-2 suggests that the forward gain βFA should be kept lower to enhance the frequency resolution. Unfortunately, this suggestion is in conflict with the requirement for shortening the locking time. The frequency

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quantization step could be mode finer at the cost of the slower loop response.

Take the critical damping case as an example, substituting KFA=0.244 and fREF=40MHz in equation 3-1, we can obtain ∆fRES,FA=βFAKDCO,C=78.08MHz, which is too large for efficient phase tracking.

To speed up the locking process while keeps the frequency resolution high, two different βFA is used during frequency acquisition mode. A larger value β_FA=8 is first applied to achieve high loop bandwidth and fast frequency tracking.

As the loop settles, the second value βFA=1 is then applied to improve frequency resolution. Since only the coarse tuning bank is active during this mode, KDCO,C

is the frequency variation correspond to one LSB of the coarse tuning bank and is about 4MHz/LSB in this design. Thus form equation 3-1, KFA for βFA=1 and βFA=8 is 0.1 and 0.0125, respectively. At the end of the frequency acquisition mode, the frequency resolution is 4MHz. From the simulation results, the time expended is less than 1µsec in frequency acquisition mode.