Digital Loop Filter and LPM

The digital loop filter consists of proportional path and integral path as shown in Fig. 4-1. The data path in the loop filter is 26 bits wide and represented in two’s complement arithmetic. Fig. 4-12 illustrates the block diagram of the detail implementation of the digital loop filter. It should be noted that the multiplied by α(β) and -α(-β) operation is replaced by selecting the positive or negative value from multiplexer inputs. In order to perform the dynamic loop parameters and modes switching, several multiplexers are introduced in the loop filter. The activity of the loop filter incorporated with these multiplexers during the locking process will be described as following.

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Fig. 4-12 Implementation of the digital loop filter.

At the beginning of the locking process, all memory elements are reset synchronous by asserting a control signal. At first, the fast frequency acquisition mode is activated where only the proportional path is used by set PD_mode to 0.

During the FA mode, the output of the phase detector ΦE is scaled by a value βFA. The scaling operation is implemented in an efficient manner as programmable right-bit-shift operation and the variable value βFA can assume to be a programmable integer value of power of two in the range from 2⁰ to 2³. To further enhance the locking performance, the FA mode is divided into two stages according to the proportional gain βFA.

At the beginning of this mode, a large gain βFA is used to allow the output frequency to lock quickly and roughly to the target frequency. Then the DCO control code CDCO is stored to a temporary register as CDCOd and control signal PD_reset shown in Fig. 4-1 is set to high to reset the phase detector. Finally, the stored control code CDCOd is loaded to the register in integral path by asserting the control signal Load and the smallest allowed gain for βFA is applied to resolve the frequency quantization error left from the proceeding stage.

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After the output frequency is settled, the PT mode is entered. The following events happen at almost the same time: First, the DCO control code C_DCO is sampled at the output of the loop filter and stored to a temporary register. The phase detector is then reset to clear the phase error residue and C_DCOd is loaded to the register in the integral path again. Finally the integral path is switched on by asserting the control signal PD_mode.

During the PT process, the loop parameters, α and β, are dynamically scaled to reduce the locking time. Fig. 4-13 reveals the hardware realization of α and β loop gain factors. At the beginning of the bang-bang phase locking process, both α and β are set to initial values. As LD_gain is asserted, α and β are scaled down by shift right operations and the scaling factors are based on the values stored in the programmable shift registers. It can be seen from Fig. 4-13 that the gain controller can generate 5 different pairs of α and β during locking operation.

To reduce the computation complexity, the multiplications in the loop filter in phase locking mode are implemented as multiplexers controlled by ΦE[7] with both positive and negative inputs of the gain factors α and β.

Fig. 4-13 Implementation of the gain controller

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As mentioned in chapter 2, the time for the control circuit to perform gain scaling is determined by the existence of the locking state. The relationship between the output of the integral path ΨI and ΦE[7] in the locking state can be shown in Fig. 4-14. It should be observed that the increment of the integral path when ΦE[7] is 0 is equal to the decreasing amount while ΦE[7] is 0. This implies that if the loop reaches steady-state condition, the peak or bottom values of Ψ_I will remain unchanged and thus the existence of the locking state can be detected.

Fig. 4-15 shows the implemented LPM. The signal ΦSC indicates that there is a transition on the MSB of the phase detector output Φ_E[7] and also a local

Fig. 4-14 Time diagram of the locking state in PT mode.

Fig. 4-15 Implementation of the LPM.

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maximum or minimum value appears on ΨI. Thus, this operation can be treated as the gradient polarity detector (GPD) of ΨI. The peak-bottom holder stores the peak or bottom values by using the signal ΦSC to clock a shift register. Note that the values stored in the peak-bottom holder should be either two peak values with one bottom value or one peak value with two bottom values. A XOR gate followed by a NOR gate is connected behind the peak-bottom holder which compares the first and third outputs of the flip-flops in the peak-bottom holder.

Thus, the XOR produces an output that indicted the difference between the adjacent peak or bottom values. If the loop is in steady-state, the XOR produces an output with all digits in the bus equal to 0 and thus PD_lock is 1.

The PD_lock indicates that the locking state is reached and the loop gain factors can be scaled immediately. However, the time of switching the gain factors is significant as far as the locking speed is concerned. The time instance for the loop parameters to be adjusted is based on the state of the control signal

Fast frequency acquisition phase 1

Fast frequency acquisition phase 2

Bang-bang phase Tracking

Store control code CDCO

Only proportional path is on (large β)

Reset phase detector Load CDCOd

Only proportional path is on (small β)

Store control code C_DCO Reset phase detector Load C_DCOd

Turn on integral path

Wait for PD_lock=1 Wait for Gain_cahnge=1 Scaling α and β by asserting LD_gain

Stop

< 5 Times

Fig. 4-16 Flowchart of the ADPLL locking process.

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Gain_change. Since the nature of the bang-bang phase locking, the output value of the loop filter oscillates around a fixed value corresponding to target frequency as the loop is in steady-state. The average of the peak and bottom values of integral path output can be assumed as the control code corresponding to the frequency closed to the target frequency. This assumption leads to the using of the average of peak and bottom values as the starting point when the loop gain factor is scaled. The signal Gain_change is raised to high only if the difference between present integral path output and the average of its peak and bottom values is less then α/2. The loop controller will assert LD_gain to adjust the loop gain factors α and β when both transitions on PD_lock and Gain_change are received. Fig. 4-16 summarizes the locking process of the proposed ADPLL.