Architecture of BBPLL

2.1.1 Analog PLL

A great majority of high performance analog PLL are based on the charge-pump PLL structure [5]. The structure of the charge-pump PLL is shown in Fig. 2-1.

The phase frequency detector (PFD) estimates the phase difference between the reference clock fREF and the divided-by-N voltage controlled oscillator (VCO) clock fFB by measuring the time difference between their closest edges and generates either an Up or a Down pulse with width proportional to the time difference measured. The current pulse generated by the charge pump is converted into the control voltage of the VCO at the loop filter. The main task of the loop filter is to suppress the glitches introduced by the charge pump on every phase comparison instance. The loop automatic adjusts the VCO control voltage by the feedback mechanism, so that under locked conditions, the average output

PFD

1/N fREF

fFB

fOUT=fREF×N Up VCO

Down

Charge Pump

Frequency Divider Loop Filter

Fig. 2-1 Typical charge-pump-based PLL.

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frequency establishes an exact relationship to the reference input frequency.

With proper design of the loop parameters, the performance of the charge-pump PLL can meet the requirements of different applications including Ethernet receivers, disk drive read/write channels, wireless transceivers, high-speed memory interfaces. Unfortunately, big challenges to the implementation of low-jitter analog synthesizers are coming from future system and technology trends.

The explosive growth of today’s telecommunication market has brought an increasing demand for low cost, reduced power consumption and more functionality of the silicon chip. These requirements are driving an unprecedented degree of integration of digital and analog circuitry on the same die forming what is known as System-on-Chip (SoC).

As the technology paradigm shifts into the nano-meter CMOS arena, the advanced process presents the new integration opportunities but complicates the implementation of traditional RF and analog circuits. For example, charge-pump-based PLL implementations in the deep-submicron CMOS may encounter capacitor leakage, current mismatch, and limited dynamic range under low supply voltage, leading to higher noise floor and spurious tone emission.

Moreover, the high degree of integration allows more digital switching noise to be coupled into the high-precision analog section through the power supply network and the low-resistance substrate. This degrades the noise signal to noise ratio of the analog circuit and the problem gets worse with the scaling down of the supply voltage.

On the other hand, migrating to the digitally intensive frequency synthesizer can benefit from the advantages of the digital design, including robustness against process-voltage-temperature (PVT) variation and substrate

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noise, higher flexibility of the loop filter design, fast design turnaround cycles, ease of testability, smaller silicon area and less power dissipation, which can get better with each process node. Consequently, digital intensive or digital assistance approached of the frequency synthesizers have drawn tremendous research efforts recently [2]-[4]. In next section, some of the state of the art all digital synthesizer will be illustrated.

2.1.2 All-Digital PLL

Due to the lack of the low-jitter digitally controlled oscillator (DCO), all digital PLLs really took off in practical high-performance RF applications in the past decade. Recently, a digitally controlled oscillator, which deliberately avoids any analog tuning voltage controls, was first ever presented in [2] for RF wireless applications. The phase domain ADPLL which uses this DCO is also reported in [3]. Its block diagram is shown in Fig. 2-2. Excellent phase noise performance and fine frequency resolution is achieved through the LC-tank based DCO and high-speed Σ∆ dithering. The variable phase RV[i] is determined by counting the

Fig. 2-2 Block diagram of the ADPLL architecture proposed in [3]

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number of rising clock transitions of the DCO oscillator clock, while the reference phase RR[k] is obtained by accumulating the frequency command word (FCW) with every rising edge of the retimed reference clock CKR. The phase error is resolved by subtracting RV[i] from RR[k] and then filtered by a digital loop filter. Finally, the output of the filter is fed to the normalized DCO to adjust the output frequency.

Due to the edge counting nature, the quantization resolution is limited by the DCO clock period. For wireless applications, a finer resolution is required.

This is achieved by using the time to digital converter (TDC), which measures the fractional time difference between the reference clock and the next rising edge of the DCO clock. It has a resolution of a single inverter delay, which is better than 40ps in the deep-submicrometer CMOS process. In order to accomplish good phase noise performance, great care must be taken with the TDC layout matching and the accuracy of the DCO period normalization factor for the output of TDC.

In [4] an all digital bang-bang PLL (BBPLL) with spread-spectrum capability is presented for the application of memory controller. The structure of the BBPLL is addressed in Fig. 2-3, where the phase information between the reference clock Fref and the feedback clock Fdiv is estimated by a simple binary phase detector (BPD). Its operation is equivalent to a one bit quantizer for the phase error. Since the BPD is sensitive only to the polarity of the phase information, it may suffer from long locking time with large initial frequency error.

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According to the method of the phase sensing, the ADPLL can be roughly classified into two major categories: linear phase detection and binary phase detection. [3] is belong to linear phase detection while [4] may represent the latter one. The ADPLL with linear phase detection may resort to the TDC or more complicated phase detector design compared to the one with binary phase detector. However, its counterpart that utilizes the binary phase detection suffers from larger output jitter, higher spur energy and longer settling time.