PAC2

As shown in Fig. 4-1, the PAC2 is implemented as a high speed counter with the rollover effect as described above. The counter can be implemented quite easily using register-type circuits such as the flip-flops, and a wide variety of design

63

exists. There are two major types of flip-flop based counter according to the clocking mechanism of the registers, namely asynchronous counter and synchronous counter.

The simplest asynchronous counter circuit is a D type flip-flop with input fed from its own inverted output. This counter increase once for every clock cycle and takes two clock cycles to overflow, so every cycle the output of the counter will alternate between 0 and 1. It should be noted that the counter creates an output clock at exactly half the frequency of the input clock and hence it also perform a divided-by 2 operation. The generated signal can clock the next counter stage if more than one stage is connected in series to extend the range of the counter.

An example of a 4-bit asynchronous down counter along with its time diagram is illustrated in Fig. 4-6. This down counter can be easily transformed to an up counter by simply inverting the output of each stage (Q1~Q4). Note that it can be shown from Fig. 4-6 that each counter stage working at half of the frequency of previous stage and the rising edge of each output (Q1~Q4) does not align to each other. The existence of the unavoidable propagation delay of the

Fig. 4-6 Asynchronous counter.

64

flip-flop results in the unstable outputs as the overflows "ripple" from stage to stage. In the case where the instantaneous count is important, the timing skew between stages will cause incorrect counting results. Besides, the increasing of the input frequency and the counter length will worsen the situation. If each stage of the output of an asynchronous counter is sampled by the same clock phase, for an L bits asynchronous counter with the D flip-flop which have a clock to output delay of tc-q and a setup time of tsetup, the maximum operating frequency fin,max can be expressed as

( )

max ,

−

− +

= c q setup

in Lt t

f . (4-6)

To solve this issue in the applications where a stable count value is important across several bits, the synchronous counters could be used. Rather then the asynchronous counters in which each flip-flop is triggered by the output of the preceding stage, the flip-flops of synchronous counters are all triggered by the same clock source. Fig. 4-7 shows a 4-bit synchronous counter composed of logic gates and flip-flops. The time diagram of the counter is also shown in Fig.

4-7 and it can be observed that the signal edge of each stage (Q1~Q4) is aligned to the input clock fin. The synchronous output of this counter solves the issue of

Fig. 4-7 Synchronous counter.

65

unsettled output while carrier signal propagates in asynchronous counter circuit at the expense of larger power consumption. Because all the flip-flops in the synchronous counter circuit operate at the frequency which is as high as input clock frequency, the synchronous counters consume much more dynamic power than asynchronous counters. In addition to the issue of power consumption, the synchronous also suffer the problem of slower operating speed. The maximum operation speed for an L bit synchronous counter can be determined by the time for the carrier signal to propagate from the first stage (LSB) to the last stage (MSB) and could be derived as:

( )

[ ]

max

, = _c−q + −1 _AND + _XOR + _setup ⁻

in t L t t t

f , (4-7)

where tc-q, tsetup, tAND and tXOR are the clock to output delay of the flip-flops, the setup time of the flip-flops, the gate delay of the AND gate tAND, and the gate delay of the XOR gate, respectively.

To solve the edge skewing issue and preserve the advantages of high speed operation and low power consumption of the asynchronous counter, a skew-insensitive high speed counter is proposed. Before presenting the complete architecture and operation of the high speed counter, a simple example of a 1-bit counter will be shown to give a clear insight into the operation principle of the high speed counter.

Fig. 4-8 shows a simple example of a 1-bit counter with proposed sample phase generator. The counter consists of a basic 1-bit flip-flop based asynchronous counter, a D type latch to perform sample phase generation and a D type flip-flop to fetch the output from the 1-bit asynchronous counter. The time diagram illustrated in Fig. 4-8 shows the relationship among the sample phase Φs, the input clock fin, the asynchronous counter output D1, the generated

66

sampling clock S1 and the fetched output Q1. The regions divided by the shadowed area indicate the connection between the time interval when the asynchronous output D1 is valid and the time slots where the rising edge of the sample phase Φ_s appears. In other words, if the rising edge appears in R₀, the corresponding output should locate in the same region and thus Q1 should be 1.

The shadowed area would be a rectangular form without the skew edge, but in reality the existence of the clock to output delay tc-q of the flip-flop leads to the misalignment between the rising edges of f_in and D₁ which results in the distortion of the shape.

The introduced D type latch not only generates a delay version of the sample clock Φs, but also adjusts the sampling point so that the flip-flop can fetch the correct value from D₁. The sample phase Φ_s ispostponed by the D latch controlled by fin and a sampling clock S1 which has a rising transition when the f_in is 0 is produced. It should be noted that when Φ_s goes to high, the output D₁ become valid after the most recently rising transition of fin delaying by tc-q. Similarly, the output D₁ remains valid until the f_in changes from low to high which results in the state transition on D1.

Time

Fig. 4-8 Example of a 1-bit counter with sample phase generator.

67

To examine the design margin and the robustness of this topology, the operation condition and the propagation delay of each component must be taken into consideration. Due to the physical phenomenon of metastability, the input data for a flip-flop must have settled by a setup time tsetup for the data to be reliably sampled. In the case where Φs goes high before the D latch becomes transparent, the upper bound of input frequency fin,max can be determined according to the setup time requirement:

(

)

in t t t

f

−

− + −

= 2

1

max

, . ( 4-8)

From equation 4-8, it can be seen that the maximum input frequency of this counter depends on the setup time tsetup of the D type flip-flop, the clock to output delay tc-q of the D type flip-flop, and the clock to output delay tc-ql of the D latch. In another case where Φs goes high after the D latch becomes transparent, the circuit may suffer from the metastability problem when the rising edge of Φs is close to the rising edge of fin. To solve this issue, a D type flip-flop is introduced which makes the rising edge of the input signal of the latch always leads the rising edge of fin, and the modified circuit is shown in Fig.

4-9.

After the detail description of the proposed 1-bit counter, it is

Fig. 4-9 Example of a 1-bit counter with an additional D type flip-flop.

68

straightforward to construct the counter with more bits by simply connecting the 1-bit counters in series. The complete block diagram and time diagram of the high speed counter is shown in Fig. 4-10. The operation principle of this architecture follows the one of the 1-bit counter as mentioned before.

Due to the non-bound relationship between fREF and fDIV4, it is quite likely that under certain condition, the flip flop may face the metastability problem.

During metastability, the output of the flip flop could be undefined at a given clock cycle which is not acceptable for proper system operation. This problem can be solved by passing the lower frequency signal through a series of flip flops which are clocked by the higher frequency clock. The overall probability of metastability condition at output of the system decreases exponentially with the number of the flip flop. Furthermore, the probability of a metastable state of a single flip flop can be reduced by increasing the speed of the flip flop. In order

Fig. 4-10 Bock diagram and time diagram of the proposed high speed counter.

69

to reduce the probability of a metastable state, the sampling in the first stage of sampling phase generator is performed by a pair of sense amplifier based flip flops [13], and Fig. 4-11 shows the schematic of the sense amplifier based flip flop. The advantages of this topology are the fast response time and low power consumption.

When fREF comes in to fetch the contents in PAC2, the sampling phase S1

for the 1^st stage of the asynchronous counter is generated by resampling fREF

through 2 D flip-flops to avoid metastability. S1 is then postponed by D-latchs DL1-DL3, which are toggled by the falling edge of the 1^st – 3^rd stage divider outputs fD1-fD3, to generate the sampling phases S2 – S4. Thus, a minimum setup time of 4TDCO-tcq can be guaranteed when retrieving the contents of the ripple counter.

Fig. 4-11 Schematic of the tactical flip flop [13]

70

The sampling scheme of the LSB ΦFB[0] is slightly different form the topology illustrated in Fig. 4-8, where the sampling signal S1 is generated by a D latch rather then a flip flop. By taking the advantage of short clock to output delay of the sense amplifier based flip flops, the asynchronous counter output fD1

can be sampled just before the transition occurs without violating the hold time condition of the output flip flop. In this way, the upper bound of input frequency as specified in equation 4-8 can be released and the additional flip flop shown in Fig. 4-11 can be removed.

From Fig. 4-10, it should be noted that the 5 MSBs asynchronous outputs fD4-fD8 are sampled by the same signal S4. From the simulation results, the delay time of the sampling signal S4 satisfies the time requirement for the “carry”

signal to propagate from the fourth stage to the last stage of the divider chain, so further generation of the sampling phase is unnecessary.