RF circuits have been widely designed and fabricated in CMOS processes due to the advantages of high integration and low cost for mass production. ESD, which has become one of the most important reliability issues in IC products, must be taken into consideration during the design phase of all ICs [1]-[4], including the RF front-end circuits. Without ESD protection circuits at all I/O pads, the RF performance of a wireless transceiver can be easily damaged by ESD stresses, because RF front-end circuits are always fabricated in advanced CMOS processes. Usually the I/O pads are connected to the gate terminal of MOS transistor or silicided drain/source terminal, which leads to a very low ESD robustness if no ESD protection design is applied to the I/O pad. Once the RF front-end circuit is damaged by ESD, it can not be recovered and the RF functionality is lost. Therefore, on-chip ESD protection circuits must be provided for all I/O pads in ICs. Two common chip-level ESD test standards are human-body-model (HBM) and machine-model (MM) ESD test standards [5], [6]. HBM and MM ESD tests are used to evaluate the ESD robustness of the IC when it is touched by the charged human body or charged machine. The equivalent circuits of HBM and MM ESD tests are shown in Figs. 1.1(a) and 1.1(b), respectively. In order to protect the internal circuits against ESD stresses, ESD protection circuits must be provided at all I/O pads. Fig. 1.2 shows the concept of whole-chip ESD protection design.
(a) (b) Fig. 1.1. Equivalent circuits of (a) HBM, and (b) MM, ESD tests.
Fig. 1.2. Typical design of on-chip ESD protection circuits in CMOS ICs.
Fig. 1.3 shows the ESD-test pin combinations. ESD stresses may have positive or negative voltages on an I/O pin with respect to the grounded VDD or VSS pin. The typical ESD specifications for commercial IC products in HBM and MM are 2 kV and 200 V, respectively. For comprehensive ESD verification, the pin-to-pin ESD stresses and VDD-to-VSS ESD stresses had also been specified to verify the whole-chip ESD robustness, which are shown in Figs. 1.4 and 1.5, respectively.
(a) (b)
(c) (d)
Fig. 1.3. ESD-test pin combinations: (a) positive-to-VSS mode (PS-mode), (b) negative-to-VSS mode (NS-mode), (c) positive-to-VDD (PD-mode), and (d) negative-to-VDD (ND-mode).
(a) (b) Fig. 1.4. Pin-to-pin ESD tests: (a) positive mode, and (b) negative mode.
(a) (b) Fig. 1.5. VDD-to-VSS ESD tests: (a) positive mode, and (b) negative mode.
The typical on-chip double-diode ESD protection scheme is shown in Fig. 1.6, which two ESD diodes at I/O pad are co-designed with the power-rail ESD clamp circuit to prevent internal circuits from ESD damage [7]. In Fig. 1.6, a P+/N-well diode (DP) and an N+/P-well diode or an N-well/P-substrate diode (DN) are placed at input pad or output pad. When the DP
and DN are under forward-biased condition, they can provide discharge paths from I/O pad to VDD and from VSS to I/O pad, respectively.
Fig. 1.6. Typical double-diode ESD protection scheme.
Under positive-to-VDD mode (PD-mode) and negative-to-VSS mode (NS-mode) ESD stresses, ESD current is discharged through the forward-biased DP and DN, respectively. To avoid the ESD diodes from being operated under breakdown condition during positive-to-VSS mode (PS-mode) and negative-to-VDD mode (ND-mode) ESD stresses, which results in a substantially lower ESD robustness, the power-rail ESD clamp circuit is used between VDD and VSS to provide ESD current paths between the power rails [8]. Thus,
ESD current is discharged from the I/O pad through the forward-biased DP to VDD, and discharged to the grounded VSS pin through the turn-on efficient power-rail ESD clamp circuit during PS-mode ESD stresses, as shown in Fig. 1.7(a). Similarly, ESD current is discharged from the VDD pin through the turn-on efficient power-rail ESD clamp circuit and the forward-biased DN to the I/O pad during ND-mode ESD stresses, as shown in Fig. 1.7(b).
(a)
(b)
(c)
Fig. 1.7. ESD current paths in the typical double-diode ESD protection scheme under (a) PS-mode, (b) ND-mode, and (c) pin-to-pin, ESD stresses.
During pin-to-pin ESD stresses, ESD current flows from the zapped I/O pad through the forward-biased DP, the power-rail ESD clamp circuit, and the forward-biased DN to the grounded I/O pad, as shown in Fig. 1.7(c). Under VDD-to-VSS ESD tests, ESD current flows through the power-rail ESD clamp circuit between VDD and VSS. Since the power-rail ESD clamp circuit works independently between VDD and VSS, its parasitic effects do not have any impact on the internal circuits. With the turn-on efficient power-rail ESD clamp circuit, the ESD diodes can be assured to be operated in the forward-biased condition under all ESD test modes, which leads to higher ESD robustness.
Although using power-rail ESD clamp circuit between VDD and VSS does not cause any effect on the internal circuits, applying ESD protection devices at the I/O pads inevitably introduce some negative impacts to circuit performance due to their parasitic effects. The main parasitic effect caused by ESD protection devices which deteriorates the high-frequency performance is the parasitic capacitance. Since the input signal swing is small at the RF input pad, it is sensitive to the shunt parasitic capacitance of ESD protection devices. Therefore, the parasitic capacitance of the ESD protection device at the RF input pad is strictly limited. For the RF transmitter, the devices in the output stage are implemented with large dimensions to transmit the output signals with large enough signal power. With proper design, the devices in the RF output stage can be used to protect the RF output pad against ESD stresses. Thus, ESD protection design for the input pad of the RF receiver is more challenging than that for the output pad of the RF transmitter.
A typical request on the maximum loading capacitance of ESD protection device for a 2-GHz RF input pin was specified as only ~200 fF, which includes the parasitic capacitances of bond pad and ESD protection device [9]. Recently, the negative impacts of ESD protection devices to RF circuit performance had been investigated [10], [11], which had demonstrated that the RF performance such as power gain and noise figure are significantly degraded by the parasitic capacitance of ESD protection devices. The impacts become more serious as the operating frequency of RF front-end circuits increases. Thus, the parasitic capacitance of ESD protection device must be minimized in ESD protection design for high-frequency applications. Generally, ESD protection circuits cause RF performance degradation with several undesired effects, which are will be discussed in the following.
Parasitic capacitance is one of the most important design considerations for RF ICs.
Conventional ESD protection devices with large dimensions have the parasitic capacitance which is too large to be tolerated for RF front-end circuits. As shown in Fig. 1.8, the parasitic
capacitance of ESD protection devices causes signal loss from the pad to ground. Moreover, the parasitic capacitance also changes the input matching condition. Consequently, the noise figure is deteriorated and the power gain is decreased.
Noise factor is one of the most important merits for RF receivers. Since the RF receiver is a cascade of several stages, the overall noise factor of the RF receiver can be obtained in terms of the noise factor and power gain of each stage in the receiver. For example, if there are m stages cascaded in the RF receiver, the total noise factor of the RF receiver can be expressed as [12] where Fi and Gpi are the noise factor and the power gain of the i-th stage, respectively.
According to (1.1), the noise factor contributed by the first stage is the dominant factor to the total noise factor of the RF receiver (Ftotal). With the ESD protection circuit added at the input pad to protect the RF receiver IC against ESD damages, the ESD protection circuit becomes the first stage in the RF receiver IC, which is shown in Fig. 1.9. For simplicity, only the first two stages, which are the ESD protection circuit and the low-noise amplifier (LNA), are taken into consideration, as shown in Fig. 1.10. The overall noise factor (FLNA_ESD) of the LNA with ESD protection circuit is
_ ESD protection and LNA circuits, respectively. Thus, the noise factor of the ESD protection circuit must be minimized, because it directly increases the total noise factor of the RF receiver and the increased noise factor can not be suppressed by the power gains of succeeding stages. Moreover, the signal loss due to the ESD protection circuit would also cause power gain degradation in RF circuits.
Fig. 1.8. Signal loss at input and output pads of IC with ESD protection devices.
Another negative impact caused by the ESD protection circuit is the input impedance mismatching, which is particularly critical for narrow band RF circuits. With the ESD protection circuit added at the input node, the original input matching condition is changed by the parasitic capacitance from the ESD protection circuit. As a result, the center frequency of the narrow band RF circuit is shifted and the power gain is decreased due to impedance mismatching. The impedance mismatching due to ESD protection devices can be mitigated by co-designing the ESD protection circuit and the input matching network. With the co-design of ESD protection scheme and input matching network, the operating frequency can be tuned to the desired frequency. However, the noise figure is definitely increased after ESD protection circuit is added because more devices indicate more noise sources.
Besides the impacts caused by ESD protection device on RF front-end circuits, the parasitic capacitance of the ESD protection device causes signal loss from the pad to ground, which decreases the signal swings. Moreover, RC delay is another impact caused by the ESD protection circuit. With the ESD protection circuit added to the input and output pads, the parasitic capacitance and parasitic resistance from the ESD protection device and the interconnection introduce RC delay to the input and output signals. Thus, the rising and falling time of the signals at the I/O pads with ESD protection become longer.
Fig. 1.9. Block diagram of an ESD-protected RF receiver.
Fig. 1.10. Block diagram of an LNA with ESD protection circuit. VS, RS, and RL denote the source voltage, source resistance, and load resistance, respectively.
In addition to parasitic capacitance, the requirements of ESD protection device characteristics under ESD stresses introduce some design considerations. To provide effective ESD protection, the voltage across the ESD protection device during ESD stresses should be carefully designed. First, the trigger voltage and holding voltage of ESD protection device must be designed lower than the gate-oxide breakdown voltage of MOS transistors to prevent the internal circuits from damage before the ESD protection device is turned on during ESD stresses. Second, the trigger voltage and holding voltage of the ESD protection device must be higher than the power-supply voltage of the IC to prevent the ESD protection devices from being mis-triggered under normal circuit operating conditions. Moreover, the turn-on resistance of ESD protection device should be minimized in order to reduce the joule heat generated in the ESD protection device and the voltage across the ESD protection device during ESD stresses. As CMOS process is continuously scaled down, the power-supply voltage is decreased and the gate oxide becomes thinner, which leads to reduced gate-oxide breakdown voltage of MOS transistor. Typically, the gate-oxide breakdown voltage is decreased to only ~5 V in a 65-nm CMOS process with gate-oxide thickness of ~15 Å. As a result, the ESD design window, defined as the difference between the gate-oxide breakdown voltage of the MOSFET and the power-supply voltage of the IC, becomes narrower in nanoscale CMOS technologies [13]. Furthermore, ESD protection circuits need to be quickly
turned on during ESD stresses in order to provide efficient discharge paths in time. In summary, ESD protection design becomes more challenging in nanoscale CMOS technologies.