Traditional Designs of High-Voltage-Tolerant ESD Clamp Circuits

Some high-voltage-tolerant ESD clamp circuits realized with only 1×VDD devices have been reported. Fig. 6.2 shows a 2×VDD-tolerant design. Under ESD stress conditions, the ESD current will discharge through M1 and M2. Under normal circuit operating conditions, the voltage divider (M3 and M4) will keep the node 1×VDD at half of the 2×VDD voltage.

Therefore, all gate-to-source and gate-to-drain voltages stay below 1×VDD voltage in the long term. It should be noted that the gate-to-bulk voltage across M5 is greater than 1×VDD voltage at steady state. However, since the conductive channel is induced under the gate of M5, the voltage across the gate oxide of such a device is not more than 1×VDD voltage.

Therefore, all low-voltage devices prevent from gate-oxide reliability concern.

Fig. 6.2. Traditional design of 2×VDD-tolerant ESD clamp circuit.

A 3×VDD-tolerant ESD clamp circuit operated under 3.3-V bias with 1.2-V low-voltage devices is shown in Fig. 6.3. The ESD clamp device is realized by a substrate-triggered SCR (STSCR) with three diodes in series. Under normal circuit operating conditions, the diode-connected PMOS (M1, M2, and M3) are used as the voltage divider to bias the ESD detection circuit. The nodes 1 and 2 in the ESD detection circuit are biased at 1.1 V and 2.2 V, respectively. The node 3 is biased to 1.2-V VDD through the resistor R1. The M5 is turned off, so there is no trigger current generated from the ESD detection circuit into the SCR device. All devices in this ESD detection circuit are free from gate-oxide reliability issue.

During ESD stress to ESD bus with VSS grounded, the capacitor Mc2 will couple some

ESD charge to node 2 to turn on M7. The RC delay of R2 and Mc1 in the ESD detection circuit will keep the gate of M6 (node 4) at lower voltage level. The VDD is initially floating with 0 V as ESD stress to ESD bus. The gate of M5 and M6 are initially at low voltage level, so the M5 and M6 can be quickly turned on to generate the substrate-triggered current into the substrate of SCR device. Then, the SCR device can be turned on to discharge ESD current from ESD bus to VSS.

Fig. 6.3. Traditional design of 3×VDD-tolerant ESD clamp circuit.

The other 3×VDD-tolerant power-rail ESD clamp circuit is shown in Fig. 6.4. The 3×VDD-tolerant power-rail ESD clamp circuit is also realized with 1.2-V low-voltage devices to operate at 3.3 V without the risk of gate-oxide reliability. The ESD clamp device is realized by STSCR with two diodes in series. Under normal circuit operating conditions, the nodes 2 and 3 in the ESD detection circuit are biased at 1.1 V and 2.2 V, respectively. The gate voltage of M7 (node 1) is biased at 0.6 V, so that M7 is turned on and the node 9 is biased at 1.1 V. The gate-to-source voltage of M10 is 0 V, and therefore M10 is turned off.

There is no trigger current generated from the ESD detection circuit into the ESD clamp device. In the ESD detection circuit, the gate voltage of M3 and M12 is biased at 3.3 V through the resistor R1. Therefore, the M3 and M12 are kept in off state. Owing to the turned-off M3, there is no current path from ESD bus through the PMOS M3, M2, and M1 to

VSS, so that M2 is kept at off state. Therefore, the source-to-gate voltage of M2 is less than the threshold voltage of the 1.2-V PMOS transistor (Vtp), so the voltage level of node 5 is kept between 2.2 V and 2.2+|Vtp| V. With the same reason, M1 is also kept at off state, and the gate voltage of M5 and M8 (node 4) is kept between 1.1 V and 1.1+|Vtp| V, so that M5 and M8 are both at on state, and therefore the voltage level of nodes 6 and 10 are biased at 2.2 V.

The gate-to-source voltages of M4, M6, and M11 are nearly 0 V, so these transistors are all at off state. In this situation, all 1.2-V devices are free from gate-oxide reliability issue under normal circuit operating conditions.

When ESD voltage is conducted to the ESD bus with VSS grounded, the RC delay of R1 and Mc1 in the ESD detection circuit keeps the gates of M3 and M12 (node 7) at low voltage level, as compared with the ESD bus. The M3 and M12 can be turned on, and therefore, the voltage levels at nodes 5 and 10 rise rapidly. The voltage levels at nodes 2 and 3 are initially floating with 0 V, so the M2 and M11 can be turned on, and the voltage levels at nodes 4 and 9 also rise rapidly. The M7 is in on state, and the voltage level at node 2 will rise with the voltage level at node 9. However, the RC delay keeps the node 2 in a low voltage level to ensure that M10 is in the turned-on state during ESD stress event. Moreover, the gate voltage of M4 (node 4) is higher than its source voltage (node 2). Therefore, M4 is turned on to keep the voltage level at node 6 in a low voltage level. The gate-to-drain voltage of M6 is ~0 V. The voltage level at node 3 is one threshold voltage higher than the voltage level at node 6. Furthermore, the gate voltage of M8 (node 4) is as high as its source voltage (node 10), so that M8 is in off state to ensure that the voltage level at node 3 can be kept in a low voltage level, as compared with node 10. Therefore, the M10, M11, and M12 can be quickly turned on to generate the substrate-triggered current into the trigger node (node 8) of the SCR under ESD stress conditions.

Fig. 6.4. Another traditional design of 3×VDD-tolerant ESD clamp circuit.

The other 2.5-V-tolerant ESD clamp circuit by using 1.2-V devices is shown in Fig. 6.5.

The ESD clamp device has a stacked NMOS (STNMOS) with a substrate-triggered design.

The STNMOS is formed by stacked NMOS transistors (M4 and M5) with a 1.2-V gate oxide in a 0.13-μm CMOS process. The gate of M5 is biased at the 1.2-V VDD through a resistor to avoid the gate-oxide reliability issue, and the gate of M4 is connected to the VSS to ensure the off state of the STNMOS during normal circuit operating conditions. Therefore, STNMOS will be kept off without gate-oxide reliability during normal circuit operating conditions.

With a 1.2-V VDD power supply voltage, the ESD bus could be charged up to 2.5 V by the 2.5-V input signals at the I/O pad. With a maximum voltage level of 2.5 V on the ESD bus, the gate of M3 will be biased at 2.5 V through resistor R1, and the gate of M1 and M2 will be biased at 1.2 V through a resistor. Therefore, M2 and M3 are kept off, and M1 is turned on to bias the substrate of STNMOS at VSS. There is no trigger current generated from the ESD detection circuit into the STNMOS, so STNMOS is guaranteed to be kept off under normal circuit operating conditions. The source-to-gate voltage of M2 is less than the

threshold voltage of the 1.2-V PMOS transistor (Vtp), so the source voltage of M2 is kept between VDD and VDD+|Vtp|. In this situation, all 1.2-V devices are free from the gate-oxide reliability issue under normal circuit operating conditions.

Under positive ESD stresses at ESD bus with VSS grounded, the gate of M3 is kept at a low voltage due to the RC delay of R1 and Mc1 in the ESD detection circuit. VDD is initially floating with 0 V. The gate of M2 is kept at a low voltage level to keep M2 at the on state.

Therefore, M2 and M3 can be quickly turned on by ESD energy to generate the substrate-triggered current into the substrate of STNMOS. After the base-emitter voltage of the lateral npn BJT in the STNMOS is greater than its cut-in voltage, the STNMOS will be triggered into its snapback region. Therefore, the ESD current can be discharged from the ESD bus through the lateral npn BJT in the STNMOS to VSS.

Fig. 6.5. Another traditional design of 2×VDD-tolerant ESD clamp circuit.