SCR Structures

The SCR device was traditionally implemented in the stripe and double-sided layout.

Under ESD stresses, ESD current primarily flows through the two edges of SCR, while other two edges do not discharge ESD current, but still contribute to parasitic capacitance. The proposed SCR device with waffle layout structure can discharge ESD current through four edges. Therefore, the FOM of VMM/CESD can be maximized by using the waffle layout structure to implement SCR.

The MOS transistors in waffle layout structures had been studied [70]. The waffle layout structures for diodes had also been proposed to reduce its parasitic capacitance for ESD protection in high-speed I/O applications [71]. In this section, SCR realized in the waffle structure is investigated in a 0.18-µm CMOS process.

3.2.1. SCR With Stripe Layout

The conventional stripe SCR (SSCR) is shown in Fig. 3.3(a), which is implemented in the stripe and double-sided layout. The anode of SSCR is electrically connected to P+

diffusion and N+ diffusion, which are formed in the N-well. The cathode is electrically connected to N+ diffusion and P+ diffusion, which are formed in the nearby P-well. The shaded regions in the cross-sectional view in Fig. 3.3(a) are the regions of shallow trench isolation in CMOS process. The equivalent circuit of the SCR device, which consists of a PNP and a NPN bipolar transistors, is shown in Fig. 3.4. Because of the reverse-biased junction between the N-well and P-well regions, the SCR device is turned off under normal circuit operating conditions. When a positive ESD stress is zapped from the anode with cathode grounded, the high voltage drop between the anode and cathode causes breakdown on the base-collector junction of BJT. In the meantime, PNP and NPN transistors will be

turned on by the breakdown current. With the positive-feedback mechanism [62] of the cross-coupled bipolar transistors, the SCR device becomes highly conductive. Therefore, the ESD current can be quickly discharged by the SCR device.

(a)

(b)

Fig. 3.3. Device cross-sectional view and layout top view of (a) stripe SCR (SSCR), and (b) waffle SCR (WSCR).

Fig. 3.4. Equivalent circuit of the SCR device.

While a positive ESD stress is zapped from the anode with cathode grounded, the discharge path of the SCR device is P+/N-well/P-well/N+. The ESD currents primarily flow through only two edges of the N-well in SSCR. The other two edges of the N-well in SSCR are unused. While a negative ESD stress is zapped from the anode with cathode grounded, the discharge path in the SCR device is the parasitic N-well/P-well diode. The ESD currents still flow through only two edges of the N-well in SSCR. The other two edges of the N-well in SSCR are not used to bypass ESD current.

3.2.2. SCR With Waffle Layout

Fig. 3.3(b) shows the proposed waffle SCR (WSCR). The anode of WSCR is electrically connected to P+ diffusion and N+ diffusion, which are formed in the N-well. The cathode surrounds the anode, and is electrically connected to N+ diffusion and P+ diffusion, which are formed in the nearby P-well. WSCR can discharge both positive and negative ESD current in four edges of the device.

3.2.3. Modified SCR With Stripe Layout

In Figs. 3.3(a) and 3.3(b), the trigger voltage (Vtrigger) of the SSCR or WSCR under positive stress is the breakdown voltage of the N-well/P-well junction. The modified SCR can improve the turn-on efficiency and reduce the trigger voltage. As shown in Fig. 3.5(a), the trigger P+ diffusion is added across the N-well/P-well junction in the stripe p-modified SCR (SPMSCR) to reduce the junction breakdown voltage. When a positive or negative ESD stress is zapped from anode to cathode, the ESD currents primarily flow through two edges of the device.

Since the large trigger diffusion often increases the parasitic capacitance, the SPMSCR was implemented with separated trigger diffusion areas to evaluate the device characteristics and ESD robustness. The trigger diffusion areas of SPMSCR1 and SPMSCR2 are 123.2 µm² and 242.48 µm², respectively, as listed in Table 3.1.

(a)

(b)

(c)

Fig. 3.5. Device cross-sectional view and layout top view of (a) stripe p-modified SCR (SPMSCR), (b) waffle p-modified SCR (WPMSCR), and (c) waffle n-modified SCR (WNMSCR).

Table 3.1

Comparisons on Measured Device Characteristics of SCR Under Different Test Structures

Trigger

3.2.4. Modified SCR With Waffle Layout

With the trigger P+ diffusion across the N-well/P-well junction, the proposed waffle p-modified SCR (WPMSCR) is shown in Fig. 3.5(b). The WPMSCR can discharge both positive and negative ESD current through the four edges of the device, so the FOM of VMM/CESD can be increased. The WPMSCR was also implemented with separated trigger diffusion areas to evaluate the device characteristics and ESD robustness. The trigger diffusion areas of WPMSCR1, WPMSCR2, and WPMSCR3 are 70.24 µm², 140.48 µm², and 264.96 µm², respectively, as listed in Table 3.1.

The trigger P+ diffusion can be replaced by the trigger N+ diffusion. As shown in Fig.

3.5(c), the trigger N+ diffusion is added across the N-well/P-well junction of the waffle n-modified SCR (WNMSCR) to characterize the ESD robustness and high frequency performances.

3.2.5. Metal Routing Strategy

The top metal (metal 6) in a 0.18-µm CMOS process, which is far from the grounded P-substrate, is used for routing on the anode of each SCR device. This is critical to reduce the parasitic capacitance at the I/O pad in RF circuits. The bottom metal (metal 1) is used for routing on the cathode of each SCR device. With such a metal routing strategy, the parasitic capacitance between the anode and cathode of SCR device can be further reduced [22].

All the aforementioned devices have been fabricated in a 0.18-µm CMOS process. The size of each SCR device in layout is kept at 60.62 x 60.62 µm². The FOM of VMM/CESD of SCR devices in different layout styles have been measured to investigate their effectiveness.