High-Voltage-Tolerant ESD Clamp Circuit

Fig. 6.9 shows the test circuit of the 2×VDD-tolerant ESD clamp circuit. The main ESD current discharging path consists of the double-triggered SCR (DTSCR) with a diode in series (DTSCR+diode). Although there is a parasitic SCR path in the DTSCR+diode structure, the parasitic SCR has the higher holding voltage due to the parasitic N-well resistor in the parasitic SCR path. Therefore, the DTSCR+diode structure has high enough holding voltage to prevent from latchup issue. The SCR device and the forward biased diode can sustain high ESD level within a small silicon area in CMOS process. Fig. 6.10(a) shows the Hspice-simulated results of the 2×VDD-tolerant ESD clamp circuit under normal circuit operating conditions. Under simulations, the ESD clamp device in Fig. 6.9 is replaced by two 100-Ω resistors, which are between the trigger PMOS Mt2 (Mt1) and VDD (VSS), to simplify the simulation. With 2-V 2×VDD and grounded VSS, node B (1×VDD) of the circuit in Fig. 6.9 is 1 V. In other words, all low-voltage devices sustain only 1 V. Therefore, all low-voltage devices prevent from gate-oxide overstress issue. The total leakage current is only ~0.15 μA at 25 °C. As the temperature varies from 25 °C to 100 °C, Fig. 6.10(b) summarizes the simulated results under normal circuit operating conditions. The node B (1×VDD) voltage is exactly at 1 V, even if the temperature varies from 25 °C to 100 °C.

Fig. 6.9. Implementation of 2×VDD-tolerant ESD clamp circuit with 2×VDD-tolerant ESD detection circuit and SCR-based ESD clamp device.

Fig. 6.11 shows the simulated transient responses of the 2×VDD-tolerant ESD clamp circuit. With the voltage disturbance on 2×VDD line, the ESD detection circuit is accidentally turned-on under normal circuit operating condition. However, the MOS capacitors can be restored to logic high to turn off the trigger currents. Therefore, this design can prevent from latch events.

(a)

(b)

Fig. 6.10. Hspice-simulated results of 2×VDD-tolerant ESD clamp circuit under normal power-on condition: (a) at 25 °C, and (b) summary within 25 °C and 100 °C.

Fig. 6.11. Hspice-simulated transient responses of 2×VDD-tolerant ESD clamp circuit.

When a positive fast-transient ESD voltage is applied to 2×VDD line with VSS grounded, the trigger currents will pass through the initial-on PMOS (Mt1 and Mt2) to trigger the DTSCR device. The RC delay keeps the trigger PMOS (Mt1 and Mt2) turned-on to continuously generate the trigger currents. Finally, the DTSCR device can be fully turned-on into holding state to discharge ESD currents from 2×VDD line to VSS. Fig. 6.12(a) shows the simulation results of the ESD detection circuit under 5-V ESD-like pulse zapping to simulate the fast transient voltage of human-body-model (HBM) ESD events, and Fig. 6.12(b) summarizes that under different voltage pulse zapping. The trigger currents can be successfully generated.

(a)

(b)

Fig. 6.12. Hspice-simulated results of 2×VDD-tolerant ESD detection circuit under ESD-like pulse zapping: (a) 5-V pulse, and (b) summary of different voltage pulse.

The 2×VDD-tolerant ESD clamp devices with and without the ESD detection circuit have been fabricated in a 1-V 65-nm CMOS process. The size of ESD clamp devices are design to pass the general requirement of 2-kV (4-kV) HBM ESD level, so the size of DTSCR and diode are all selected to be 25 μm (50 μm). Besides, Mt1 and Mt2 of ESD detection circuit are also selected to be 25 μm (50 μm). The layout top view of one test pattern with the high-voltage-tolerant ESD clamp circuit is shown in Fig. 6.13.

80 µm

DTSCR+

Diode ESD Detection Circuits

Fig. 6.13. Layout top view of one test pattern with high-voltage-tolerant ESD clamp circuit.

6.4.4. Experimental Results

The I-V characteristics of the circuits are measured by using transmission line pulsing (TLP) system with 10-ns rise time and 100-ns pulse width. Figs. 6.14, 6.15, and 6.16 show the TLP-measured I-V curves of the ESD clamp circuits.

Fig. 6.14 shows the TLP-measured I-V curves of the stand-alone ESD clamp devices without the ESD detection circuit. The trigger voltages (Vt1) of each stand-alone ESD clamp devices without the ESD detection circuit are 11.8 V. The secondary breakdown currents (It2) of ESD clamp devices are 1.6 A and 2.8 A, respectively.

Fig. 6.15 shows the TLP-measured I-V curves of the ESD clamp circuits with the 25-μm trigger PMOS (Mt1 and Mt2). The trigger voltages (Vt1) of the ESD clamp circuits with 25-μm and 50-μm DTSCR are reduced to 6.7 V and 7.3 V, respectively. The secondary

breakdown currents (It2) of ESD clamp devices are kept 1.6 A and 2.8 A, respectively.

Fig. 6.16 shows the TLP-measured I-V curves of the ESD clamp circuits with the 50-μm trigger PMOS (Mt1 and Mt2). The trigger voltages (Vt1) of the ESD clamp circuits with 25-μm and 50-μm DTSCR are reduced to 6 V and 6.5 V, respectively. The secondary breakdown currents (It2) of ESD clamp devices are 1.6 A and 2.9 A, respectively. These data are summarized in Table 6.1.

Fig. 6.14. TLP I-V curves of (a) 25-μm and (b) 50-μm DTSCR+diode without trigger PMOS.

0 2 4 6 8 10 12

0 2 4 6 8 10 12

The HBM ESD robustness of the fabricated ESD clamp circuits are evaluated by the ESD simulator. Fig. 6.17(a) shows the HBM ESD robustness of all ESD clamp circuits, and Fig. 6.17(b) summarizes the It2 levels of all ESD clamp circuits. All ESD clamp devices with 25-μm (50-μm) size can achieve 2.6-kV (4.8-kV) HBM ESD robustness. These data are also summarized in Table 6.1.

The dc I-V characteristics of ESD clamp circuits are measured by using Tek370 curve tracer. The measured dc holding voltages (Vhold) of all ESD clamp circuits under room temperature are ~2.8 V, as shown in Fig. 6.18. All the dc holding voltages exceed 2×VDD (2 V) with 0.8-V margin, which is very safe from latchup event under normal circuit operating condition.

The standby leakage current of the stand-alone 25-μm (50-μm) DTSCR in series with diode under 2-V bias at room temperature is only 4 nA (5 nA). Even if the 25-μm trigger PMOS is applied to the 25-μm (50-μm) DTSCR in series with diode, the standby leakage current under 2-V bias at room temperature is 148 nA (170 nA). As the 50-μm trigger PMOS is applied to the 25-μm (50-μm) DTSCR in series with diode, the standby leakage current under 2-V bias at room temperature is 264 nA (293 nA). Although the leakage current is increased with the insert of ESD detection circuit, the trigger voltage can be significantly reduced to effectively protect the core circuits. Therefore, the ESD clamp circuit of this work can provide the excellent ESD robustness with low standby leakage current by using only low-voltage devices.

25 50

Fig. 6.17. (a) HBM ESD robustness and (b) secondary breakdown current of ESD clamp circuits.

(a)

(b)

Fig. 6.18. Measured dc holding voltages of ESD clamp circuits with (a) 25-μm and (b) 50-μm ESD clamp devices under room temperature.

Table 6.1

The new 2×VDD-tolerant ESD clamp circuit by using only low-voltage devices with low standby leakage current and high ESD robustness for SoC applications with mixed-voltage I/O interfaces has been successfully designed and verified in a 65-nm CMOS process. The 2×VDD-tolerant ESD clamp circuit can operate without gate-oxide reliability issue, and the leakage current is only in the order of 100 nA under normal circuit operating condition. The HBM ESD robustness of the test patterns with 25-μm and 50-μm ESD clamp devices can achieve 2.6 kV and 4.8 kV, respectively. In addition, the new ESD detection circuit shows significant help on increasing the turn-on speed of ESD clamp device. With trigger currents generated from the ESD detection circuit, the trigger voltage of the SCR-based ESD clamp device can be reduced as compared with the stand-alone SCR device. The TLP-measured trigger voltage of the ESD clamp device with the ESD detection circuit is ~6 V. Besides, the holding voltage of each ESD clamp circuits is ~2.8 V, which is much greater than 2×VDD voltage (2 V). Therefore, there is no latchup concern in this design. The new ESD clamp circuit by using only low-voltage devices with very low standby leakage current and high ESD robustness is the useful circuit solution for on-chip ESD protection design with mixed-voltage I/O interfaces in SoC applications.

Chapter 7